VLVnT 2015 – Very Large Volume Neutrino Telescope 14 – 16 September 2015, University...

VLVnT 2015 – Very Large Volume Neutrino Telescope 14 – 16 September 2015, University “Sapienza”, Rome - Italy

Carlo A. Nicolau – INFN Sez. [email protected]

KM3NET-IT TOWERDATA ACQUISITION AND DATA TRANSPORT

ELECTRONICSCARLO A. NICOLAU

ON BEHALF OF THEKM3NET – ITALY COLLABORATION

Outline:

• KM3NeT-Italy Layout

• Tower Layout

• Data and Timing Link

• Floor Electronics

• Optical Module Electronics

• Conclusions



KM3NeT-IT Tower – Data Acquisition and Data Transport Electronics

375 VDC

KM3NeT – IT Layout

Shore Laboratory in Capo Passero harbour

Control Room

Guest House

DAQPower Feeding

Equipment

ON-SHORE OFF-SHORE

20 x opt. fibers

up to 10 kV

~100 km

MVC Opt. Splitter

JunctionBox

JunctionBox

KM3NeTString DUs

TB

FCM

FCM

FCM

FCMKM3NeT-ITTowers




Tower Layout

TB

FCM

FCM

FCM

FCM

Tower Base

Floor #1

Floor #2

Floor #13

Floor #14

JunctionBox

375 VDC

2 opt. fibers

Detection Unit Characteristics

• Design based on NEMO• All data to shore approach• Tower

• 14 Floors• Vertical floor spacing is 20m• Star connection topology

• Base Module• Optical link distribution DWDM• Power control and distribution

• Floor• 8 m long• Floor Control Module Vessel• 6 Optical Modules• 2 Hydrophones

• Optical Module• Single 10” PMT• Front End Module• LED Beacon (2 per floor)




Tower Base

TOWER BASE

E

MAN

IFO

LD

1

2

...

JUN

CTIO

N B

OX

E

OO

13

14

FLOOR 1

FLOOR 14

E

OELECTRONICS POD

POWER POD

PHOTONICS POD

E O E O

E O

E O E O

E O

Tower Base Module

• Contains 3 vessels• Photonics Pod• MUX/DEMUX lambdas from/to floors

• Power Pod• Distribution, Control, Monitoring

• Electronics Pod• Communication, Monitoring,

Laser beacon control

uCAD

V-I M

onito

r

375

V

F1 F2 …. F14

Power Pod Photonics Pod

DRO

PAD

D

OptAmp

OptAmp

BTS

BTS

To Floors & E. Pod

From Floors & E. Pod

Electronics Pod

Tower Base Control Module

Board(same as Floor)

PSS Board375 V

Power PodRS232

Photonics PodRS232

HydrophoneAES3

Laser Beacon Controller




Floor Layout

FCM

KM3NeT-ITFloor

To/fromother5 OMs

To/from2 x Digital St. Hydr.

Front End Module Board

HVPSU

OpticalModule

Center - FloorVessel

PSSBoard

Floor Control Module Board

375 V

To/f

rom

Tow

er B

ase

Power, ClockData IN/OUT

12V, ClockAES3




Data & Timing Link Model

GPS

GPS

Tim

e D

istr

ibuti

on

DWDMMUX

DWDMMUX~100km

FCM

KM3NeT-ITFloor

• Point to point link

• Each Floor is assigned a couple of

lambdas (rx/tx) in DWDM spectrum

• Standard component

• Lambda drift monitoring and tuning

• Fully synchronous link

• Clock, Data and Timing embedded

in a single 8b/10b stream

• Each device is time-stamp aware

• Fixed latency

• Round-trip time monitoring

+ pre-deployment calibration

GPS TimeDistrib. FCM FEM

Phase Noise JitterLab Measures

(Agilent E5052B SSA)

10 MHz38.5 ps rms

80 MHz9.7 ps rms

Recovered80 MHz

35.2 ps rms

Sampling Clock200 MHz

52.3 ps rms

DAQFPGA (short)




Center Floor Electronics

OM #0

RS232 PortCompass (+3.3V)

RS232 PortExt Instrument(Isolated, +12V)

2 x Digital AES3Hydrophone

Spare RS232 Port(Isolated, +12V)

OM #1OM #2

OM #3OM #4

OM #5

375 V

Power Connectors1.2 V, 3.3 V, 5 V, 12 V(V & I Measurement)

Spartan 6 FPGA• Fixed-latency transceiver• No external PLL• 6 x OM interfaces (clock distribution, data rx / tx), 2 x AES3• Host a microblaze-based system on-chip

• Slow control communication• Slow-control functions (OM power control and monitoring)• Voltage and Current Monitoring• I2C bus, Serial Ports• Flash Read/Write

• Full remote safe reprogrammability with multiboot (3 full images + data)

Power Supply System

Floor Control Module

H/TSensor

DC/DC Converters 375 V -> 5 V 5 V -> 12 V 5 V -> 1.2V, 2.5V, 3.3V




Optical Module Layout

HVPSU

CLOCK

DIN / VCC

DOUT / GND

TO/

FRO

M F

CM

USER CONN(Power, AIN, GPIO, I2C, RS232, ...)

GATE In

PMT signal

HVPSUPowerControlFeedback

LED BeaconPowerTrigger

Front EndModule

PMTLPFADC14 bit

200 Mhz

L0-Trigrising and falling

thresholds

FIFO2048 Samples+ timestamp

Timestamping

8b/10b enc.To FCM

20 Mbps

Data Acquisition Chain

current pulses~3 ns rising time

voltage pulses~15 ns rising time

Samples14 bit / 200 Mhz

Timestamp (5 ns) + SamplesEvents: Timestamp (5 ns) Waveforms




Front End Module

Analog Front End• Differential shaping filter• Linear• Fully passive• Adjustable Offset

T/H I2C sensor

Slow DACs/ADCsAFE conditioning (pedestal)HVPSU Control / monitoringLED-Beacon control

LED Beacon VDC/DC based generator (24V)

Clock out driver

DC/DCs LMZ10501

Line Interface• Clock (LVDS)• DATA IN/OUT (LVDS)• GND/VCC on COM

Fast ADC TI ADS4149Differential 200 MHz 14 bit

Spartan 6LX25 FPGA• Level 0 trigger (zero-skipping)• Programmable threshold• Programmable number of tail samples• 2 ksample FIFO• Timestamping• Lossless compression on spe• Line interface encode/decode• Rate monitoring in realtime• Sustained spe rate up to ~150kHz• Microblaze-based SOC• Full remote safe reprogrammability with multiboot (3 images + data)

DAQ Core

FSL

H/T SensorSensirion SHT21

3 x Ext. Serial Ports

Micron N25Q032FlashI2C

16bit DAC

16bit ADC

HVPSU Control& monitor

uBlazeSPI

UART

16bit DAC

16bit ADC

AFE Control & Monitor

AD414914bit/200MHz

Config.

64kB




Front End Module

Data acquired by tower #0 in 2014/nov

nhits : ~150k mean : 9.5 pC std : 6.2 pC

spe peak

~1/4 speEquivalent threshold

Pedestal

Linear analog frontend fixed relation ADC channel vs input current

( ~0.0228 pC per ADC channel)




Conclusions

Dissipative linearvoltage regulators Active low noise DC/DC

5 different boards 2 boards

7 processing units3 architectures(Xilinx FPGA, Microchip PIC,Freescale DSP)

1 processing unit1 architecture(Xilinx FPGA w/ uBlaze MCU)

Previous Design(NEMO)

KM3NeT-IT

Dissipative linearvoltage regulators Active low noise DC/DC

2 x 8 bit ADC (100 Msps)Non-Linear Analog Comp.

Single ADC 14 bitLinear Front end

2 processing units2 architectures(Xilinx FPGA, Freescale DSP)

1 processing unit1 architecture(Xilinx FPGA w/ uBlaze MCU)Same codebase as FCM

Floo

r Con

trol

Mod

ule

Fron

t End

Mod

ule

Easier code maintainance• From VHDL / DSPASM / C To VHDL / C++• One common code-base for all slow-control functions and communication

Simplified elaborationNo need to “decompress” signalsSimplified calibration processNo need to calibrate each single FEM at different temperatures

Reduced power consumptionFEM : From ~2 W / OM To ~1 W / OMFCM: From ~7.5 W To ~3 W

Simplified integration, lower cost




Thank You

VLVnT 2015 – Very Large Volume Neutrino Telescope 14 – 16 September 2015, University...

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