VLSI_Design_-_Unit II - Part I
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Transcript of VLSI_Design_-_Unit II - Part I
![Page 1: VLSI_Design_-_Unit II - Part I](https://reader033.fdocuments.net/reader033/viewer/2022061123/5474c91db4af9f89048b456d/html5/thumbnails/1.jpg)
NMOS & CMOS inverter and gates
Unit II
![Page 2: VLSI_Design_-_Unit II - Part I](https://reader033.fdocuments.net/reader033/viewer/2022061123/5474c91db4af9f89048b456d/html5/thumbnails/2.jpg)
NMOS & CMOS Digital Logic Inverter
S. B. Sivasubramaniyan MSEC, Chennai
![Page 3: VLSI_Design_-_Unit II - Part I](https://reader033.fdocuments.net/reader033/viewer/2022061123/5474c91db4af9f89048b456d/html5/thumbnails/3.jpg)
CMOS Inverter
It is the basic building block of any digital system We had discussed the operation of the circuit
earlier
S. B. Sivasubramaniyan MSEC, Chennai
![Page 4: VLSI_Design_-_Unit II - Part I](https://reader033.fdocuments.net/reader033/viewer/2022061123/5474c91db4af9f89048b456d/html5/thumbnails/4.jpg)
CMOS Inverter - Operation
S. B. Sivasubramaniyan MSEC, Chennai
![Page 5: VLSI_Design_-_Unit II - Part I](https://reader033.fdocuments.net/reader033/viewer/2022061123/5474c91db4af9f89048b456d/html5/thumbnails/5.jpg)
CMOS Inverter – Operation
S. B. Sivasubramaniyan MSEC, Chennai
![Page 6: VLSI_Design_-_Unit II - Part I](https://reader033.fdocuments.net/reader033/viewer/2022061123/5474c91db4af9f89048b456d/html5/thumbnails/6.jpg)
CMOS Inverter - inference
The output voltage levels are 0 and VDD. This shows the signal swing is maximum
The static power dissipation is zero A low resistance path exists between output and ground and
output and VDD The low resistance path is independent of W/L ration of the
transistor The input resistance is infinite. Thus the inverter can drive
large number of similar inverters but the delay rises accordingly
S. B. Sivasubramaniyan MSEC, Chennai
![Page 7: VLSI_Design_-_Unit II - Part I](https://reader033.fdocuments.net/reader033/viewer/2022061123/5474c91db4af9f89048b456d/html5/thumbnails/7.jpg)
The Voltage Transfer Characteristics
Repetition of the above graphical procedure for intermediate values gives rise to voltage transfer characteristics
The current equations of the two transistors in the two regions of operation is given by
S. B. Sivasubramaniyan MSEC, Chennai
' 20
1
2
,
DN n I tn on
o I tn
Wi k v V v v
L
for v v V
2'1
2
,
DN n I tnn
o I tn
Wi k v V
L
for v v V
![Page 8: VLSI_Design_-_Unit II - Part I](https://reader033.fdocuments.net/reader033/viewer/2022061123/5474c91db4af9f89048b456d/html5/thumbnails/8.jpg)
The Voltage Transfer Characteristics
The current equations of the two transistors in the two regions of operation is given by
S. B. Sivasubramaniyan MSEC, Chennai
2' 1
2
,
DP p DD I tp DD o DD op
o I tp
Wi k V v V V v V v
L
for v v V
2'1
2
,
DP p DD I tpp
o I tp
Wi k V v V
L
for v v V
![Page 9: VLSI_Design_-_Unit II - Part I](https://reader033.fdocuments.net/reader033/viewer/2022061123/5474c91db4af9f89048b456d/html5/thumbnails/9.jpg)
The Voltage Transfer Characteristics
The CMOS inverter is usually designed to have the equal threshold voltage and
We know, The electron mobility is 2 to 2.5 times higher than that of holes
so to make
The width of the p-channel devices is made 2 to 2.5 times larger
Note: Both devices are designed to have equal Length
S. B. Sivasubramaniyan MSEC, Chennai
' 'n p
n p
W Wk k
L L
' '&n n ox p p oxk C k C
' 'n p
n p
W Wk k
L L
![Page 10: VLSI_Design_-_Unit II - Part I](https://reader033.fdocuments.net/reader033/viewer/2022061123/5474c91db4af9f89048b456d/html5/thumbnails/10.jpg)
The Voltage Transfer Characteristics
The width of the two devices are related by
S. B. Sivasubramaniyan MSEC, Chennai
' 'n p
n p
W Wk k
L L
n ox p oxn p
W WC C
L L
n n p pW W n pL L
p n
n p
W
W
![Page 11: VLSI_Design_-_Unit II - Part I](https://reader033.fdocuments.net/reader033/viewer/2022061123/5474c91db4af9f89048b456d/html5/thumbnails/11.jpg)
The Voltage Transfer Characteristics
When this is accomplished, we say that the CMOS inverter is symmetric
The Voltage transfer characteristic will be symmetric
S. B. Sivasubramaniyan MSEC, Chennai
![Page 12: VLSI_Design_-_Unit II - Part I](https://reader033.fdocuments.net/reader033/viewer/2022061123/5474c91db4af9f89048b456d/html5/thumbnails/12.jpg)
The Voltage Transfer Characteristics
To determine VIH, we need to equate the current of QN and QP
QN operates in the triode region and QP operates in the saturation region
Equating the currents, we get
S. B. Sivasubramaniyan MSEC, Chennai
2 20
1 1
2 2DD I tn I tn oV v V v V v v
![Page 13: VLSI_Design_-_Unit II - Part I](https://reader033.fdocuments.net/reader033/viewer/2022061123/5474c91db4af9f89048b456d/html5/thumbnails/13.jpg)
The Voltage Transfer Characteristics
Differentiate both sides relative to VI, and substitute
We get,
Substitute,
S. B. Sivasubramaniyan MSEC, Chennai
& 1oI IH
I
dvv V
dv
2DD
o IH
Vv V
&2DD
I IH o IH
Vv V v V
![Page 14: VLSI_Design_-_Unit II - Part I](https://reader033.fdocuments.net/reader033/viewer/2022061123/5474c91db4af9f89048b456d/html5/thumbnails/14.jpg)
The Voltage Transfer Characteristics
We get,
Similarly
From VIL and VIH, we can determine Noise Margins
S. B. Sivasubramaniyan MSEC, Chennai
15 2
8IH DD tV V V
13 2
8IL DD tV V V
H OH IHNM V V
13 2
8H DD tNM V V
L IL OLNM V V
13 2
8L DD tNM V V
![Page 15: VLSI_Design_-_Unit II - Part I](https://reader033.fdocuments.net/reader033/viewer/2022061123/5474c91db4af9f89048b456d/html5/thumbnails/15.jpg)
The Voltage Transfer Characteristics
Symmetrical transistors assumptions gave rise to identical noise margins
S. B. Sivasubramaniyan MSEC, Chennai
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Problem
For a CMOS inverter with matched MOSFETs having Vt = 1 V, find
VIL , VIH and the noise margins if VDD = 5V
S. B. Sivasubramaniyan MSEC, Chennai
![Page 17: VLSI_Design_-_Unit II - Part I](https://reader033.fdocuments.net/reader033/viewer/2022061123/5474c91db4af9f89048b456d/html5/thumbnails/17.jpg)
Solution
We know,
Substituting, we get
Similarly,
S. B. Sivasubramaniyan MSEC, Chennai
15 2
8IH DD tV V V
15 5 2 1
8IHV 2.875IHV V
13 2
8IL DD tV V V 13 5 2 1 2.125
8ILV V
![Page 18: VLSI_Design_-_Unit II - Part I](https://reader033.fdocuments.net/reader033/viewer/2022061123/5474c91db4af9f89048b456d/html5/thumbnails/18.jpg)
Solution
We know,
Substituting, we get
Similarly,
S. B. Sivasubramaniyan MSEC, Chennai
13 2
8H DD tNM V V
13 5 2 1
8HNM 2.1HNM V
L HNM NM
![Page 19: VLSI_Design_-_Unit II - Part I](https://reader033.fdocuments.net/reader033/viewer/2022061123/5474c91db4af9f89048b456d/html5/thumbnails/19.jpg)
Problem
Consider a CMOS inverter with , (W/L)n = 20, (W/L)p = 40, , and VDD = 10 V. For , find the maximum current that the inverter can sink while remains
S. B. Sivasubramaniyan MSEC, Chennai
2tn tpV V V 22 20 /n ox p oxC C A V
I DDv V0.5Vov
![Page 20: VLSI_Design_-_Unit II - Part I](https://reader033.fdocuments.net/reader033/viewer/2022061123/5474c91db4af9f89048b456d/html5/thumbnails/20.jpg)
Solution
Sinking current is taken care by NMOS transistor For , NMOS transistor will operate in the
triode region (?) The current equation is given by
The maximum current for , will occur when
S. B. Sivasubramaniyan MSEC, Chennai
20
1
2tnDN n ox I on
Wi C v V v v
L
0.5ov V
0.5ov V
0.5ov V
![Page 21: VLSI_Design_-_Unit II - Part I](https://reader033.fdocuments.net/reader033/viewer/2022061123/5474c91db4af9f89048b456d/html5/thumbnails/21.jpg)
Solution
Substituting, we get
S. B. Sivasubramaniyan MSEC, Chennai
20
1
2tnDN n ox I on
Wi C v V v v
L
2120 20 10 2 0.5 0.5
2DNi
1.55DNi mA
![Page 22: VLSI_Design_-_Unit II - Part I](https://reader033.fdocuments.net/reader033/viewer/2022061123/5474c91db4af9f89048b456d/html5/thumbnails/22.jpg)
Problem
An inverter fabricated in a 1.2 m CMOS technology uses the minimum possible channel length (i.e., ). If Wn = 1.8 m, find the value of Wp that would result in QN and QP being matched. For this technology,
. Also, calculate the value of the output resistance of the inverter when
S. B. Sivasubramaniyan MSEC, Chennai
1.2n pL L m
2 280 / , 27 / , 0.8 & 5n p tn DDk A V k A V V V V V
o OLv V
![Page 23: VLSI_Design_-_Unit II - Part I](https://reader033.fdocuments.net/reader033/viewer/2022061123/5474c91db4af9f89048b456d/html5/thumbnails/23.jpg)
Solution We know,
Substituting, we get
S. B. Sivasubramaniyan MSEC, Chennai
pn
p n
W
W
1.8 p
p nW
1.8 p
p n
k
W k
1.8 27
80pW
5.4pW m
![Page 24: VLSI_Design_-_Unit II - Part I](https://reader033.fdocuments.net/reader033/viewer/2022061123/5474c91db4af9f89048b456d/html5/thumbnails/24.jpg)
Solution
When , NMOS transistor actually provides the path of low resistance given by,
S. B. Sivasubramaniyan MSEC, Chennai
1DSN
n DD tnn
rW
k V VL
o OLv V
2
1
1.880 5 0.8
1.2
DSNr AV
V
0.001984DSN
Vr
A
1.984DSNr k
![Page 25: VLSI_Design_-_Unit II - Part I](https://reader033.fdocuments.net/reader033/viewer/2022061123/5474c91db4af9f89048b456d/html5/thumbnails/25.jpg)
Assignment
Show that the threshold voltage Vth of a CMOS inverter is given by
Where,
S. B. Sivasubramaniyan MSEC, Chennai
1
DD tp tn
th
r V V VV
r
pp
nn
Wk
Lr
Wk
L
![Page 26: VLSI_Design_-_Unit II - Part I](https://reader033.fdocuments.net/reader033/viewer/2022061123/5474c91db4af9f89048b456d/html5/thumbnails/26.jpg)
Dynamic Operation
The speed of digital system is characterized by the propagation delay of the individual gates employed in the chip
The inverter propagation delay is the basic parameter with which the propagation delay of the whole system is specified
Here we are going to discuss about the propagation delay of the basic inverter
S. B. Sivasubramaniyan MSEC, Chennai
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Dynamic Operation
It is assumed that the input is driven by a pulse with zero rise time and zero fall time
The inverter propagation delay is the basic parameter with which the propagation delay of the whole system is specified
S. B. Sivasubramaniyan MSEC, Chennai
![Page 28: VLSI_Design_-_Unit II - Part I](https://reader033.fdocuments.net/reader033/viewer/2022061123/5474c91db4af9f89048b456d/html5/thumbnails/28.jpg)
Dynamic Operation
S. B. Sivasubramaniyan MSEC, Chennai
![Page 29: VLSI_Design_-_Unit II - Part I](https://reader033.fdocuments.net/reader033/viewer/2022061123/5474c91db4af9f89048b456d/html5/thumbnails/29.jpg)
Dynamic Operation - Assumptions
We assume the transistors to be matched This makes tpHL and tpLH to be same Calculating any one of the parameter will help us to
obtain the other We will calculate tpHL For which, we assume that at the instant t = 0+ the
output voltage is at VDD Now transistor QN is ON which would sink large current
S. B. Sivasubramaniyan MSEC, Chennai
![Page 30: VLSI_Design_-_Unit II - Part I](https://reader033.fdocuments.net/reader033/viewer/2022061123/5474c91db4af9f89048b456d/html5/thumbnails/30.jpg)
Dynamic Operation
The characteristics is shown in the figure
S. B. Sivasubramaniyan MSEC, Chennai
![Page 31: VLSI_Design_-_Unit II - Part I](https://reader033.fdocuments.net/reader033/viewer/2022061123/5474c91db4af9f89048b456d/html5/thumbnails/31.jpg)
Dynamic Operation
Substituting the expression for current we get,
S. B. Sivasubramaniyan MSEC, Chennai
DN oi dt Cdv
20
1
2n DD t o on
Wk V V v v dt Cdv
L
20
12
nn o
DD t o
Wk
dvLdt
C V V v v
![Page 32: VLSI_Design_-_Unit II - Part I](https://reader033.fdocuments.net/reader033/viewer/2022061123/5474c91db4af9f89048b456d/html5/thumbnails/32.jpg)
Dynamic Operation
S. B. Sivasubramaniyan MSEC, Chennai
20
1
2
nn o
DD to
DD t
Wk
dvLdt
C V V vv
V V
20
1
2
nn o
DD to
DD t
Wk
dvLdt
C V V vv
V V
![Page 33: VLSI_Design_-_Unit II - Part I](https://reader033.fdocuments.net/reader033/viewer/2022061123/5474c91db4af9f89048b456d/html5/thumbnails/33.jpg)
Dynamic Operation
S. B. Sivasubramaniyan MSEC, Chennai
![Page 34: VLSI_Design_-_Unit II - Part I](https://reader033.fdocuments.net/reader033/viewer/2022061123/5474c91db4af9f89048b456d/html5/thumbnails/34.jpg)
Dynamic Operation
Integrating the equation between the limits, VDD – Vt and VDD/2, we get
Also tpHL is denoted as tpHL2
S. B. Sivasubramaniyan MSEC, Chennai
22 2
0
1
2
DD
DD t
Vnn o
pHL V VDD t
oDD t
Wk
dvLt
C V V vv
V V
![Page 35: VLSI_Design_-_Unit II - Part I](https://reader033.fdocuments.net/reader033/viewer/2022061123/5474c91db4af9f89048b456d/html5/thumbnails/35.jpg)
Dynamic Operation
We know,
S. B. Sivasubramaniyan MSEC, Chennai
2
2
1ln 1
12
DD
DD t
V
pHL
n DD t oDD t V V
Ct
Wk V V vL V V
2
1ln 1
dx
axax x
21
, &2 o
DD t
Here a x vV V
![Page 36: VLSI_Design_-_Unit II - Part I](https://reader033.fdocuments.net/reader033/viewer/2022061123/5474c91db4af9f89048b456d/html5/thumbnails/36.jpg)
Dynamic Operation
Simplifying,
Total time,
S. B. Sivasubramaniyan MSEC, Chennai
2
3 4ln DD t
pHLDD
n DD t
V VCt
W Vk V VL
1 2pHL pHL pHLt t t
2
3 4ln
12
DD ttpHL
DDn DD t n DD t
V VCV Ct
W W Vk V V k V VL L
![Page 37: VLSI_Design_-_Unit II - Part I](https://reader033.fdocuments.net/reader033/viewer/2022061123/5474c91db4af9f89048b456d/html5/thumbnails/37.jpg)
Dynamic Operation
Simplifying,
Taking the typical value for threshold voltage
And substituting here, we get
S. B. Sivasubramaniyan MSEC, Chennai
3 42 1
ln2
DD ttpHL
DD t DDn DD t
V VVCt
W V V Vk V VL
0.2t DDV V1.6
pHL
n DDn
Ct
Wk V
L
![Page 38: VLSI_Design_-_Unit II - Part I](https://reader033.fdocuments.net/reader033/viewer/2022061123/5474c91db4af9f89048b456d/html5/thumbnails/38.jpg)
Dynamic Operation
For tpLH, the same expression applies except for
Which has to replaced by
S. B. Sivasubramaniyan MSEC, Chennai
nn
Wk
L
pp
Wk
L
![Page 39: VLSI_Design_-_Unit II - Part I](https://reader033.fdocuments.net/reader033/viewer/2022061123/5474c91db4af9f89048b456d/html5/thumbnails/39.jpg)
Propagation Delay
For tp,
S. B. Sivasubramaniyan MSEC, Chennai
2pLH pHL
p
t tt
![Page 40: VLSI_Design_-_Unit II - Part I](https://reader033.fdocuments.net/reader033/viewer/2022061123/5474c91db4af9f89048b456d/html5/thumbnails/40.jpg)
Propagation Delay - Inference
For tp to be lower, Capacitance should be small Kn’ should be high (W/L) should be high VDD should be high A trade off between above parameters is done to ensure lower propagation
delay
S. B. Sivasubramaniyan MSEC, Chennai
![Page 41: VLSI_Design_-_Unit II - Part I](https://reader033.fdocuments.net/reader033/viewer/2022061123/5474c91db4af9f89048b456d/html5/thumbnails/41.jpg)
Problem
A CMOS inverter in a VLSI circuit operating from a 10 V supply has
If the total effective load capacitance is 15 pF. Find tp
S. B. Sivasubramaniyan MSEC, Chennai
20, 40,n p
W W
L L
22 20 / , 2 .n ox p ox tn tpC C A V V V V
![Page 42: VLSI_Design_-_Unit II - Part I](https://reader033.fdocuments.net/reader033/viewer/2022061123/5474c91db4af9f89048b456d/html5/thumbnails/42.jpg)
Solution
We Know
S. B. Sivasubramaniyan MSEC, Chennai
1.6p
n DDn
Ct
Wk V
L
1.6 15
20 20 10p
pFt 6pt ns
![Page 43: VLSI_Design_-_Unit II - Part I](https://reader033.fdocuments.net/reader033/viewer/2022061123/5474c91db4af9f89048b456d/html5/thumbnails/43.jpg)
Solution
Alternate
S. B. Sivasubramaniyan MSEC, Chennai
3 42 1ln2
t DD tp
DD t DDn DD t
n
V V VCt
W V V Vk V VL
122 15 10 3 10 4 22 1ln
20 20 8 10 2 2 10pt
6pt ns
![Page 44: VLSI_Design_-_Unit II - Part I](https://reader033.fdocuments.net/reader033/viewer/2022061123/5474c91db4af9f89048b456d/html5/thumbnails/44.jpg)
Assignment
Solution
S. B. Sivasubramaniyan MSEC, Chennai
0.8 , 0.8 , 0.8pLH pHL pt ns t ns t ns
![Page 45: VLSI_Design_-_Unit II - Part I](https://reader033.fdocuments.net/reader033/viewer/2022061123/5474c91db4af9f89048b456d/html5/thumbnails/45.jpg)
Dynamic Power Dissipation – contd.
The expression for propagation delay can also be derived by taking the average of the currents at VDD (operating point E) and at VDD/2 (operating point F)
S. B. Sivasubramaniyan MSEC, Chennai
![Page 46: VLSI_Design_-_Unit II - Part I](https://reader033.fdocuments.net/reader033/viewer/2022061123/5474c91db4af9f89048b456d/html5/thumbnails/46.jpg)
Dynamic Power Dissipation – contd.
Device current at E is the saturation current of NMOS transistor, given by
Device current at F is the triode region current of NMOS transistor, given by
S. B. Sivasubramaniyan MSEC, Chennai
20
1
2 n DD tDNn
Wi k V V
L
2
1
2 2 2pHL
DD DDn DD tDN t
n
V VWi k V V
L
![Page 47: VLSI_Design_-_Unit II - Part I](https://reader033.fdocuments.net/reader033/viewer/2022061123/5474c91db4af9f89048b456d/html5/thumbnails/47.jpg)
Dynamic Power Dissipation – contd.
Average current
The propagation delay is given by (high to low)
S. B. Sivasubramaniyan MSEC, Chennai
0
1
2 pHLDN av DN DN ti i i
pHL
DN av
C Vt
i
/ 2DDpHL
DN av
C Vt
i
![Page 48: VLSI_Design_-_Unit II - Part I](https://reader033.fdocuments.net/reader033/viewer/2022061123/5474c91db4af9f89048b456d/html5/thumbnails/48.jpg)
Dynamic Power Dissipation – contd.
Propagation delay
Simplifying, we get
S. B. Sivasubramaniyan MSEC, Chennai
2
2
/ 2
1 1 12 2 2 2 2
DDpHL
DD DDn DD t n DD t
n n
C Vt
V VW Wk V V k V V
L L
2 2
12 2 2 2
DDpHL
DD t DD DDn DD t
n
CVt
V V V VWk V V
L
![Page 49: VLSI_Design_-_Unit II - Part I](https://reader033.fdocuments.net/reader033/viewer/2022061123/5474c91db4af9f89048b456d/html5/thumbnails/49.jpg)
Dynamic Power Dissipation – contd.
Propagation delay
S. B. Sivasubramaniyan MSEC, Chennai
2 20.8
0.82 2 8
DDpHL
DD DD DDn DD
n
CVt
V V VWk V
L
1.7pHL
n DDn
Ct
Wk V
L
![Page 50: VLSI_Design_-_Unit II - Part I](https://reader033.fdocuments.net/reader033/viewer/2022061123/5474c91db4af9f89048b456d/html5/thumbnails/50.jpg)
Problem
Consider a CMOS inverter fabricated in a 0.25 mm process defined as follows,
Find,
S. B. Sivasubramaniyan MSEC, Chennai
2 2115 / , 30 / , 0.4 ,
0.375 1.1252.5 , , , 6.25
0.25 0.25
n ox p ox tn tp
DD Ln p
C A V C A V V V V
W m W mV V C fF
L m L m
, &pHL pHL pt t t
![Page 51: VLSI_Design_-_Unit II - Part I](https://reader033.fdocuments.net/reader033/viewer/2022061123/5474c91db4af9f89048b456d/html5/thumbnails/51.jpg)
Solution
The Propagation delay, (high to low)
Where,
S. B. Sivasubramaniyan MSEC, Chennai
/ 2DDpHL
DN av
C Vt
i
0
1
2 pHLDN av DN DN ti i i
![Page 52: VLSI_Design_-_Unit II - Part I](https://reader033.fdocuments.net/reader033/viewer/2022061123/5474c91db4af9f89048b456d/html5/thumbnails/52.jpg)
Solution
S. B. Sivasubramaniyan MSEC, Chennai
20
1
2 n DD tDNn
Wi k V V
L
20
1 0.375115 2.5 0.42 0.25DN
n
i
0 380DNi A
2
0.375 2.5 1 0.5115 2.5 0.4
0.25 2 2 2pHLDN ti
2
1
2 2 2pHL
DD DDn DD tDN t
n
V VWi k V V
L
318pHLDN t
i A
![Page 53: VLSI_Design_-_Unit II - Part I](https://reader033.fdocuments.net/reader033/viewer/2022061123/5474c91db4af9f89048b456d/html5/thumbnails/53.jpg)
Solution
Propagation delay,
S. B. Sivasubramaniyan MSEC, Chennai
349DN avi A
1318 380
2DN avi
/ 2DDpHL
DN av
C Vt
i
15
6
6.25 10 1.25
349 10pHLt
23.3pHLt ps
![Page 54: VLSI_Design_-_Unit II - Part I](https://reader033.fdocuments.net/reader033/viewer/2022061123/5474c91db4af9f89048b456d/html5/thumbnails/54.jpg)
Solution
From the given data,
We see that, the transistors are not matched, The low to high transition will increase by a factor
(3.83/3)
S. B. Sivasubramaniyan MSEC, Chennai
3.83
3pLH pHLt t
3p
n
W
W
& 3.83n
p
1.3 23.3pLHt 30pLHt ps
![Page 55: VLSI_Design_-_Unit II - Part I](https://reader033.fdocuments.net/reader033/viewer/2022061123/5474c91db4af9f89048b456d/html5/thumbnails/55.jpg)
Solution
Therefore, the actual propagation delay is given by,
S. B. Sivasubramaniyan MSEC, Chennai
1
2p pLH pHLt t t 123.3 30
2pt
26.5pt ps
![Page 56: VLSI_Design_-_Unit II - Part I](https://reader033.fdocuments.net/reader033/viewer/2022061123/5474c91db4af9f89048b456d/html5/thumbnails/56.jpg)
Assignment
Suppose that an additional load capacitance of 0.1pF is added for the inverter mentioned in the previous problem. Also, in an attempt to decrease the area of the inverter in the previous problem, (W/L)p is made equal to (W/L)n. What is the percentage reduction in area achieved? Find the new values of tpHL, tpLH, and tp.
S. B. Sivasubramaniyan MSEC, Chennai
![Page 57: VLSI_Design_-_Unit II - Part I](https://reader033.fdocuments.net/reader033/viewer/2022061123/5474c91db4af9f89048b456d/html5/thumbnails/57.jpg)
Current Flow and Power Dissipation
Consider the two characteristics which were already introduced
S. B. Sivasubramaniyan MSEC, Chennai
![Page 58: VLSI_Design_-_Unit II - Part I](https://reader033.fdocuments.net/reader033/viewer/2022061123/5474c91db4af9f89048b456d/html5/thumbnails/58.jpg)
Current Flow and Power Dissipation
The total energy dissipation in the CMOS inverter in the two cases is given by
If the inverter is switched at the rated of f cycles per second, the dynamic power dissipation is given by
S. B. Sivasubramaniyan MSEC, Chennai
2DDCV
2D DDP fCV
![Page 59: VLSI_Design_-_Unit II - Part I](https://reader033.fdocuments.net/reader033/viewer/2022061123/5474c91db4af9f89048b456d/html5/thumbnails/59.jpg)
Current Flow and Power Dissipation
We know, frequency of operation is inversely proportional to the propagation delay
The lower the propagation delay (desired) the higher is the power dissipation (not desirable)
A figure of merit referred to as Power Delay product is thus introduced
Power Delay product is given by
S. B. Sivasubramaniyan MSEC, Chennai
D pDP P t
![Page 60: VLSI_Design_-_Unit II - Part I](https://reader033.fdocuments.net/reader033/viewer/2022061123/5474c91db4af9f89048b456d/html5/thumbnails/60.jpg)
Power Delay product
Power Delay product is a constant, the lower the value of Power Delay product, higher is the effectiveness of the technology
The Power Delay product has the unit of joules It is a measure of energy dissipated per cycle of operation For CMOS technology, the power delay product is simply
S. B. Sivasubramaniyan MSEC, Chennai
2DDDP CV
![Page 61: VLSI_Design_-_Unit II - Part I](https://reader033.fdocuments.net/reader033/viewer/2022061123/5474c91db4af9f89048b456d/html5/thumbnails/61.jpg)
Problem
Consider a CMOS inverter with , (W/L)n = 20, (W/L)p = 40, , and VDD = 10 V. Find peak current drawn from the supply.
S. B. Sivasubramaniyan MSEC, Chennai
2tn tpV V V 22 20 /n ox p oxC C A V
![Page 62: VLSI_Design_-_Unit II - Part I](https://reader033.fdocuments.net/reader033/viewer/2022061123/5474c91db4af9f89048b456d/html5/thumbnails/62.jpg)
Solution
For peak current drawn from the supply, Vth = VDD/2 QP and QN both work in the saturation region The current equation if given by
Substituting, we get
S. B. Sivasubramaniyan MSEC, Chennai
21
2DP p DD I tpp
Wi k V V V
L
2
22
1 1010 40 10 2
2 2DP
Ai V
V
![Page 63: VLSI_Design_-_Unit II - Part I](https://reader033.fdocuments.net/reader033/viewer/2022061123/5474c91db4af9f89048b456d/html5/thumbnails/63.jpg)
Solution
Simplifying, we get
S. B. Sivasubramaniyan MSEC, Chennai
1800 1.8DPi A mA
![Page 64: VLSI_Design_-_Unit II - Part I](https://reader033.fdocuments.net/reader033/viewer/2022061123/5474c91db4af9f89048b456d/html5/thumbnails/64.jpg)
Problem
Consider a CMOS VLSI chip having 100,000 gates fabricated in a 1.2 m CMOS technology. Let load capacitance per gate be 30 fF. If the chip is operated from a 5V supply and is switched at a rate of 100 MHz, find
The power dissipation per gate The total power dissipated in the chip assuming that only
30 % of the gates are switched at any one time
S. B. Sivasubramaniyan MSEC, Chennai
![Page 65: VLSI_Design_-_Unit II - Part I](https://reader033.fdocuments.net/reader033/viewer/2022061123/5474c91db4af9f89048b456d/html5/thumbnails/65.jpg)
Solution
Power dissipation per gate is the dynamic power dissipation given by
Substituting,
S. B. Sivasubramaniyan MSEC, Chennai
2DDP fCV
26 15100 10 30 10 5P
75P W
![Page 66: VLSI_Design_-_Unit II - Part I](https://reader033.fdocuments.net/reader033/viewer/2022061123/5474c91db4af9f89048b456d/html5/thumbnails/66.jpg)
Solution
Total Power dissipation when 30 % of the gates are switched at any one time
S. B. Sivasubramaniyan MSEC, Chennai
3075 100,000
100P W
2.25P W
![Page 67: VLSI_Design_-_Unit II - Part I](https://reader033.fdocuments.net/reader033/viewer/2022061123/5474c91db4af9f89048b456d/html5/thumbnails/67.jpg)
Problem
Consider a CMOS inverter with , (W/L)n = 20, (W/L)p = 40, , and VDD = 10 V. If the inverter is loaded by 15 pF capacitor, find the dynamic power dissipation when it is switched at a frequency of 2 MHz. What is the average current drawn from the supply?
S. B. Sivasubramaniyan MSEC, Chennai
2tn tpV V V 22 20 /n ox p oxC C A V
![Page 68: VLSI_Design_-_Unit II - Part I](https://reader033.fdocuments.net/reader033/viewer/2022061123/5474c91db4af9f89048b456d/html5/thumbnails/68.jpg)
Solution 3 mW, 0.3 mA
S. B. Sivasubramaniyan MSEC, Chennai
Assignment
![Page 69: VLSI_Design_-_Unit II - Part I](https://reader033.fdocuments.net/reader033/viewer/2022061123/5474c91db4af9f89048b456d/html5/thumbnails/69.jpg)
Combinational circuits do not have memory elements
Combinational circuits forms part of every digital systems
S. B. Sivasubramaniyan MSEC, Chennai
Combinational logic design – with CMOS
![Page 70: VLSI_Design_-_Unit II - Part I](https://reader033.fdocuments.net/reader033/viewer/2022061123/5474c91db4af9f89048b456d/html5/thumbnails/70.jpg)
CMOS logic circuit is just an extension of CMOS inverter
As we know, in a CMOS inverter, a pull-down transistor is formed by a NMOS device and a pull-up transistor is formed by a PMOS device
Similarly, a CMOS logic circuit will have a pull-down network formed by NMOS transistors, and a pull-up network formed by PMOS transistors
S. B. Sivasubramaniyan MSEC, Chennai
Combinational logic design – with CMOS
![Page 71: VLSI_Design_-_Unit II - Part I](https://reader033.fdocuments.net/reader033/viewer/2022061123/5474c91db4af9f89048b456d/html5/thumbnails/71.jpg)
Pull-down network (PDN) will contain all input combinations that make the output low
Similarly, Pull-up network (PUN) will contain all input combinations that make the output high
We know, Pull-down network is formed by NMOS transistors and NMOS transistors are activated when the gate is high, a PDN network is activated when the gate(input) is high
Similarly, a Pull-up network is activated when the gate(input ) is low
S. B. Sivasubramaniyan MSEC, Chennai
Pull-down and Pull-up network
![Page 72: VLSI_Design_-_Unit II - Part I](https://reader033.fdocuments.net/reader033/viewer/2022061123/5474c91db4af9f89048b456d/html5/thumbnails/72.jpg)
The inputs to PDN and PUN networks work in a complementary fashion similar to CMOS inverter in which inputs to NMOS and PMOS devices work in a complementary fashion
S. B. Sivasubramaniyan MSEC, Chennai
Pull-down and Pull-up network
![Page 73: VLSI_Design_-_Unit II - Part I](https://reader033.fdocuments.net/reader033/viewer/2022061123/5474c91db4af9f89048b456d/html5/thumbnails/73.jpg)
The pull-down (and Pull-up) network employs devices in parallel to realize OR function
The pull-down (and Pull-up) network employs devices in series to realize AND function
S. B. Sivasubramaniyan MSEC, Chennai
Pull-down - Basics
![Page 74: VLSI_Design_-_Unit II - Part I](https://reader033.fdocuments.net/reader033/viewer/2022061123/5474c91db4af9f89048b456d/html5/thumbnails/74.jpg)
Y will be low when A is high or B is high
S. B. Sivasubramaniyan MSEC, Chennai
Pull-down - examples
![Page 75: VLSI_Design_-_Unit II - Part I](https://reader033.fdocuments.net/reader033/viewer/2022061123/5474c91db4af9f89048b456d/html5/thumbnails/75.jpg)
Y will be low when A is high and B is high
S. B. Sivasubramaniyan MSEC, Chennai
Pull-down - examples
![Page 76: VLSI_Design_-_Unit II - Part I](https://reader033.fdocuments.net/reader033/viewer/2022061123/5474c91db4af9f89048b456d/html5/thumbnails/76.jpg)
Y will be low when A is high or when B and C are high
S. B. Sivasubramaniyan MSEC, Chennai
Pull-down - examples
![Page 77: VLSI_Design_-_Unit II - Part I](https://reader033.fdocuments.net/reader033/viewer/2022061123/5474c91db4af9f89048b456d/html5/thumbnails/77.jpg)
The pull-up (and Pull-down) network employs devices in parallel to realize OR function
The pull-up (and Pull-down) network employs devices in series to realize AND function
S. B. Sivasubramaniyan MSEC, Chennai
Pull-up - Basics
![Page 78: VLSI_Design_-_Unit II - Part I](https://reader033.fdocuments.net/reader033/viewer/2022061123/5474c91db4af9f89048b456d/html5/thumbnails/78.jpg)
The pull-up (and Pull-down) network employs devices in parallel to realize OR function
The pull-up (and Pull-down) network employs devices in series to realize AND function
S. B. Sivasubramaniyan MSEC, Chennai
Pull-up - examples
![Page 79: VLSI_Design_-_Unit II - Part I](https://reader033.fdocuments.net/reader033/viewer/2022061123/5474c91db4af9f89048b456d/html5/thumbnails/79.jpg)
Y will be high when A is low or B is low
S. B. Sivasubramaniyan MSEC, Chennai
Pull-down - examples
![Page 80: VLSI_Design_-_Unit II - Part I](https://reader033.fdocuments.net/reader033/viewer/2022061123/5474c91db4af9f89048b456d/html5/thumbnails/80.jpg)
Y will be high only when A and B are low
S. B. Sivasubramaniyan MSEC, Chennai
Pull-down - examples
![Page 81: VLSI_Design_-_Unit II - Part I](https://reader033.fdocuments.net/reader033/viewer/2022061123/5474c91db4af9f89048b456d/html5/thumbnails/81.jpg)
Y will be high only when A is low or if B and C are both low
S. B. Sivasubramaniyan MSEC, Chennai
Pull-down - examples
![Page 82: VLSI_Design_-_Unit II - Part I](https://reader033.fdocuments.net/reader033/viewer/2022061123/5474c91db4af9f89048b456d/html5/thumbnails/82.jpg)
Two input NOR gate Two input NAND gate Y = [A(B + CD)]’ Two input Ex-OR gate Three input Ex-OR gate
S. B. Sivasubramaniyan MSEC, Chennai
Assignment