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Department of Electronics and Communication Engineering, VBITDepartment of Electronics and Communication Engineering, VBIT
UNIT - I
INTRODUCTION
P.VIDYA SAGAR ( ASSOCIATE PROFESSOR)
VLSI
Department of Electronics and Communication Engineering, VBITDepartment of Electronics and Communication Engineering, VBIT
contents
UNIT I
INTRODUCTION: Introduction to IC Technology – MOS, PMOS, NMOS, CMOS & BiCMOS
technologies.
BASIC ELECTRICAL PROPERTIES : Basic Electrical Properties of MOS and BiCMOS Circuits:
Ids-Vds relationships, MOS transistor threshold Voltage, gm, gds, figure of merit ωo ; Pass transistor,
NMOS Inverter, Various pull ups, CMOS Inverter analysis and design, Bi-CMOS Inverters.
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A Brief History Invention of the Transistor
Vacuum tubes ruled in first half of 20th century Large, expensive, power-hungry, unreliable
1947: first point contact transistor (3 terminal devices)
Shockley, Bardeen and Brattain at Bell Labs
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A Brief History, contd..
1958: First integrated circuit Flip-flop using two transistors
Built by Jack Kilby (Nobel Laureate) at Texas Instruments
Robert Noyce (Fairchild) is also considered as a co-inventor
smithsonianchips.si.edu/ augarten/
Kilby’s IC
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1970’s processes usually had only nMOS transistors Inexpensive, but consume power while idle
1980s-present: CMOS processes for low idle power
MOS Integrated Circuits
Intel 1101 256-bit SRAM Intel 4004 4-bit Proc
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Moore’s Law
1965: Gordon Moore plotted transistor on each chip
Fit straight line on semilog scale
Transistor counts have doubled every 26 months
Year
Tra
nsisto
rs
40048008
8080
8086
80286Intel386
Intel486Pentium
Pentium ProPentium II
Pentium III
Pentium 4
1,000
10,000
100,000
1,000,000
10,000,000
100,000,000
1,000,000,000
1970 1975 1980 1985 1990 1995 2000
Integration Levels
SSI: 10 gates
MSI: 1000 gates
LSI: 10,000 gates
VLSI: > 10k gates
http://www.intel.com/technology/silicon/mooreslaw/
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The First Computer
The BabbageDifference Engine(1832)
25,000 parts
cost: £17,470
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ENIAC - The first electronic computer (1946)
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WHY VLSI?
Integration Improves the Design
• Lower parasitics, higher clocking speed
• Lower power
• Physically small
Integration Reduces Manufacturing Costs
• (almost) no manual assembly
• About $1-5billion/fab
• Typical Fab 1 city block, a few hundred people
• Packaging is largest cost
• Testing is second largest cost
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n+n+S
GD
+
DEVICE
CIRCUIT
GATE
MODULE
SYSTEM
Design Levels
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Moore’s Law 1965: Gordon Moore plotted transistor on each chip
Fit straight line on semilog scale
Transistor counts have doubled every 26 months
He predicted that the number of transistors on a chip would double about every
18 months
Year
Tra
nsisto
rs
40048008
8080
8086
80286Intel386
Intel486Pentium
Pentium ProPentium II
Pentium III
Pentium 4
1,000
10,000
100,000
1,000,000
10,000,000
100,000,000
1,000,000,000
1970 1975 1980 1985 1990 1995 2000
http://www.intel.com/technology/silicon/mooreslaw/
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INTEGRADED CIRCUIT (IC):
Multi terminal electronic device in which discrete components like
transistors,resisters,capacitors are fabricated in a single construction process.
Classification of ICs :
•Based on application -Analog , digital
•Based on complexity -SSI, MSI, LSI, VLSI
•Based on fabrication-Monolithic , hybrid
•Based on technology -RTL ,DTL, TTL, MOS.
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IC Evolution :
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Name Year Transistors number Logic gates number
small-scale integration (SSI) 1964 1 to 10 1 to 12
medium-scale integration (MSI) 1968 10 to 500 13 to 99
large-scale integration (LSI) 1971 500 to 20,000 100 to 9,999
very large scale integration (VLSI) 1980 20,000 to 1,000,000 10,000 to 99,999
Ultra large scale integration (ULSI) 1984 1,000,000 and more 100,000 and more
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Pentium 4 Processor
http://www.intel.com/intel/intelis/museum/online/hist_micro/hof/index.htm
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Ref: http://micro.magnet.fsu.edu/creatures/technical/sizematters.html
• Modern transistors are few microns wide and approximately 0.1 micron or less in length
• Human hair is 80-90 microns in diameter
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MOS (Metal-oxide-silicon)
although invented before bipolar transistor, was initially difficult to manufacture
nMOS (n-channel MOS) technology developed in 1970s required fewer masking steps,
was denser, and consumed less power than equivalent bipolar Ics.
CMOS (Complementary MOS): n-channel and p-channel MOS transistors =>
lower power consumption, simplified fabrication process
Bi-CMOS - hybrid Bipolar, CMOS (for high speed)
GaAs - Gallium Arsenide (for high speed)
Si-Ge - Silicon Germanium (for RF)
Metal-oxide-semiconductor (MOS) and related VLSI technology
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Mos transistors
– Basic MOS transistors with the doping concentration of transistor two types of MOS transistors
are available as NMOS transistor and PMOS transistor. With their mode of operation further they
are classified as depletion mode transistor and enhancement mode transistor.
nMOS enhancement mode transistor
– nMOS devices are formed in a p-type substrate of moderate doping level. The source and drain
regions are formed by diffusing n-type impurities through suitable masks into these areas.
Thus source and drain are isolated from one another by two diodes and their Connections are
made by a deposited metal layer. The basic block diagrams of nMOS enhancement mode
transistor is shown in figure.
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nMOS depletion mode transistornMOS enhancement mode transistor
– The basic block diagram of nMOS depletion mode transistor is shown in figure. In depletion mode
transistor the channel is established even the voltage Vgs = 0 by implanting suitable impurities in
the region between source and drain during manufacture and prior to depositing the insulation
and the gate.
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MOS Transistors
– Four terminal device: gate, source,
drain, body
– Gate – oxide – body stack looks like a
capacitor
– Gate and body are conductors (body
is also called the substrate)
– SiO2 (oxide) is a “good” insulator
(separates the gate from the body
– Called metal–oxide–semiconductor
(MOS) capacitor, even though gate is
mostly made of poly-crystalline
silicon (polysilicon)
SiO2
n
GateSource Drain
bulk Si
Polysilicon
p+ p+
n+
p
GateSource Drain
bulk Si
SiO2
Polysilicon
n+
NMOS
PMOS
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MOS Capacitor
Gate and body form MOS capacitor
Operating modes
Accumulation
Depletion
Inversion
polysilicon gate
(a)
silicon dioxide insulator
p-type body+-
Vg < 0
(b)
+-
0 < Vg < V
t
depletion region
(c)
+-
Vg > V
t
depletion region
inversion region
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Terminal Voltages
– Mode of operation depends on Vg, Vd, Vs
– Vgs = Vg – Vs
– Vgd = Vg – Vd
– Vds = Vd – Vs = Vgs - Vgd
– Source and drain are symmetric diffusion terminals
– By convention, source is terminal at lower voltage
– Hence Vds 0
– nMOS body is grounded. First assume source is 0 too.
– Three regions of operation
– Cutoff
– Linear
– Saturation
Vg
Vs
Vd
Vgd
Vgs
Vds
+-
+
-
+
-
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nMOS Cutoff
– No channel
– Ids = 0
+-
Vgs
= 0
n+ n+
+-
Vgd
p-type body
b
g
s d
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nMOS Linear
– Channel forms
– Current flows from d to s
– e- from s to d
– Ids increases with Vds
– Similar to linear resistor
+-
Vgs
> Vt
n+ n+
+-
Vgd
= Vgs
+-
Vgs
> Vt
n+ n+
+-
Vgs
> Vgd
> Vt
Vds
= 0
0 < Vds
< Vgs
-Vt
p-type body
p-type body
b
g
s d
b
g
s dIds
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nMOS Saturation
– Channel pinches off
– Ids independent of Vds
– We say current saturates
– Similar to current source
+-
Vgs
> Vt
n+ n+
+-
Vgd
< Vt
Vds
> Vgs
-Vt
p-type body
b
g
s d Ids
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I-V Characteristics
25VIDYA SAGAR P
NMOS:Vgs < Vt OFFVds < Vgs -Vt LINEARVds > Vgs – Vt SATURATION
PMOSVsg < |Vt| OFFVsd < Vsg – |Vt| LINEARVsd > Vsg – |Vt| SATURATION
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CMOS
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Structure: n-channel MOSFET(NMOS)
pn+n+
metal
LW
source
S
gate: metal or heavily doped poly-Si
Gdrain
D
body
B
oxide
IG=0
ID=ISIS
x
y
(bulk or
substrate)
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Channel Charge
– MOS structure looks like parallel plate capacitor while operating in inversion
– Gate – oxide – channel
– Qchannel =
n+ n+
p-type body
+
Vgd
gate
+ +
source
-
Vgs
-drain
Vds
channel-
Vg
Vs
Vd
Cg
n+ n+
p-type body
W
L
tox
SiO2 gate oxide
(good insulator, ox
= 3.9)
polysilicon
gate
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Channel Charge
– MOS structure looks like parallel plate capacitor while operating in inversion
– Gate – oxide – channel
– Qchannel = CV
– C =
n+ n+
p-type body
+
Vgd
gate
+ +
source
-
Vgs
-drain
Vds
channel-
Vg
Vs
Vd
Cg
n+ n+
p-type body
W
L
tox
SiO2 gate oxide
(good insulator, ox
= 3.9)
polysilicon
gate
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Channel Charge
– MOS structure looks like parallel plate capacitor while operating in inversion
– Gate – oxide – channel
– Qchannel = CV
– C = Cg = oxWL/tox = CoxWL
– V =
n+ n+
p-type body
+
Vgd
gate
+ +
source
-
Vgs
-drain
Vds
channel-
Vg
Vs
Vd
Cg
n+ n+
p-type body
W
L
tox
SiO2 gate oxide
(good insulator, ox
= 3.9)
polysilicon
gate
Cox = ox / tox
30VIDYA SAGAR P
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Channel Charge
– MOS structure looks like parallel plate capacitor while operating in inversion
– Gate – oxide – channel
– Qchannel = CV
– C = Cg = oxWL/tox = CoxWL
– V = Vgc – Vt = (Vgs – Vds/2) – Vt
n+ n+
p-type body
+
Vgd
gate
+ +
source
-
Vgs
-drain
Vds
channel-
Vg
Vs
Vd
Cg
n+ n+
p-type body
W
L
tox
SiO2 gate oxide
(good insulator, ox
= 3.9)
polysilicon
gate
Cox = ox / tox
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Carrier velocity
– Charge is carried by e-
– Carrier velocity v proportional to lateral E-field between source and drain
– v =
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Carrier velocity
– Charge is carried by e-
– Carrier velocity v proportional to lateral E-field between source and drain
– v = E called mobility
– E =
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Carrier velocity
– Charge is carried by e-
– Carrier velocity v proportional to lateral E-field between source and drain
– v = E called mobility
– E = Vds/L
– Time for carrier to cross channel:
– t =
34VIDYA SAGAR P
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Carrier velocity
– Charge is carried by e-
– Carrier velocity v proportional to lateral E-field between source and drain
– v = E called mobility
– E = Vds/L
– Time for carrier to cross channel:
– t = L / v
35VIDYA SAGAR P
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nMOS Linear I-V
– Now we know
– How much charge Qchannel is in the channel
– How much time t each carrier takes to cross
dsI
36VIDYA SAGAR P
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nMOS Linear I-V
– Now we know
– How much charge Qchannel is in the channel
– How much time t each carrier takes to cross
channelds
QI
t
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nMOS Linear I-V
– Now we know
– How much charge Qchannel is in the channel
– How much time t each carrier takes to cross
channel
ox 2
2
ds
dsgs t ds
dsgs t ds
QI
t
W VC V V V
L
VV V V
ox = W
CL
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nMOS Saturation I-V
– If Vgd < Vt, channel pinches off near drain
– When Vds > Vdsat = Vgs – Vt
– Now drain voltage no longer increases current
dsI
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nMOS Saturation I-V
– If Vgd < Vt, channel pinches off near drain
– When Vds > Vdsat = Vgs – Vt
– Now drain voltage no longer increases current
2dsat
ds gs t dsat
VI V V V
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nMOS Saturation I-V
– If Vgd < Vt, channel pinches off near drain
– When Vds > Vdsat = Vgs – Vt
– Now drain voltage no longer increases current
2
2
2
dsatds gs t dsat
gs t
VI V V V
V V
41VIDYA SAGAR P
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nMOS I-V Summary
2
cutoff
linear
saturatio
0
2
2n
gs t
dsds gs t ds ds dsat
gs t ds dsat
V V
VI V V V V V
V V V V
– Shockley 1st order transistor models
42VIDYA SAGAR P
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Transistors as Switches
– We can view MOS transistors as electrically controlled switches
– Voltage at gate controls path from source to drain
g
s
d
g = 0
s
d
g = 1
s
d
g
s
d
s
d
s
d
nMOS
pMOS
OFFON
ONOFF
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CMOS Inverter
A Y
0 1
1 0
VDD
A=0 Y=1
GND
OFF
ON
A Y
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CMOS NAND Gate
A B Y
0 0
0 1
1 0
1 1
A
B
Y
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CMOS NAND Gate
A B Y
0 0 1
0 1
1 0
1 1
A=0
B=0
Y=1
OFF
ON ON
OFF
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CMOS NAND Gate
A B Y
0 0 1
0 1 1
1 0
1 1
A=0
B=1
Y=1
OFF
OFF ON
ON
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CMOS NAND Gate
A B Y
0 0 1
0 1 1
1 0 1
1 1
A=1
B=0
Y=1
ON
ON OFF
OFF
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CMOS NAND Gate
A B Y
0 0 1
0 1 1
1 0 1
1 1 0
A=1
B=1
Y=0
ON
OFF OFF
ON
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CMOS NOR Gate
A B Y
0 0 1
0 1 0
1 0 0
1 1 0
A
BY
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nMOS FABRICATION
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Pure silicon is melted in a pot (1400º C) and a small seed containing the desired crystal
orientation is inserted in to molten silicon and slowly(1mm/minute) pulled out. The wafers
are generally available in diameters of 150 mm, 200 mm, or 300 mm, and are mirror-polished
and rinsed before shipment from the wafer manufacturer.
Wafer
Fabrication
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Oxidation
It refers to the chemical process of silicon reacting with oxygen to form silicon dioxide, SiO2.
Si+O2=SiO2
The process can be classified as two types:
Dry oxide: introduce high-purity gas. It gives better electrical characteristics.
Wet oxide. Introduce water vapor.
SiO2 is used to form insulator, capacitor, an effective mask
against many impurities in SiO2 region, but allowing the
introduction of dopants into Si region.
Thin oxide is usually grown using dry oxidation
Thick oxide is usually grown using wet oxidation
Dry oxidation results in slower growth rate, but high density — higher breakdown voltage.
Fig. Schematic of the Oxidation Process
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Oxidation
– Grow SiO2 on top of Si wafer
– 900 – 1200 C with H2O or O2 in oxidation furnace
p substrate
SiO2
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Diffusion
It introduces impurity atoms (dopants) into silicon to change its resistivity.
Dopant types:-p-type dopants: boron
-n-type dopants: phosphorus and arsenic
A pn junction (PN)- formed by diffusing p-type dopants into an n-type substrate.
Diffusion of impurities is usually carried out at high temperatures (1000 to 1200°C) to
obtain the desired doping profile. When the wafer is cooled to room temperature, the
impurities are essentially “frozen” in position.
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Ion implantation
An alternative process to replace diffusion--used to introduce
impurities into silicon.
An ion implanter-produces ions of the desired impurity,
accelerates them by an electric field,allows them to strike the
silicon surface.
It is used for accurate control of the dopants.
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Ion Implantation
Focus Neutral beam and
beam path gated
Beam trap and
gate plate
Wafer in wafer
process chamber
X - axis
scanner
Y - axis
scanner
Neutral beam trap
and beam gate
p- epi
p+ substrate
field oxide
photoresist mask
n-w ell
p-channel transistor
phosphorus
(-) ions
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Photolithography
1.Photoresist application: the surface to be patterned is
spin-coated with a light-sensitive organic polymer called photoresist
2.Printing (exposure):the mask pattern is developed on the
photoresist, with UV light exposure depending on the type of
photoresist(negative or positive), the exposed or unexposed parts
become resistant to certain types of solvents
3.Development: the soluble photoresist is chemically removed The
developed photoresist acts as a mask for patterning of underlying
layers and then is removed.
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oxidationoptical
mask
process
step
photoresist coatingphotoresist
removal
(ashing)
spin, rinse,
dryacid etch
photoresist
development
stepper
exposure
Photolithographic Process
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Photolithography
Exposure Processes
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Etching
Once the desired shape is patterned with photoresist,
the etching process allows unprotected materials to be
removed
Wet etching: uses chemicals
Dry or plasma etching: uses ionized gases
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Etch
Etch
Chambers
Cluster Tool
Configuration
Transfer
Chamber
Loadlock
Wafers
RIE Chamber
Transfer
Chamber
Gas Inlet
Exhaust
RF Power
Wafer
Die-electric Etch
Plasma Etch
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Chemical Vapor Deposition (CVD)
To develop nitride films and polysilicon films, the chemical vapordeposition (CVD) method is used, in which a gaseous reactant is introducedto the silicon substrate, and chemical reaction produce the deposited layermaterial.
The metallic layers used in the wiring of the circuit are also formed by CVD, spattering (PVD: physical vapor deposition)
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Metallization
Interconnecting the devices, such as transistors, formed on the silicon wafer completes the
circuit. the wafer is first covered with a thick and flat interlayer insulation film (oxide film).
Next, contact holes are drilled by lithograph and etching, through the interlayer insulation
film, above the devices to be connected. Many metal films used in IC fabrication are
deposited by sputtering. In the sputtering process, argon gas is excited by a high energy field
to split up into positively charged argon ions and free electrons. An electric field attracts the
argon ions toward a target made out of the material to be deposited. .
Sputter process.
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Encapsulation
During Encapsulation, lead frames are placed onto mold plates and heated. Molten plastic
material is pressed around each die to form its individual package. The mold is opened,
and the lead frames are pressed out and cleaned.
Wafer Test
Upon completion of wafer fabrication, not all of the die on awafer will be fully
functional. The yield loss at this step ranges from a few percent for mature
processes, to 90% or more for new processes. In order to avoid adding additional
value to defective units during packaging, a 100% test of the die is performed.
PackagingSilicon ICs in “die” form are difficult to handle, fragile even though they have a
protective layer, and the tiny bond pads are difficult to connect to. In order to further
protect the die and make the parts easier to handle and connect, packaging is
performed.
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Testing
Defective IC
Individual integrated circuits are
tested to distinguish good die
from bad ones.
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Die Cut and Assembly
Good chips are attached
to a lead frame package.
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Die Attach and Wire Bonding
lead frame gold wire
bonding pad
connecting pin
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Final Test
Chips are electrically
tested under varying
environmental conditions.
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N-MOS Fabrication Process
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Step -Metallization
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• CMOS Technology depends on using both N-Type and P-Type devices on the same chip.The
two main technologies to do this task are:
– P-Well :The substrate is N-Type. The N-Channel device is built into a P-Type well within
the parent N-Type substrate. The P-channel device is built directly on the substrate.
– N-Well:The substrate is P-Type. The N-channel device is built directly on the substrate,
while the P-channel device is built into a N-type well within the parent P-Type substrate.
• Two more advanced technologies to do this task are:
Twin Tub:Both an N-Well and a P-Well are manufactured on a lightly doped N-type
substrate.
Silicon-on-Insulator (SOI) CMOS Process:SOI allows the creation of independent,
completely isolated nMOS and pMOS transistors virtually side-by-side on an insulating
substrate.
Complementary MOS fabrication
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What is CMOS?
– CMOS
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– Six masks
– n-well
– Polysilicon
– N+ diffusion
– P+ diffusion
– Contact
– Metal
Detailed Mask Views
Metal
Polysilicon
Contact
n+ Diffusion
p+ Diffusion
n well
Masks: Each Processing steps in the fabrication procedure requires to define certain area on
the chip. This is known as Masks.
Chips are specified with set of masks
VIDYA SAGAR P82
Department of Electronics and Communication Engineering, VBITDepartment of Electronics and Communication Engineering, VBIT VIDYA SAGAR P83
Department of Electronics and Communication Engineering, VBITDepartment of Electronics and Communication Engineering, VBIT VIDYA SAGAR P84
Department of Electronics and Communication Engineering, VBITDepartment of Electronics and Communication Engineering, VBIT VIDYA SAGAR P85
Department of Electronics and Communication Engineering, VBITDepartment of Electronics and Communication Engineering, VBIT VIDYA SAGAR P86
Department of Electronics and Communication Engineering, VBITDepartment of Electronics and Communication Engineering, VBIT VIDYA SAGAR P87
Department of Electronics and Communication Engineering, VBITDepartment of Electronics and Communication Engineering, VBIT
Fabrication Steps
– Start with blank wafer
– Build inverter from the bottom up
– First step will be to form the n-well
– Cover wafer with protective layer of SiO2 (oxide)
– Remove layer where n-well should be built
– Implant or diffuse n dopants into exposed wafer
– Strip off SiO2
p substrate
VIDYA SAGAR P88
Department of Electronics and Communication Engineering, VBITDepartment of Electronics and Communication Engineering, VBIT
Oxidation
– Grow SiO2 on top of Si wafer
– 900 – 1200 C with H2O or O2 in oxidation furnace
p substrate
SiO2
VIDYA SAGAR P89
Department of Electronics and Communication Engineering, VBITDepartment of Electronics and Communication Engineering, VBIT
Photoresist
– Spin on photoresist
– Photoresist is a light-sensitive organic polymer
– Softens where exposed to light
p substrate
SiO2
Photoresist
VIDYA SAGAR P90
Department of Electronics and Communication Engineering, VBITDepartment of Electronics and Communication Engineering, VBIT
Lithography
– Expose photoresist through n-well mask
– Strip off exposed photoresist
p substrate
SiO2
Photoresist
VIDYA SAGAR P91
Department of Electronics and Communication Engineering, VBITDepartment of Electronics and Communication Engineering, VBIT
Etch
– Etch oxide with hydrofluoric acid (HF)
– Seeps through skin and eats bone; nasty stuff!!!
– Only attacks oxide where resist has been exposed
p substrate
SiO2
Photoresist
VIDYA SAGAR P92
Department of Electronics and Communication Engineering, VBITDepartment of Electronics and Communication Engineering, VBIT
Strip Photoresist
– Strip off remaining photoresist
– Use mixture of acids called piranah etch
– Necessary so resist doesn’t melt in next step
p substrate
SiO2
VIDYA SAGAR P93
Department of Electronics and Communication Engineering, VBITDepartment of Electronics and Communication Engineering, VBIT
n-well
– n-well is formed with diffusion or ion implantation
– Diffusion
– Place wafer in furnace with arsenic gas
– Heat until As atoms diffuse into exposed Si
– Ion Implanatation
– Blast wafer with beam of As ions
– Ions blocked by SiO2, only enter exposed Si
n well
SiO2
VIDYA SAGAR P94
Department of Electronics and Communication Engineering, VBITDepartment of Electronics and Communication Engineering, VBIT
Strip Oxide
– Strip off the remaining oxide using HF
– Back to bare wafer with n-well
– Subsequent steps involve similar series of steps
p substrate
n well
VIDYA SAGAR P95
Department of Electronics and Communication Engineering, VBITDepartment of Electronics and Communication Engineering, VBIT
Polysilicon
– Deposit very thin layer of gate oxide
– < 20 Å (6-7 atomic layers)
– Chemical Vapor Deposition (CVD) of silicon layer
– Place wafer in furnace with Silane gas (SiH4)
– Forms many small crystals called polysilicon
– Heavily doped to be good conductor
Thin gate oxide
Polysilicon
p substraten well
VIDYA SAGAR P96
Department of Electronics and Communication Engineering, VBIT
Polysilicon Patterning
– Use same lithography process to pattern polysilicon
Polysilicon
p substrate
Thin gate oxide
Polysilicon
n well
Department of Electronics and Communication Engineering, VBIT
Self-Aligned Process
– Use oxide and masking to expose where n+ dopants should be
diffused or implanted
– N-diffusion forms NMOS source, drain, and n-well contact
p substraten well
Department of Electronics and Communication Engineering, VBIT
P-Diffusion
– Similar set of steps form p+ diffusion regions for pMOS source and
drain and substrate contact
p+ Diffusion
p substraten well
n+n+ n+p+p+p+
Department of Electronics and Communication Engineering, VBIT
Contacts
– Now we need to wire together the devices
– Cover chip with thick field oxide
– Etch oxide where contact cuts are needed
p substrate
Thick field oxide
n well
n+n+ n+p+p+p+
Contact
Department of Electronics and Communication Engineering, VBIT
Metallization
– Sputter on aluminum over whole wafer
– Pattern to remove excess metal, leaving wires
p substrate
Metal
Thick field oxide
n well
n+n+ n+p+p+p+
Metal
Department of Electronics and Communication Engineering, VBITDepartment of Electronics and Communication Engineering, VBIT
Twin-Tub (Twin-Well) CMOS Process
This technology provides the basis for separate optimization of the nMOS and pMOS transistors, thus making it possible
for threshold voltage, body effect and the channel transconductance of both types of transistors to be tuned
independently. Generally, the starting material is a n+ or p+ substrate, with a lightly doped epitaxial layer on top. This
epitaxial layer provides the actual substrate on which the n-well and the p-well are formed. Since two independent
doping steps are performed for the creation of the well regions, the dopant concentrations can be carefully optimized to
produce the desired device characteristics. The Twin-Tub process is shown below.
In the conventional p & n-well CMOS process, the doping density of the well region is typically about one order of
magnitude higher than the substrate, which, among other effects, results in unbalanced drain parasitics. The twin-tub
process avoids this problem.
VIDYA SAGAR P102
Department of Electronics and Communication Engineering, VBIT
Advanced CMOS Technologies
– Substrate for Twin-Well MOS Technogy
For inexpensive and low-performance chips, one may use a heavily doped substrate and omit one
well. The substrate should be doped to about 1016/cm3, with a resistivity of about 1 Ω-cm. This
allows simpler construction, with good “Ground Potential” distribution, but the devices are not
optimal and there is a chance of latch-up if the voltages are pushed hard.
For high-performance chips, one uses a low doped substrate, 1015/cm3, 10 Ω-cm, and then
constructs Two Wells at optimum doping levels (called Tubs in the diagram). Since the substrate is
lightly doped, there is less chance for latch-up because of the high resistivity.
VIDYA SAGAR P103
Department of Electronics and Communication Engineering, VBITDepartment of Electronics and Communication Engineering, VBIT
P-EpiP-Wafer
Boron Ions
P-WellN-Well
Photoresist
P-Epi
P-Wafer
Photoresist
N-Well
Phosphorus Ions
Twin Well
Two mask steps
Flat surface
Common used in advanced CMOS IC chip
High energy, low current implanters
Furnaces annealing and driving-in
VIDYA SAGAR P104
Department of Electronics and Communication Engineering, VBITDepartment of Electronics and Communication Engineering, VBIT
Silicon-on-Insulator (SOI) CMOS Process
Rather than using silicon as the substrate material, technologists have sought to use an insulating substrate to
improve process characteristics such as speed and latch-up susceptibility. The SOI CMOS technology allows
the creation of independent, completely isolated nMOS and pMOS transistors virtually side-by-side on an
insulating substrate. The main advantages of this technology are the higher integration density (because of
the absence of well regions), complete avoidance of the latch-up problem, and lower parasitic capacitances
compared to the conventional p & n-well or twin-tub CMOS processes. A cross-section of nMOS and
pMOS devices using SOI process is shown below.
The SOI CMOS process is considerably more costly than the standard p & n-well CMOS process. Yet the
improvements of device performance and the absence of latch-up problems can justify its use, especially for
deep-sub-micron devices.
VIDYA SAGAR P105
Department of Electronics and Communication Engineering, VBIT
Thank you………………