Vlsi Vii Unit[1]

8/8/2019 Vlsi Vii Unit[1]

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Simplified FPGA design implementation flow


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ASIC Design Flow


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Design methods

1. Behavioral synthesis

2. RTL synthesis3. Logic Synthesis

4. Structural-to-Layout synthesis

5. Layout synthesis


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1. Behavioral synthesis

At the behavioral level, the operation ofthe system is captured without specifyingthe implementation.

Behavioral level is technology-independent.

Behavioral synthesis allows design at higherlevels of abstraction by automating thetranslation and optimization of a behavioraldescription, or high-level model, into an RTL

implementation. This process starts with a high-level

language description of a module's behavior,including I/O actions and computationalfunctionality.


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Behavioral synthesis The other inputs to the synthesis process are a target

technology library, for the selected fabrication process, and aset of directives that will influence the resulting architecture.

Several algorithmic optimizations are performed to reduce thecomplexity and then the description is analyzed to determinethe essential operations and the dataflow dependenciesbetween them.

A behavioral compiler must perform the following operations:

Decide and assign resources based on area and timingrequirements Insert pipeline registers to achieve timing constraints. Create microcode and/or control logic.

Silicon compilers such as Cathedral series, LAGER compiler.


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Hardware describing languages (HDL)

Describe behavior not implementation

Make model independentof technology Model complete systems

Specification ofsub-module functions

Speed up simulation oflarge systems

Standardized text format


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Design entry

Text:

Tool

independent

Good fordescribing

algorithms Bad for getting

an overview of alarge design


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Add-on tools Block diagrams to get overview of hierarchy Graphical description of final state machines

(FSM)

Generates synthesizable HDL code

Language sensitive editors

Waveform display tools

From Visual HDL, Summit design


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2. RTL Synthesis

RTL-synthesis programs take an RTL descriptionand convert it to a set of registers andcombinational logic.

RTL descriptions are captured using HardwareDescription Language (HDL).

HDL description includes Control flow using if-then-else and case statements. Arithmetic and logic operations.

Register specification and allocation. Sequential Vs parallel operations.

RTL compiler converts a HDL description into a setof registers and combinational logic.

RTL synthesis tool: Synopsys VHDL Compiler.


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3. Logic synthesis

HDL compilation (from VHDL or Verilog)

Registers: Where storage is required

Logic: Boolean equations, if-then-else, case, etc.

Logic optimization Logic minimization (similar to Karnaugh maps)

Finds logic sharing between equations

Maps into gates available in given technology

Uses local optimization rules6 basic CMOS gates

3 basic CMOS gates

3 logic gates


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Logic Optimization

Logic optimization programs take logicdescriptions generated by RTL synthesis

and optimize the logic network of the gatesto meet both speed and area constraints.

The register are then reunited withoptimized logic.

The physical layout then may beimplemented using available automatictechniques.


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Logic Optimization contd

Net listLogic equation

optimization

Compile

input input

Extract

Net-list generation(Technology mapping)


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Logic Optimization contd.

Generally, the logic optimization systems divide theproblem into two stages: A technology independent phase in which the logic is

optimized according to algebraic and/or Booleantechniques. A technology mapping phase, that translates the

technology independent description to specific librarycells.

A typical logic optimization flow:

Network organization Two-level minimization Algebraic decomposition of two-level logic expression into

multi-level logic expression (weak division) Iterative improvement


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Software tools for logic synthesis

Software tools for logic synthesis targetingASICs Design Compiler by Synopsys

Encounter RTL Compiler by Cadence Design Systems

TalusDesign by Magma Design Automation

BooleDozer: Logicsynthesistoolby IBM (internalIBM EDA tool)

Software tools for logic synthesis targeting FPGAs Encounter RTL Compiler by Cadence DesignSystems

LeonardoSpectrumand Precision(RTL / Physical)by MentorGraphics

Synplify (PRO / Premier)by Synplicity

BlastFPGA by Magma DesignAutomation Quartus II integrated Synthesis byAltera

XST (delivered withinISE)by Xilinx

DesignCompilerUltra and ICCompilerby Synopsys

IspLeverby Lattice Semiconductor

GeneXproTools - Software forLogicSynthesis


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4. Structural-to-Layout Synthesis

Automatically converts the net-list of gatesand registers to physical layout.

Includes two phasesPlacement

Routing

Placement:

Placement is the task of placing modules adjacentto each other to minimize area and delay.

There are two mainly used automated algorithmsfor placement.


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4. Structural-to-Layout Synthesis contd

Min-cut Algorithm: It takes the top-level modules to be placed and finds two

equal area-groupings of sub-blocks with the minimumnumber of signal interconnections.

These two blocks are then placed in the top and bottom halfof a conceptual final layout.

Same process is repeated for these two halves, splitting theconceptual layout into quarters and so on until the leaf cellsare reached.

This algorithm is very fast and gives good performance.

Another popular technique is similar tothermal annealing. Modules are initially allowed to move randomly and the

temperature of the layout is evaluated by applying somemeasures such as routing area and timing.

As the layout cools, the routing and/or timing improves.


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4. Structural-to-Layout Synthesis contd

Routing:

A router connects the modules with wires.

Different types of routers are:Channel routers are used to route rectangular

channels.

Switchbox routers are used to route more

complex channels.Maze routers are used to route any configuration

but have comparatively long running times.


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5. Layout Synthesis

The layout of regular structures such as RAMs,ROMs, PLAs registers, data paths and multipliersmay be synthesized by software generators.

These programs take a number of parameters asinput and automatically create a custom physicallayout.

Some systems create actual mask layout tuned toa particular process, while others create symbolic

layouts that may be compacted to suit a particulartechnology. The combination of symbolic layout, a powerful

language and a good CAD tools may createpowerful layout generators with minimum effort.


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Design capture tools

1. HDL Design

2. Schematic Design3. Layout Design

4. Floor-planning

5. Chip Composition


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1. HDL Design

The behavior and/or structure of a system may becaptured in HDL such as VHDL, ELLA, Verilog and

modified high level languages such as C, Pascal.


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2. Layout Design

Layout can be captured via code or interactivegraphic editors.

A good color editor is strongly required ifsubstantial layout editing is to be performed.

Design rule checking (DRC) programs allowsinteractive checking of DRC errors and circuit-

connectivity issues.


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3. Schematic Design

Schematic editor provide a means to draw andconnect components.

The schematic editors provides Creating, selecting and deleting parts.

Changing the graphic view by panning, zooming or othermeans.

Selecting an electrical node and interrogating it for state,

connections, capacitance etc. Running an attached simulator.


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4. Floorplanning

Floorplanning is the exercise of arranging blocks of layoutwithin a chip to minimize area or maximize speed.

Floorplan editors provide graphical feedback about the sizeand placement of modules without showing internal layoutdetails.

The editors also show connectivity information betweenmodules in the form of rats-nest wiring diagram, wherethe connected ports of modules are connected by straight

lines. The floorplanning may be done automatically but many times

a much better job can be done manually.


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Design Verification Tools

1. Simulation

Circuit-level Simulation

Timing Simulation

Logic-level Simulation

Switch-level simulation

Mixed mode simulation


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