Vlsi Unit 5 Notes

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PRATHYUSHA INSTITUTE OF TECHNOLOGY AND MANAGEMNET DEPARTMENT OF ECE CLASS: VII SEM, ECE SUB. CODE/ SUB. NAME: EC 1401 /VLSI DESIGN TOPICS COVERED: UNIT III SPECIFICATIONS USING VERILOG HDL: (i) VLSI design Flow (ii) Identifiers (iii)Gate primitives (iv)Behavioral modeling (v) Switch Level Modeling (vi)Timing controls (vii) (viii) Procedural assignments Conditional Statements

(ix)Structural and gate level description of Ripple carry adder, 3:8 Decoder, Priority encoder, Comparator in Verilog . PART A 1.What is HDL? HDL stands for Hardware Description language. There are two types of HDLs: VHDL Very high speed Integrated circuit Hardware Description Language Verilog HDL 2.What is Verilog? Verilog is a general purpose hardware descriptor language. It is similar in syntax to the C programming language. It can be used to model a digital system at many levels of abstraction ranging from the algorithmic level to the switch level. 3. What are the various modeling used in Verilog? (i). Gate-level modeling (Or) Structural modeling (ii). Data-flow modeling

(iii) Switch-level modeling (iv)Behavioral modeling 4. What is structural gate-level modeling? Structural modeling describes a digital logic networks in terms of the components that make up the system. Gate-level modeling is based on using primitive logic gates and specifying how they are wired together. 5. What is Switch-level modeling? Verilog allows switch-level modeling that is based on the behavior of MOSFETs.Digital circuits at the MOS-transistor level are described using the MOSFET switches. Eg; nmos,pmos,cmos,rnmos,rpmos,rcmos 6. What are identifiers? Identifiers are names of modules, variables and other objects that we can reference in the design. Identifiers consists of upper and lower case letters, digits 0 through 9, the underscore character(_) and the dollar sign($). It must be a single group of characters. Examples: A014, a ,b, in_o, s_out Keywords: Reserved Identifiers are known as Keywords. Eg: assign, module,end Escaped Identifiers : It is a way of providing printable ASCII characters and it starts with a \ (backslash ) character. 7. What are the value sets in Verilog? Verilog supports four levels for the values needed to describe hardware referred to as value sets. Value levels Condition in hardware circuits 0 Logic zero, false condition 1 Logic one, true condition X Unknown logic value Z High impedance, floating state 8. Give the classifications of timing control? Methods of timing control: (i). Delay-based timing control (ii). Event-based timing control (iii) Level-sensitive timing control Types of delay-based timing control: (i). Regular delay control (ii). Intra-assignment delay control (iii). Zero delay control Types of event-based timing control: (i). Regular event control (ii). Named event control (iii). Event OR control (iv). Level-sensitive timing control 9. Give the different arithmetic operators?

Operator symbol Operation performed Number of operands * Multiply Two / Divide Two + Add Two - Subtract Two % Modulus Two ** Power (exponent) Two 10. Give the different bitwise operators. Operator symbol Operation performed Number of operands ~ Bitwise negation One & Bitwise and Two | Bitwise or Two ^ Bitwise xor Two ^~ or ~^ Bitwise xnor Two ~& Bitwise nand Two ~| Bitwise nor Two 11. What are gate primitives? Verilog supports basic logic gates as predefined primitives. Primitive logic function keyword provide the basics for structural modeling at gate level. These primitives are nstantiated like modules except that they are predefined in verilog and do not need a module definition. The important operations are and, nand, or, xor, xnor, and buf(non-inverting drive buffer). 12. Define Pull gates. Pull gates have only one output with no inputs. There are two types of pull gates in Verilog : pullup and pulldown. Syntax : pullgate name (output variable); Eg: pullup PUP(control); The output variable Control is assigned logic 1 always. 13. Give the two blocks in behavioral modeling. (i). An initial block executes once in the simulation and is used to set up initial conditions and step-by-step data flow (ii). An always block executes in a loop and repeats during the simulation. 14. What are the types of typical gate delays in Verilog HDL? In real circuits, logic gates have delays associated with them: (i) Rise delay (ii) Fall Delay (iii) Turn off delay 15. What are the types of conditional statements? 1. No else statement Syntax : if ( [expression] ) true statement; 2. One else statement

Syntax : if ( [expression] ) true statement; else false-statement; 3. Nested if-else-if Syntax : if ( [expression1] ) true statement 1; else if ( [expression2] ) true-statement 2; else if ( [expression3] ) true-statement 3; else default-statement; The [expression] is evaluated. If it is true (1 or a non-zero value) true-statement is executed. If it is false (zero) or ambiguous (x), the false-statement is executed. 16.. Name the types of ports in Verilog Types of port Keyword Input port Input Output port Output Bidirectional port inout 17. What are the types of procedural assignments? 1. Blocking assignment 2. Non-blocking assignment 18.What is a task in Verilog? A task is like a procedure that provides the ability to execute common piece of code from several different places in a description. 19. What is a continuous statement in Verilog HDL? Continuous assignment statement is the most basic statement in Dataflow modeling used to drive a value onto a net. Syntax : assign = expression; Eg: assign #5 sum = a^ b; 20. Why do you require sensitivity list? The sensitivity list is used to specify the event which flags off the execution of the statements inside a block. Syntax : always @ (sensitivity list) Eg: (i)always @(posedge clock); (ii)always @(a,b); 21. Give the basic syntax of Verilog HDL. Syntax: module (Variable list); Input ; Output < variable list>; .

. endmodule Eg: module halfadder(a,b,sum,carry);

PART B 5. Explain in detail the VLSI design flow.(May 08/May 09)(12) The flowchart of designing a VLSI circuit is given below:Design Specification

Behavioral Description

RTL Description

Functional Verification and Testing Logic Synthesis /Timing Verification

Logic Design Process

Gate level Netlist

Logical Verification and Testing Floor Planning /Automatic Place and r route

Physical Design Process

Physical Layout

Layout verification


Design Specification: In this stage, functionality, interface and overall architecture of the digital circuit to be designed is described abstractly. Once the behavioral level design description is ready, it is tested extensively with the help of a simulation tool. Behavioral Description and RTL Description: The design at this level has to be extended with the help of known functional blocks and it is the next level of detailed description. Once again the design is tested for its functionality.RTL description that is register transfer language explains the design in the form of data flow. Functional verification and Testing: Design descriptions are tested for their functionality at every level - behavioral, data flow and gate. This is to check whether al l the functions are carried out as expected and to rectify them. This is carried out by the simulation tool. Logic Synthesis: The corresponding hardware realization of the circuit is carried at this level. The circuits are realized through FPGA or ASIC. Logic synthesis converts the RTL description into gate level net list. Gate level net list: A gate level net list is a description of the circuit in terms of gates and connections between them. Logic synthesis tool ensures that the gate level net list meets timing, area and power specifications. PHYSICAL DESIGN: Floor Planning: In this step, the sizes of all the functional blocks are calculated and locations are assigned. The main objective of this step is to keep the highly connected blocks physically close to each other. Blocks with I/O pins are kept close to the periphery; those which interact frequently are kept close together.

Placement: The objectives of the placement step are: Routing: Once the designer has floor planned a chip and the logic cells have been placed, it is time to make the interconnections by routing the chip. There are two types of routing : Global routing and Detailed routing The goal of the global router is to provide complete instructions to the detailed router on where to route .The main objective of this step is to reduce the interconnect length and area and to reduce the delays in the critical path. Implementation: Once the placement and routing are completed, the performance specifications are computed and verified. After verification, the design of the VLSI circuit is implemented in an IC. Minimize the critical net delays Make the chip as dense as possible Minimize the power dissipation Minimize the interconnect congestion Minimize the timing requirement Minimize cross talk Minimize the interconnect length:

2.Write a note on gate primitives in Verilog HDL.(8 Marks ) Verilog HDL has the capability of gate level modeling. The following are the bult in primitive gates in VErilog HDL:(i)

Multiple input gates: These gates have one or more than one input with one output. Eg: or,and,nand,nor,xor,xnor

Syntax: multiple input gate type (output A,input 1, input2.,input n) Eg: or or1(A,B,C,D,S1,);


Multiple output gates; These gates have only one input with multiple outputs. These gates can be used in an application where the output of a gate has to drive more than one load. Eg: buf,not Syntax: multiple output gate type (input A,output 1, output2.,ouyput n) Eg: buf buf1(A,S1, S2,S3);


Tristate gates; These gates have an additional control signal.The input is driven to the outpu