VLSI Physics, Characterization and Technology Activities at IIT BombayMicroelectronics Group,Department of Electrical Engineering2002

http://www.ee.iitb.ac.in/~microel

Prof. V. Ramgopal Rao

OverviewMain thrust in silicon CMOS devicesExtensive work on physics, characterization and technology aspects of CMOS and other compound semiconductorsDeveloped novel characterization techniques for CMOS which are currently used by industryProjects of national importanceLarge number of projects from multinational industriesExtensive consultation work for industry

Faculty - CMOS Physics, Technology and CharacterizationA. N. ChandorkarS. DuttaguptaR. LalS. Mahapatra

V. Ramgopal RaoD. K. SharmaJ. VasiR.O.Dusane (ME&MS)

Areas of R & DTechnology for CMOS and novel process development (down to 50 nm technology node)Development of novel electrical characterization techniques for Bulk and SOI MOSFETsSolar Cells on Flexible SubstratesSensorsSilicon CMOS physics (SOI and Bulk)Bio-MEMSEmerging AreasInteraction between VLSI technology and designStrong Interdisciplinary activity

Technology CMOSTechnologies for Special Applications (for radiation and other hazardous environments)Novel Unit Process Development/OptimizationFull process integration for Novel structuresIn-house development of process equipment Solar Cells on Flexible Substrates Sensors

Bio-MEMS (Please see Prof. R.Lals presentation)

FacilitiesClass 1000 Clean Room with a 5 mm CMOS FacilityExcellent characterization facilitySEM; photoluminescenceVLSI design workstationsSimulation workstationsVarious TCAD tools and Design SoftwareIntel Microelectronics LabTCS VLSI Design Lab

Fabrication Facilities IIT Bombay

Fabrication LaboratorySet-up in late 1980sFull CMOS 2 wafer process facility worth over 5 croresOne of its kind in an academic institutionAll equipment in working condition Several oxidation/diffusion furnaces Low pressure and atmospheric pressure CVD/Hot-Wire CVD furnaces Plasma Implantation system Mask aligner and photolithography Several vacuum evaporation systems Plasma processing systems Rapid Thermal Processing System Class 100 clean benches Fabrication monitoring equipment like SEM, ellipsometer, surface profiling, 4-probe, etc.

RTP System

A Novel CMOS Process Integration for Sub 50 nm Technologies ..1 Full CMOS process integration with :Hot-Wire CVD (HWCVD) Silicon Nitride as gate dielectric In-situ doped low temperature (

Process Flow ..2We have already made the first devices, and further process optimization is currently underway.

Solar Cells on Flexible SubstratesThe defect density of a-Si:H is minimum (~1015 cm-3) at a growth temperature of 200 - 250 C.Substrate Material Requirement: Stable at 200 - 250 C. Undeformed Impurity-free Plastics (Polyimide) Stainless Steel foil

Lightweight- ideal for millitary and space applications

Roll-to-roll process allows for ease of integration power everywhere!

Potential low cost technologies on the horizon-organic solar cellsApplication of Flex Solar Cells

Flexible Solar Cells : Device structurei- a-Si:HTextured TCOZnOp- a-SiC:Hn- a-Si:H30% T Ag Glass / TCO / p / i / n / Ag SS / ZnO / p / i / n /AgVoc Doped layersJsc i-layer defect density Light trappingFF i-layer defect density Interfaces

Rigid (TCO/Glass) vs. Flex (SS) J-VProperties of a-Si:H films (p, i, and n) were optimized for solar cells deposited on TCO/glass.h~ 8%h~ 2.5%

Future Directions Flexible Solar CellsDevelop a low temp technique to get texturing on flexible substrates Multijunction a-Si solar cells to reduce instabilityExplore alternatives: microcrystalline Si, Organic cellsHigh throughput roll-to-roll deposition process critical for commercialization

Sensors 1Objective Sensor for heavy metalscandidates: Mercury, Leadbroad range of concentrationschemical speciation field portable for in situ measurement

Sensors 2environmental assessmentcontaminant and remediation monitoringsmart waste site developmentElectrochemical Sensors Polythiophene based sensors

First Demonstration of ..Sub 100 nm Channel Length Lateral Asymmetric Channel (LAC) n-and p-MOSFETs on Bulk and SOI Substrates (in collaboration with University of California, Los Angeles)

Planar Doped Barrier vertical MOSFETs down to 60 nm channel lengths and demonstration of velocity overshoot effects due to the delta channel doping (in collaboration with the Universitaet der Bundeswehr, Munich, Germany)

In-situ Doped Polysilicon and Gate quality Nitride Depositions for CMOS Technologies using a novel Hot-wire CVD process

High Performance Sub 100 nm MNSFETs using Jet-Vapor-Deposited Nitride as a Gate Insulator (in collaboration with Prof. T.P.Ma, Yale University and Prof. J.C.S.Woo, UCLA)

CMOS CharacterizationExtensive experimental work on sub-quarter micron Lateral Asymmetric Channel MOSFETs for Mixed Signal Applications

CMOS Reliability Characterization for Digital and Analog Applications

Reliability Characterization for Flash Memories

Characterization of Vertical MOSFETs down to 60 nm Channel Lengths

Novel Techniques for Plasma Damage Characterization in CMOS Devices

New electrical techniques for Bulk and SOI MOSFET interface characterization

Facilities - Characterization Shielded probe stations with thermochuck (-60oC to +150oC) SEM with Electron-beam induced currents (EBIC) and voltage contrast attachments Large number of electrometers, Source-Measure-Units, Pulse Generators, Capacitance meters, bridges and plotters, signal analyzers etc. Photoluminescence setup High-, low- and combined high-low frequency C-V measurements High-field stressing of MOS and bipolar devices Avalanche injection measurements Bias-temperature and triangular voltage sweep (TVS) measurements DLTS I-V measurements of MOS and bipolar devices Charge pumping measurements, including defect profiling Hot-carrier measurements Gate transfer and delay characteristics Complete AC/DC Characterization facility for Non-volatile memories

Bulk and SOI MOSFETs Mixed Signal CMOS Device Optimization Charge Pumping Techniques Floating Body Effects in SOI Flicker Noise Measurements Plasma Process Induced Damage Atomic Force/Scanning Tunneling Microscope studies for defects Channel and Source/Drain Engineering for CMOS Hot-carrier Effects in CMOS and Flash Memories Gate Oxide Characterization and Reliability analysis Low-Temperature oxides Novel CMOS Device Structures Radiation Effects Molecular ElectronicsExtensive Characterization work related to

Silicon CMOS physics CMOS Device Degradation Alleviating the Floating Body Effects in SOI MOSFETs Channel Engineering for Sub 100 nm MOSFET Optimization Velocity Overshoot Effects Short-Channel Effects Ultra-thin oxide Characterization Defect generation in ultra-thin Silicon oxides/nitrides Radiation effects, hot-carrier effects, high-field stressing, oxide breakdown, and ESD related issues in MOSFETs Fringing field effects in high-K gate dielectrics Quantum effects in ultra-short channel MOSFETs DNA Conduction Solar Cells Sensors

Emerging Areas Molecular Electronics

Molecular Electronics at IIT Bombay(Collaborators: Prof. Soumyo Mukherji, Bio-medical Engg. and Prof. Ravikanth, Chemistry Dept., IIT Bombay)Electronic conduction in DNA studied by: Electron transfer rate reactions Direct electronic conduction

Attach specific molecular devices to specific portions on a DNA array using a variety of linker porphyrins (Synthesis done. Electrical characterization underway) Nanoelectrode Fabrication

Sponsored ProjectsProjects of National Importance (Space, Defense)Projects cover all areas of Microelectronics & VLSIProjects from major government agencies, and leading Indian & international companies

Some Ongoing Projects: Physics & Technology

Radiation Hard Technology for Space Applicaions (DOE)Microfabricated silicon sensors (MHRD)Sub 100 nm CMOS technology Development (MHRD)Silicon sensors for electroporation (Praman Technology)Characterization of SiGe HBTs (DST)Characterization of vertical MOS transistors (Siemens)

Some Ongoing Projects: Modeling & SimulationDevelopment of a hot-carrier simulator (Motorola)Modeling of power semiconductor devices (GE)RF MOSFET Models (IME, Singapore)Oxide scaling effects on design issues (Intel)

Some Ongoing Projects: VLSI Design & CAD ToolsInterconnect capacitance extraction by Monte Carlo (Intel)Interconnect parasitics extraction (SAS)High-speed comparator design (TII)Design issues with high-k dielectrics (Intel)VLSI Design training (MIT, TCS)

Industry CollaborationsProjects with Indian industry: BEL, ITI, SAS, TI, Cypress, ControlNet, SCL etcProjects with international industry: Intel, Motorola, GE, Siemens, National, NTT, SunIndustry sponsorship of studentsContinuing Education Programs for industry

University CollaborationsCollaborations with other IITs, Universities of Bombay, PuneCollaborations with International universities likeUCLA, UCSB, Yale University (USA)Hong Kong University of Sc. & Tech. (HK)Delft University (The Netherlands)University of Bundeswehr (Germany)Griffith University (Australia)NUS, IME, NTU, IHPC (Singapore)

PublicationsOver 30 publications every year in major journals and conferencesOver 40 technical reports in last 10 yearsCover all areas of interestDetails at www.ee.iitb.ernet.in/~microel/

ConclusionsMost active Microelectronics & VLSI group in IndiaExcellent research/fabrication facilitiesProjects of national importanceProjects from Indian & international industryMajor teaching programs at all levels