VLSI Physical Design Automation Professor Jason...
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CS258F 2002S Prof. J. Cong 1 CS 258F VLSI Physical Design Automation Professor Jason Cong Computer Science Department Jason Cong 2 VLSI Physical Design Automation 1-1 Objectives: Obtain a general understanding of IC designs. Understand the process of VLSI layout design Study the basic algorithms used in layout design of VLSI circuits. Learn about the physical design automation techniques used in the best-known academic and commercial layout systems. Get know hot research topics and problems.
Transcript of VLSI Physical Design Automation Professor Jason...
CS258F 2002S
Prof. J. Cong 1
CS 258F
VLSI Physical Design Automation
Professor Jason CongComputer Science Department
Jason Cong 2
VLSI Physical Design Automation
1-1
Objectives:
Obtain a general understanding of IC designs.Understand the process of VLSI layout designStudy the basic algorithms used in layout design of VLSI circuits.Learn about the physical design automation techniques used in the best-known academic and commercial layout systems.Get know hot research topics and problems.
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Course Requirements
• Prerequisites– CS 180 and CS 51A– Consent of instructor
• Grading Policy– 30% homeworks– 30% midterm– 40% class project and term paper
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Contact Information
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My office address: Boelter Hall, 4711
My office hour: Tu 4-5pm
E.mail: [email protected]
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Website for Lecture Notes
• http://cadlab.cs.ucla.edu/~cong/cs258f_handouts.html• For class attendees only. Please don’t distribute.
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Chapter 1Introduction to VLSI Design
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SystemSpecification
ChipManual
Automation
Large number of devices
Optimization requirements for high performance
Time-to-market competition
Cost
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VLSI Design Cycle
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VLSI Design Cycle
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System SpecificationFunctional DesignLogic DesignCircuit DesignPhysical DesignDesign verificationFabricationPackaging, Testing and Debugging
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System Specification
Functional Design
Logic Design
Circuit Design
X=(AB*CD)+(A+D)+(A(B+C))
Y=(A(B+C))+AC+D+A(BC+D))
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VLSI Design Cycle
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Physical Design
Fabrication
Packaging
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VLSI Design Cycle (cont.)
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Physical design converts a circuit description into a geometric description. This description is used to manufacture a chip. The physical design cycle consists of
1 Partitioning
2 Floorplanning and Placement
3 Routing
4 Compaction
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Physical Design
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Physical Design Process
Design Steps:Partition & ClusteringFloorplan & Placement
clk
clk clk
a
a
aPin AssignmentGlobal RoutingGlobal RoutingDetailed Routing
Methodology:Divide-and-Conquer
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Physical Design CyclePhysical Design
Circuit Design
(a)
(b)
(c)
(d)
Partitioning
Floorplanning&
Placement
Routing
Compaction
Fabrication
cutline 2
cutline 1
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More than 10 million transistor
Performance driven designs
Time-to-Market
Design cycle
High performance, high cost
…...
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Complexities of Physical Design
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Technology (um) 0.25 0.18 0.15 0.13 0.10 0.07Year 1997 1999 2001 2003 2006 2009
# transistors 11M 21M 40M 76M 200M 520MOn-Chip Clock (MHz) 750 1200 1400 1600 2000 2500
Area (mm2) 300 340 385 430 520 620Wiring Levels 6 6-7 7 7 7-8 8-9
Moore’s Law and NTRS’97
• Moore’s Law– The min. transistor feature size decreases by 0.7X every three
years (Electronics Magazine, Vol. 38, April 1965)– True in the past 30 years!
• 1997 National Technology Roadmap for Semiconductors
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Productivity Gap
xxxxxx
x 21%/Yr. Productivity growth rate
x
58%/Yr. Complexity growth rate
1
10
100
1,000
10,000
100,000
1,000,000
10,000,000
199810
100
1,000
10,000
100,000
1,000,000
10,000,000
100,000,000
Logi
c Tr
ansi
stor
s/C
hip
(K)
Tran
sist
or/S
taff-
Mon
th
Chip Capacity and Designer Productivity2003
Source: NTRS’97
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Design Challenges in Nanometer Technologies
• Interconnect-limited designs– Interconnect performance limitation– Interconnect modeling complexity– Interconnect reliability– Impact of new interconnect materials
• High degree of on-chip integration– Complexity and productivity– Limitation of current design abstraction and hierarchy– System on a chip– Power barrier
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Complexity of VLSI circuits
Full custom
Performance Size Cost Market time
Standard Cell Gate Array FPGA
Different design styles
Cost ,Flexibility,Performance
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Design Styles
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Full Custom Design StylePad Metal Via Metal 2
I/OData Path
ROM/RAM
PLA
A/D ConverterRandom logic
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Standard Cell Design StyleVDD Metal 1
CellMetal 2
Feedthrough GND
D C C B
A C C
D C D B
C C C B
Cell A
Cell C
Cell B
Cell D Feedthrough cell
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Gate Array Design Style
A
B
C
A
BC
VDD Metal1 Metal2
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FPGA Design Style
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Programmable logicProgrammable interconnectsProgrammable inputs/outputs
Field-Programmable Gate-Arrays (FPGAs)
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Comparisons of Design Styles
full-custom standard cell gate array FPGA
cell size variable fixed height * fixed fixed
cell type variable variable fixed programmable
cell placement variable in row fixed fixedinterconnections variable variable variable programmable
* uneven height cells are also used
style
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Area
Performance
Fabrication layers
style
full-custom standard cell gate array FPGA
compact
high
compactto moderate moderate large
highto moderate
moderate low
ALL ALL routing layers
none
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Comparisons of Design Styles
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Printed Circuit Board PCB
Multi-Chip Module MCM
Wafer Scale Integration WSI
Packaging
Area
Performance, cost
The increasing complexity and density of the semiconductor devices are driving the development of more advanced VLSI packaging and interconnection approaches.
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Packaging Styles
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Printed Circuit Board Model
Large number of layers (150a pitch)
Larger area
Low performance
Low cost
PackagePlated through holes
IC ( a )
( b )
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MCM Model
Up to 36 layers ( 75a pitch)Moderate to small areaModerate to high performanceHigh costHeat dissipation problems
IC ( a )
( b )
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Wafer Scale Integration
Small number of layers (VLSI technology- 6a pitch)
Smallest area
Significant yield problems
Very high performance
Significant heat dissipation problems
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Comparisons of Packaging Styles
Technology Figure of Merit(inches/psec. density inches/sq in)
WSIMCMPCB
28.014.62.2
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Merit = propagation speed (inches/psec.) * interconnection density (inches/sq. in).
Interconnect resistance was not considered
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History of VLSI Layout ToolsYear Design Tools
1950 - 1965
1965 - 1975
1975 - 1985
1985 – 1995
1995 -- present
Manual Design
Layout editorsAutomatic routers( for PCB)Efficient partitioning algorithm
Automatic placement toolsWell Defined phases of design of circuitsSignificant theoretical development in all phases
Performance driven placement and routing toolsParallel algorithms for physical designSignificant development in underlying graph theoryCombinatorial optimization problems for layout
Interconnect layout optimization, Interconnect-centric design, physical-logical codesign
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ACM IEEE Design Automation Conference (DAC)
International Conference on Computer Aided Design(ICCAD)
IEEE International Symposium on Circuits and Systems (ISCAS)
International Conference on Computer Design(ICCD)
Design, Automation and Test in Europe, Conference and Exhibition (DATE)
Asia and South Pacific Design Automation Conference (ASP-DAC)
International Symposium on Physical Design (ISPD)
VLSI CAD Conferences
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VLSI CAD Journals
IEEE Transactions on CAD of Circuits and systems (T-CAD)
ACM Trans. on Design Automation of Electronic Systems (TODAES)
Integration: The VLSI Journal
IEEE Transactions on Circuits and Systems
IEEE Trans. on VLSI Systems
IEEE Trans. on Computers
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ACM SIGDA (Special Interest Group on Design Automation)
IEEE Circuits and System Society
Design Automation Technical Committee(DATC) of IEEE Computer Society
VLSI CAD Organization
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SummaryPhysical design is one of the steps in the VLSI design cyclePhysical design is further divided into clustering, partitioning, floorplanning, placement, global and detailed routing , and compactionThere are four major design styles -- full custom, standard cell, gate array, and FPGAs.There are three alternatives for packaging of chips -- PCB, MCM and WSIAutomation reduces cost, increases chip density, reduces time-to-market, and improves performance.CAD tools currently lag behind fabrication technology, which is hindering the progress of IC technology
