Vlsi Part a Programs

8/3/2019 Vlsi Part a Programs

1/11

verilog code for inverter

module inv(a, b);input a;output b;assign b=~a;

endmodule

test bench for inverter

module in_v;reg a;wire b;inv uut (

.a(a),

.b(b));

initial begina = 0;#100;a=1;#100;a=0;end------------------------------------------------------------------

verilog code for buffer

module buff(a, b);input a;

output b;assign b=a;

endmodule

test bench for buffer

module buf_v;reg a;wire b;buff uut (

.a(a),

.b(b));

initial begina = 0;#100;a=1;#10;a=0;endendmodule


2/11

----------------------------------------------------------------------

verilog code for basic gates

module basic(a, b, c1, c2, c3, c4, c5);input a;input b;

output c1;output c2;output c3;output c4;output c5;

assign c1=a&b;assign c2=a|b;assign c3=~(a&b);assign c4=~(a|b);assign c5=a^b;endmodule

test bench for basic gates

module bg_v;reg a;reg b;wire c1;wire c2;wire c3;wire c4;wire c5;basic uut (

.a(a),

.b(b),

.c1(c1),

.c2(c2),

.c3(c3),

.c4(c4),

.c5(c5));

initial begina = 0;b = 0;#50;a=0;b=1;#50;a=1;b=0;

#50;a=1;b=1;endendmodule----------------------------------------------------------------

verilog code for sr flipflop

module srff(s, r, clk, q, qb);


3/11

input s;input r;input clk;output q;output qb;reg q;reg qb;always@(posedge clk)beginif(s==0 & r==0)q=q;else if(s==0 & r==1)q=1'b0;else if(s==1 & r==0)q=1'b1;elseq=1'b0;qb=~q;endendmodule

test bench for sr flipflop

module sr_v;reg s;reg r;reg clk;wire q;wire qb;srff uut (

.s(s),

.r(r),

.clk(clk),

.q(q),

.qb(qb));

initialclk=0;always#10 clk=~clk;initial begins = 0;r = 0;clk = 0;#50;s=0;

r=1;#50;s=1;r=0;#50;s=1;r=1;endendmodule-----------------------------------------------------------


4/11

verilog code for jk flipflop

module jkff(j, k, clk, q, qb);input j;input k;input clk;

output q;output qb;reg q;reg qb;

always@(posedge clk)beginif(j==0 & k==0)q=q;else if(j==0 & k==1)q=1'b0;else if(j==1 & k==0)q=1'b1;elseq=~q;qb=~q;endendmodule

test bench for jk flipflop

module jk_v;reg j;reg k;reg clk;wire q;wire qb;

jkff uut (.j(j),.k(k),.clk(clk),.q(q),.qb(qb)

);initialclk=0;always#10 clk=~clk;initial begin

j = 0;k = 0;

#50;j=0;k=1;#50;

j=1;k=0;#50;

j=1;k=1;


5/11

endendmodule-------------------------------------------------------------------

verilog code for t flipflop

module tflipflop(t, clk, q, reset);

input t;input clk;output q;input reset;reg q;always @(posedge clk)beginif(reset==1)q=1'b0;else if (t==0)q=q;elseq=~q;endendmodule

test bench for t flipflop

module tff_v;reg t;reg clk;reg reset;wire q;tflipflop uut (

.t(t),

.clk(clk),

.q(q),

.reset(reset));

initial clk=0;always #10 clk=~clk;initial begint = 0;clk = 0;reset = 0;#50;reset=1;t=1;#50;reset=0;

endendmodule---------------------------------------------------

verilog code for d flipflop

module dflipflop(d, clk, en, q);input d;input clk;input en;


6/11

output q;reg q;always @(posedge clk)beginif (en==0)q=1'b0;elseq=d;endendmodule

test bench for d flipflop

module dff_v;reg d;reg clk;reg en;wire q;dflipflop uut (

.d(d),

.clk(clk),

.en(en),

.q(q));

initial clk=0;always #10 clk=~clk;initial begind = 0;clk = 0;en = 0;#50;en=1;d=1;

endendmodule----------------------------------------------------

verilog code for successive approximation

module SAR(r, l, e, w, clk, q);input [7:0] r;input l;input e;input w;input clk;output [7:0] q;reg [7:0] q;

integer k;always @ (posedge clk)if (l)q0;k=k-1)q[k-1]


7/11

endendmodule

test bench for successive approximation

module SAR_T_v;

reg [7:0] r;reg l;reg e;reg w;reg clk;wire [7:0] q;SAR uut (

.r(r),

.l(l),

.e(e),

.w(w),

.clk(clk),

.q(q));

initial clk=0;always #5 clk=~clk;initial beginr = 0;l = 0;e = 0;w = 0;clk = 0;#100;l=1;w=0;e=0;#50

r=10101010;#10l=1'b0;e=1'b1;w=1'b0;#50w=1'b1;#100w=1'b0;endendmodule

----------------------------------------------------------

verilog code for 4bit async counter

module asy(clk, rst, q);input clk;input rst;output q;reg [3:0]q;always @(posedge clk, negedge rst)if(rst==0)


8/11

q=4'b0000;elseq


9/11

rst = 0;#50;rst=1;endendmodule-----------------------------------------------------------------

verilog code for serial addermodule seriadd(a, b, clk, load, sum);input [7:0] a;input [7:0] b;input clk;input load;output [8:0] sum;reg [7:0] ina;reg [7:0]inb;reg[8:0] oreg;wire c0,s0;

always@(posedge clk)beginif(load==1)beginina=a;inb=b;endelsebeginina[7:0]={1'b0,ina[7:1]};inb[7:0]={1'b0,inb[7:1]};endendalways@(posedge clk)begin

if(load==1)beginoreg=8'd0;endelsebeginoreg[8]=c0;oreg[7:0]={s0,oreg[7:1]};endendassign s0=ina[0]^inb[0]^oreg[8];assign c0=(ina[0]&inb[0])|(ina[0]&oreg[8])|(oreg[8]&inb[0]);assign sum=oreg;

endmodule

test bench for serial adder

module sadd_v;reg [7:0] a;reg [7:0] b;reg clk;


10/11

reg load;wire [8:0] sum;seriadd uut (

.a(a),

.b(b),

.clk(clk),

.load(load),

.sum(sum));

initial clk=1'b0;always #10 clk=~clk;initial begina =8'd100;b =8'd25;load = 0;#10;load=1;#10;load=0;#80;

$display("a=%d",a,"b=%d",b,"sum=%d",sum);endendmodule------------------------------------------------------------------------------------------

verilog code for parallel adder

module padd(a, sum, b);input [7:0] a;output [8:0] sum;input [7:0] b;reg[8:0] sum;reg tc=1'b0;integer i;

always@(a,b)beginfor(i=0;i


11/11

initial begina = 8'd25;b = 8'd25;#100;a=8'd23;b=8'd20;#100;endendmodule----------------------------------------------------------------------------------------

verilog code for transmission gate

module tragat(a, b, sel);input a;output b;input sel;

reg b;always@(a,sel)beginif(sel)b=a;elseb=~a;endendmodule

test bench for transmission gate

module tg_v;reg a;reg sel;wire b;tragat uut (

.a(a),

.b(b),

.sel(sel));

initial begina = 0;sel =1'b0;#50;a=1;#50;sel=1'b1;

a=0;endendmodule

Vlsi Part a Programs

Documents

Transcript of Vlsi Part a Programs