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7/31/2019 vlsi op2

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II.SEQUENTIAL LOGIC CIRCUITS USING VHDL

7. FLIP FLOPS

AIM:

To design and simulate JK, RS ,D and T using VHDL.

APPARATUS REQUIRED:

PC with windows XP

XILINX 9.2i software

PROCEDURE:

Open the Xilinx 9.2i software

Close if any other project is opened

Open a new file from file menu and specify the project name

Choose the language and simulator to be used

In new source wizard select VHDL module, then in the next window assign I/O pins and

select finish, now the design summary will be displayed

Enter the code to be executed, save it and synthesis the entered code

If the program is in structural model we have to add component in sources, do right click

and add source.

To simulate the output the test bench waveform is chosen from the new source. Before giving input select behavioral simulation in sources, now give the input in

simulation window and save it.

Now simulate the wave form and verify the output.

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JK FLIPFLOP:

PROGRAM :

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating

---- any Xilinx primitives in this code.

--library UNISIM;

--use UNISIM.VComponents.all;

entity jkff is

Port ( j,k,clk : in STD_LOGIC;

q : inout STD_LOGIC);

end jkff;

architecture Behavioral of jkff is

begin

process(j,k,clk)

beginif(clk'event and clk='1') then

if(j='0')and(k='0')then

q<=q;

elsif(j='1')and(k='0')then

q<='1';


q<='0';


q<=(not q);

end if; end if;

end process;end Behavioral;

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RTL SCHEMATIC DIAGRAM FOR JK FLIPFLOP:

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OUTPUT WAVEFORM FOR JK FLIPFLOP:

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SR FLIPFLOP :

PROGRAM :

library IEEE;






--library UNISIM;


entity rsff isPort ( s,r,clk : in STD_LOGIC;


end rsff;

architecture Behavioral of rsff is

begin

process(s,r,clk)

begin

if(clk'event and clk='1')then

if(s='0' and r='0')then

q<=(not q);

elsif(s='0' and r='1')then

q<='0';


q<='1';


q<=’X’; end if;

end if;

end process;

end Behavioral;

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RTL SCHEMATIC DIAGRAM FOR SR FLIPFLOP :

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OUTPUT WAVEFORM FOR SR FLIPFLOP :

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D FLIPFLOP :

PROGRAM :

library IEEE;






--library UNISIM;


entity dff is

Port ( D : in STD_LOGIC;

clk : in STD_LOGIC;

Q : out STD_LOGIC);

end dff;

architecture Behavioral of dff is

begin

process(D,clk)

begin


Q<=D;

end if;

end process;

end Behavioral;

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RTL SCHEMATIC DIAGRAM FOR D FLIPFLOP :

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OUTPUT WAVEFORM FOR D FLIPFLOP :

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T FLIP FLOP:

PROGRAM :

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;




--library UNISIM;


entity tff is

Port ( t,clk : in STD_LOGIC;

q,qb : inout STD_LOGIC);end tff;

architecture Behavioral of tff is

begin

process(t,clk)

begin


if(q\ =’0’ and qb \ =’0’) then

q<=’0’; else

q<=(not q);end if;

end if;

end process;

end Behavioral;

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RTL SCHEMATIC DIAGRAM FOR T FLIPFLOP :

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OUTPUT WAVEFORM FOR T FLIPFLOP:

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8.COUNTER

AIM:

To design and simulate UP-DOWN counter using VHDL.

APPARATUS REQUIRED:

PC with windows XP


PROCEDURE:


Close if any other project is opened Open a new file from file menu and specify the project name






and add source.

To simulate the output the test bench waveform is chosen from the new source.

Before giving input select behavioral simulation in sources, now give the input in



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PROGRAM:

library IEEE;






--library UNISIM;


entity upc is

Port ( clk : in STD_LOGIC;

updown : in STD_LOGIC;

clr : in STD_LOGIC;

q : out STD_LOGIC_VECTOR (3 downto 0));

end upc;

architecture Behavioral of upc is

signal tem : std_logic_vector( 3 downto 0);

begin

process(clr,clk)

begin

if(clr='1')then

tem <="0000";

elsif(clk'event and clk='1') then

if(updown='1') then

tem <= tem+1;

else

tem <= tem-1;

end if;

end if;

end process;

q <= tem;

end Behavioral;

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RLT SCHEMATIC DIAGRAM :

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OUTPUTWAVEFORM:

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9.SHIFT REGITERS

AIM:

To design and simulate SISO,SIPO ,PISO and PIPO using VHDL

APPARATUS REQUIRED:

PC with windows XP


PROCEDURE:








and add source.





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SERIAL IN SERIAL OUT:

PROGRAM:

library IEEE;use IEEE.STD_LOGIC_1164.ALL;





--library UNISIM;


entity siso is

Port ( clk : in STD_LOGIC;re : in STD_LOGIC;

s : in STD_LOGIC;

q : out STD_LOGIC);

end siso;

architecture Behavioral of siso is

signal reg:STD_LOGIC_VECTOR(4 DOWNTO 1);

begin

process(re,clk)

begin

if(clk'event and clk ='1')then

if(re ='1')then

reg <= "0000";

q <= '0';

else

reg <= s & reg(4 downto 2);

q <= reg(4);

end if;

end if;

end process;

end Behavioral;

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RTL SCHEMATIC DIAGRAM FOR SERIAL IN SERIAL OUT:

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OUTPUT WAVEFORM:

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SERIAL IN PARALLEL OUT:

PROGRAM:

library IEEE;





--library UNISIM;


entity SIPO is

Port ( data,clk,reset : in STD_LOGIC;

q : out STD_LOGIC_VECTOR (4 downto 1));

end SIPO;

architecture Behavioral of SIPO is

signal reg: STD_LOGIC_VECTOR(4 DOWNTO 1);

signal count:std_logic_vector(3 downto 1);

begin

process(clk,reset)

begin


if(reset='1')then

reg<="0000";

q<="0000";

count<="000";

else

reg<=data & reg(4 downto 2);

count<=count+1;

q<=reg;

if(count="100")then

count<="000";

end if;

end if;

end if;

end process;

end Behavioral;

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RTL SCHEMATIC DIAGRAM FOR SERIAL IN PARALLEL OUT:

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OUTPUT WAVEFORM FOR SERIAL IN PARALLEL OUT:

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PARALLEL IN SERIAL OUT:

PROGRAM:

library IEEE;






--library UNISIM;


entity pis017 isPort ( input : in STD_LOGIC_VECTOR (3 downto 0);

clk,reset,input_accept : in STD_LOGIC;

q : out STD_LOGIC);

end pis017;

architecture Behavioral of pis017 is

signal reg:std_logic_vector(3 downto 0);

signal count:std_logic_vector(2 downto 0);

begin

process(clk,reset)

begin

if(reset='1')then

count<="000";

reg<="0000";

elsif(clk'event and clk='1')then

if(input_accept='1')then

reg<=input;

else

q<=reg(0);

reg<='0' & reg(3 downto 1);

count<=count+1;

end if;

if(count="100")then

count<="000";

reg<="0000";

end if;

end if;

end process;

end Behavioral;

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RTL SCHEMATIC DIAGRAM FOR PARALLEL IN SERIAL OUT:

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OUTPUT WAVEFORM FOR PARALLEL IN SERIAL OUT:

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PARALLEL IN PARALLEL OUT:

PROGRAM:

library IEEE;





--library UNISIM;


entity ppiippoo is

Port ( clk,reset : in STD_LOGIC;

input : in STD_LOGIC_VECTOR (4 downto 1);output : out STD_LOGIC_VECTOR (4 downto 1));

end ppiippoo;

architecture Behavioral of ppiippoo is

signal reg:STD_LOGIC_VECTOR(4 downto 1);

begin

process(clk,reset)

begin


if(reset='1')then

reg<="0000";

output<="0000";

else

reg<=input;

output<=reg;

end if;

end if;

end process;

end Behavioral;

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RTL SCHEMATIC DIAGRAM FOR PARALLEL IN PARALLEL OUT:

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OUTPUT WAVEFORM FOR PARALLEL IN PARALLEL OUT:

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10.FREQUENCY DIVIDER

AIM:

To design and simulate frequency divider using VHDL.

APPARATUS REQUIRED:

PC with windows XP


PROCEDURE:








and add source.





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PROGRAM :

library IEEE;


use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;



--library UNISIM;


entity tfli is

Port (

t : in STD_LOGIC;

clr : in STD_LOGIC;clk : in STD_LOGIC;


end tfli;

architecture Behavioral of tfli is

begin

process (t,clk,clr)

begin

if(clr='1')then

if(clk' event and clk = '1')thenif(t='0')then

q <= q;

else

q <= (not q);

end if;

end if;

else

q <= '0';

end if;

end process;

end Behavioral;

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RTL SCHEMATIC DIAGRAM FOR FREQUENCY DIVIDER:

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OUTPUT WAVEFORM FOR FREQUENCY DIVIDER:

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