Vlsi Lab Manua2(1)

VLSI Lab Manual

VLSI LAB MANUAL (06ECL77)

Subject Code : 06ECL77 IA Marks : 25

No. OF Practical Hrs/Week : 03 Exam Hours : 03

Total no. OF Practical Hrs. : 42 Exam Marks : 50

PART – A

DIGITAL DESIGN

ASIC-DIGITAL DESIGN FLOW

1. Write Verilog Code for the following circuits and their Test Bench for verification, observe

the waveform and synthesis the code with technological library with given Constraints*. Do the

initial timing verification with gate level simulation.

i. An inverter

ii. A Buffer

iii. Transmission Gate

iv. Basic/universal gates

v. Flip flop -RS, D, JK, T

vi. Serial & Parallel adder

vii. 4-bit counter [Synchronous and Asynchronous counter]

viii. Successive approximation register [SAR]

* An appropriate constraint should be given

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PART - B

ANALOG DESIGN

Analog Design Flow

1. Design an Inverter with given specifications*, completing the design flow mentioned below:

a. Draw the schematic and verify the following

i) DC Analysis

ii) Transient Analysis

b. Draw the Layout and verify the DRC, ERC

c. Check for LVS

d. Extract RC and back annotate the same and verify the Design

e. Verify & Optimize Time, Power and Area to the given constraint***

2. Design the following circuits with given specifications*, completing the design flow

mentioned below:


i) DC Analysis

ii) AC Analysis

iii) Transient Analysis


c. Check for LVS

d. Extract RC and back annotate the same and verify the Design.

i) A Single Stage differential amplifier

ii) Common source and Common Drain amplifier

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3. Design an op-amp with given specification* using given differential amplifier Common

source and Common Drain amplifier in library** and completing the design flow mentioned

below:


i) DC Analysis

ii). AC Analysis



c. Check for LVS


4. Design a 4 bit R-2R based DAC for the given specification and completing the design flow

mentioned using given op-amp in the library**.


i) DC Analysis

ii) AC Analysis



c. Check OF LVS


5. For the SAR based ADC mentioned in the figure below draw the mixed signal schematic and

verify the functionality by completing ASIC Design FLOW.

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PART – A

DIGITAL DESIGN

Steps to use Xilinx tool:

Start the Xilinx Project Navigator by using the desktop shortcut or by using the

Start Programs Xilinx ISE Project Navigator.

In the Project Navigator window go to FILE New project Click on new source

verilog module and give the name inverter.v Define portsFinish

Select devicesGeneral purpose Spartan 3 ISE simulatorverilog

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In the create new source window select source type as verilog module give file name

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assign inputs and outputs click next finishyesnext nextfinish

Double click on source filecomplete the verilog code for inverter

Check syntax, and remove errors if present

Simulate the design using ISE Simulator Highlight inverter.v file in the Sources in

Project window. To run the Behavioral Simulation, Click on the symbol of FPGA device

and then right clickClick on new sourceClick on verilog text fixtureGive file

name with _tb finish

Generate test bench file after initial begin assign value for inputs Click on simulate

behavioral model see the output.

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INVERTER

1. Write Verilog Code of an inverter circuits and their Test Bench for verification

Objective:

To design an inverter in verilog using xilinx tool and verify it on ISE simulator

Tools : Xilinx ISE simulator .

Symbol and truth table:

Design Description:

NOT gate, for example, will invert the data. NOT gate has 1 input and 1 output. Whatever

the value is at the input, the output will have the opposite value. If the input is a 1, the output is a 0.

If the input is a 0, the output is a 1. B = ~A

Waveform:

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VERILOG CODE

//Data flow model

module in1(a, b);

input a; output b;

assign b=~a;

endmodule

// Behavioural model

module in1(a, b);

input a;

output reg b;

always @(a)

begin

b=~a;

end

endmodule

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//Test bench structure

module iin_v;

reg a; // Inputs

wire b; // Outputs

// Instantiate the Unit Under Test (UUT)

in1 uut (.a(a),.b(b) );

initial begin

a = 0;

#100; // Wait 100 ns for global reset to finish

// Add stimulus here

a = 1;

#100; // Wait 100 ns for global reset to finish

end

endmodule

Waveform:

Conclusion: Design of an inverter is done using xilinx tool and is verified.

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BUFFER

2. Write Verilog Code of a Buffer circuits and their Test Bench for verification

Objective:

To design a buffer in verilog using xilinx tool and verify it on ISE simulator.


Symbol and Truth table:

Design Description:

If we were to connect two inverter gates together so that the output of one fed into the

input of another, the two inversion functions would "cancel" each other out so that there would

be no inversion from input to final output: For this purpose, a special logic gate called a buffer is

manufactured to perform the same function as two inverters. Its symbol is simply a triangle, with

no inverting "bubble" on the output terminal: B = A

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Waveform:

// VERILOG CODE:

//Data flow model

module buffer(a, b);

input a;

output b;

assign b=a;

endmodule

// Behavioural

module buffer (a, b);

input a;

output reg b;

always @(a)

begin

b=a;

end

endmodule


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module iin_v;

reg a; // Inputs

wire b; // Outputs


in1 uut (.a(a),.b(b) );

initial begin

a = 0; #100;

a = 1; #100;

end

endmodule

Waveform:

Conclusion: Design of a buffer in xilinx tool and is verified according to the truth Table.

Transmission Gate

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3. Write Verilog Code of a transmission gate circuits and their Test Bench for verification

Objective:To design a transmission gate in verilog using xilinx tool and verify it on ISE simulator.


Circuit Diagram and Truth table:

A(Select)

IN OUT

0 X X1 0 01 1 1

Design Description:

Transmission gate is an electronic element. It is a good non-mechanical relay, built

with CMOS technology. It can be used to simplify digital logic circuits or to switch analog

signals, and so is also known as an analog gate, analogue switch or electronic relay depending on

its use. It is made by the parallel combination of an nMOS and a pMOS transistor with the input

at the gate of one transistor being complementary to the input at the gate of the other transistor.

//VERILOG CODE

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http://en.wikipedia.org/wiki/PMOS_logic

http://en.wikipedia.org/wiki/NMOS_logic

http://en.wikipedia.org/wiki/Analogue_switch

http://en.wikipedia.org/wiki/Logic_gate

http://en.wikipedia.org/wiki/Analog_electronics

http://en.wikipedia.org/wiki/CMOS

http://en.wikipedia.org/wiki/Relay

http://en.wikipedia.org/wiki/Electronics

VLSI Lab Manual

module transmission_gate(A,IN,OUT);

input A,IN;

output OUT;

wire Abar;

assign Abar=~A;

pmos(OUT,Abar,IN);

nmos(OUT,A,IN);

endmodule

//Test bench code

module tg_tb_v;

reg A; reg IN; // Inputswire OUT; // Outputs

// Instantiate the Unit Under Test (UUT)transmission_gate uut (

.A(A),

.IN(IN),

.OUT(OUT) );

initial begin// Initialize InputsA = 0; IN = 0;#100;

A = 0; IN = 1;#100;A = 1; IN = 0;#100;A = 1; IN = 1;#100;

end endmodule

Waveform:

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Conclusion: Design of a transmission gate in xilinx tool and is verified according to the truth Table.

BASIC GATES

4. Write Verilog Code of a Basic gates circuits and their Test Bench for verification.

Objective:

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To design a basic gates in verilog using xilinx tool and verify it on ISE simulator.


AND GATE:

Symbol and Truth table of AND gateDesign Description:

The output of an AND gate is only equal to 1 if both inputs (A AND B in this case) are

equal to 1. Otherwise the output is equal to 0. The above picture shows a two input AND gate,

but an AND gate can have many inputs. In any case, no matter how many inputs it has, the

output is only equal to 1 if all the inputs are equal to 1, otherwise the output is 0.

The equation of an AND gate is: C = A & B

Waveform:

OR GATE:

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Symbol and Truth table of OR gate

Design Description:

The output of an OR gate is equal to 1 if either input (A OR B in this case) is equal to

one. If neither input is equal to 1, the output is equal to zero. Again, the above picture shows a

two input OR gate, but an OR gate can have as many inputs as you like. The output will be equal

to 1 if any of the inputs is equal to 1.

The equation of an OR gate is: C = A + B

Waveform:

EX-OR GATE:

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Symbol and Truth table of XOR gate:

Design Description:

The output of an XOR gate is equal to 1 if either input (A or B in this case) is equal to

one, but equal to zero if both inputs are equal to zero or if both inputs are equal to 1. This is the

difference between an OR gate and an XOR gate, an OR gates output will equal 1 if both inputs

are equal to 1.

The equation OF an XOR gate is: C = A ^ B

Waveform:

NAND GATE:

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Symbol and Truth table of NAND gate:

Design Description:

A variation on the idea of the AND gate is called the NAND gate. The word "NAND" is

a verbal contraction of the words NOT and AND. Essentially, a NAND gate behaves the same as

an AND gate with a NOT (inverter) gate connected to the output terminal. To symbolize this

output signal inversion, the NAND gate symbol has a bubble on the output line. The truth table

for a NAND gate is as one might expect, exactly opposite as that of an AND gate:

As with AND gates, NAND gates are made with more than two inputs. In such cases, the

same general principle applies: the output will be "low" (0) if and only if all inputs are "high"

(1). If any input is "low" (0), the output will go "high" (1).

The equation of an XOR gate is: C = ~(A &B)

Waveform:

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NOR GATE:

Symbol and Truth table of NOR gate:

Design Description:

A variation on the idea of the OR gate is called the NOR gate. The word "NOR" is a

verbal contraction of the words NOT and OR. Essentially, a NOR gate behaves the same as an

OR gate with a NOT (inverter) gate connected to the output terminal. To symbolize this output

signal inversion, the NOR gate symbol has a bubble on the output line. The truth table for a NOR

gate is as one might expect, exactly opposite as that of an OR gate:

As with OR gates, NOR gates are made with more than two inputs. In such cases, the

same general principle applies: the output will be "low" (0) if any inputs are "high" (1). If both

the inputs is "low" (0), the output will go "high" (1).

Waveform:

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VERILOG CODE

//Data flow model

module gat(c,d,a,o,na,no,x);

input c,d ;

output a,o,x,no,na;

assign o=(c|d); //o -> or gate output

assign no=~(c|d); // no-> nor gate output

assign a=(c&d); // a-> and gate output

assign na=~(c&d); // na-> nand gate output

assign x=(c^d); // x-> xor gate output

endmodule


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module basi_v;

reg c; reg d;// Inputs

wire a; wire o; wire na; wire no; wire x; // Outputs


gat uut (.c(c), .d(d), .a(a), .o(o), .na(na), .no(no), .x(x) );

initial begin

c = 0; d = 0;#100;

c = 0;d = 1;#100;

c = 1;d = 0;#100;

c = 1;d = 1;#100;

end

endmodule

Waveform:

Conclusion: Design of Basic gates in xilinx tool and is verified according to the truth Table.

FLIP FLOPS

5. Write Verilog Code of Flip flops circuits and their Test Bench for verification

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Objective:

To design Flip flops in verilog using xilinx tool and verify it on ISE simulator


i) D FLIPFLOP

Symbol and truth table

Design Description:

D Flip Flop has two inputs, the clock and the D input, and one output, Q. In the picture

D is connected to the node A, and Q is connected to the node B, so these are essentially names OF

the same thing. As can be seen in the truth table, the output is equal to the input on the rising edge

OF the clock. If there is no rising clock edge, the output will remain in its current state.

Waveform:

// VERILOG CODE

module d_ff( d, clk, q, q_bar);

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input d, clk;

output q, q_bar;

reg q;

reg q_bar;

always @ (posedge clk)

begin

q <= d;

q_bar <= !d;

end

endmodule


module cc_v;

reg d;reg clk; // Inputs

wire q; wire q_bar; // Outputs


d_ff uut (.d(d), .clk(clk), .q(q), .q_bar(q_bar) );

initial begin

d = 0; clk = 0; #100;// Initialization of Inputs

d = 0; clk = 1; #100;

d = 1; clk = 1; #100;

d = 1; clk = 0; #100;

end

endmodule

Waveform:

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ii) T FLIPFLOP

Symbol and truth table// VERILOG CODE

module t_ff ( t, clk, q, q_bar);

input t, clk;

output q, q_bar;

reg q;

reg q_bar;

always @ (posedge clk)

begin

q = ~t;

q_bar = ~q;

end

endmodule


module cc_v;

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reg t; reg clk; // Inputs

wire q; wire q_bar; // Outputs


t_ff uut ( .t(t), .clk(clk), .q(q), .q_bar(q_bar) );

initial begin

t = 0; clk = 0; #100; // Initialization of Inputs

t = 0; clk = 1; #100;

t = 1; clk = 1; #100

t = 1; clk = 0; #100;

end

endmodule

Waveform:

iii) SR FLIPFLOP:

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Symbol and truth table

Design Description:

An SR Flip Flop is an arrangement of logic gates that maintains a stable output even after the

inputs are turned off. This simple flip flop circuit has a set input (S) and a reset input (R). The set

input causes the output of 0 (top output) and 1 (bottom output). The reset input causes the opposite to

happen (top = 1, bottom =0). Once the outputs are established, the wiring of the circuit is maintained

until S or R go high, or power is turned of to the circuit.

Waveform:

// VERILOG CODE

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module sr_ff(clk,s,r,q,qb);

input clk,s,r;

output rer q,qb;

always @(clk,s,r)

begin

if(clk==1)

begin

if(s==0 & r==1)

begin

q=0; qb=~q;

end

else if(s==1 & r==0)

begin

q=1; qb=~q;

end


begin

q=q; qb=~q;

end


begin

q=1'bz; qb= 1'bz;

end

end

end

endmodule


module rsff_v;

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reg clk ;reg s; reg r; // Inputs

wire q; wire qb; // Outputs


ff uut ( .clk(clk), .s(s), .r(r), .q(q), .qb(qb) );

initial begin

clk = 0; s = 1; r = 0;#100; // Initialization of the Inputs

clk = 1; s = 0; r = 1;#100;

clk = 1; s = 1; r = 0;#100;

clk = 1; s = 0; r = 0;#100;

clk = 1; s = 1; r = 1;#100;

end

endmodule

Waveform:

IV) JK FLIP FLOP:

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Symbol and truth table:

Design Description:

The J-K flip-flop is perhaps the most widely used type of flip-flop. Its function is

identical to that of the S-R flip flop in the SET, RESET and HOLD conditions of operation. The

difference is that the J-K flip-flop does not have any invalid states. The logic symbol for the J-K

flip-flop is presented in Figure 3-8 and its corresponding truth table is listed in Table 3-5. Notice

that for J=1 and K=1 the output toggles, that is to say that the output at time t is complemented at

time t+1.

Waveform:

// VERILOG CODE

module jk_ff(clk,j,k,q,qb);

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input clk, j, k;

output q,qb;

reg q,qb;

always @(clk,j,k)

begin

if(clk==1)

begin

if(j==0 & k==1)

begin

q=0; qb=~q;

end

else if(j==1 & k==0)

begin

q=1; qb=~q;

end


begin

q=q; qb=~q;

end


q=~q; qb=~q;

end

end

endmodule


module jk_v;

reg clk, j, k ; // Inputs

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wire q, qb; // Outputs


jk_ff uut (.clk(clk), .j(j), .k(k), .q(q), .qb(qb) );

initial begin

clk = 0; j = 0; k = 0; #100;

clk = 1; j = 1; k = 0; #100;

clk = 1; j = 0; k = 1; #100;

clk = 1; j = 0; k = 0; #100;

clk = 1; j = 1; k = 1; #100;

end

endmodule

Waveform:

Conclusion: Design of Flipflops(D,T,SR,JK) in xilinx tool and is verified according to the truth Table.

PARALLEL ADDER

6. Write Verilog Code of Parallel adder circuits and their Test Bench for verification

Objective:To design parallel adder in verilog using xilinx tool and verify it on ISE simulator

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Block diagram of parallel adder.

Design Description: Parallel adders are digital circuits that compute the addition of variable binary strings of equivalent or different size in parallel.A number of full adders may be added to the ripple carry adder or ripple carry adders of different sizes may be cascaded in order to accommodate binary vector strings of larger sizes. For an n-bit parallel adder, it requires n computational elements (FA).

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It is composed of four full adders. The augend’s bits of x are added to the addend bits of y respectfully of their binary position Each bit 6 addition creates a sum and a carry out. The carry out is then transmitted to the carry in of the next higher-order bit. The final result creates a sum of four bits plus a carry out (c4).

// VERILOG CODE

module padd(x,y, c, sum, cout); input [3:0] x,y; input c; output [3:0] sum; output cout;

FA stage0(x[0],y[0],c,sum[0],c1); FA stage1(x[1],y[1],c1, sum[1],c2); FA stage2(x[2],y[2],c2, sum[2],c3); FA stage3(x[3],y[3],c3,sum[3],cout);

endmodule

// Function of full Adder

module FA(a,b,cin, s,c0); input a,b,cin; output s,c0;

assign s=a^b^cin; assign c0=(a&b)|(b&cin)|(cin&a);

endmodule

// Test bench code

module aaa_v;

reg [3:0] x; reg [3:0] y; reg c; // Inputswire [3:0] sum; wire cout; // Outputs

// Instantiate the Unit Under Test (UUT)padd uut (

.x(x),

.y(y),

.c(c),

.sum(sum),

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.cout(cout));

initial begin// Initialize Inputsx = 4'b0101;y = 4'b1100;c = 0;#100;

x = 4'b0001;y = 4'b1011;c = 1;#100;

x = 4'b1011;y = 4'b0101;c = 0;#100;

endendmodule

Waveform:

Conclusion: Design of Parallel Adder in xilinx tool and is verified according to the truth Table.

COUNTER

7. Write Verilog Code of counter circuits and their Test Bench for verification

Objective:To design counter in verilog using xilinx tool and verify it on ISE simulator


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Circuit Diagram: 1) 4bit Up Counter:

Block diagram and truth table of Up counter. Design Description:

In the 4-bit counter to the right, we are using edge-triggered master-slave flip-flops similar to those in the Sequential portion of these pages. The output of each flip-flop changes state on the falling edge (1-to-0 transition) of the T input.

The count held by this counter is read in the reverse order from the order in which the flip-flops are triggered. Thus, output D is the high order of the count, while output A is the

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low order. The binary count held by the counter is then DCBA, and runs from 0000 (decimal 0) to 1111 (decimal 15). The next clock pulse will cause the counter to try to increment to 10000 (decimal 16). However, that 1 bit is not held by any flip-flop and is therefore lost. As a result, the counter actually reverts to 0000, and the count begins again.

Waveform:

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2) 4 bit Down counter:

Block diagram and truth table of Down counter.

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// VERILOG CODE

module counter_1 (clock , reset , counter_out );

input clock ,reset ;

output [3:0] counter_out ;

reg [3:0] counter_out ;

always @ (posedge clock)

begin

if (reset == 0)

counter_out <= 4'b0000;

else

counter_out <= counter_out + 1;//for down cntr

counter_out<=counter_out-1;

end

endmodule

//Test bench code

module counter_tb_v;

reg clock; reg reset; // Inputs

wire [3:0] counter_out; // Outputs


counter_1 uut (

.clock(clock),

.reset(reset),

.counter_out(counter_out)

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);

initial begin

// Initialize Inputs

clock = 1; reset = 0; #10;

clock = 0;reset = 1; #10;

clock = 1; reset = 1; #10;// cntd for further counts;

end

endmodule

Waveform:

Up counter

Down counter

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3) Decade 4-bit Synchronous Counter:

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Waveform:

// VERILOG CODE

module counter_1 (clock , reset , counter_out );

input clock ,reset ;

output [3:0] counter_out ;

reg [3:0] counter_out ;

always @ (posedge clock)

begin

if (reset == 0)

counter_out <= 4'b0000;

else

counter_out <= counter_out + 1;

if(counter_out== 4'b1001)

counter_out<=4'b0000;

end

endmodule

//Test bench code

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module ssss_v;

reg clock; reg reset; // Inputs

wire [3:0] counter_out; // Outputs


counter_1 uut ( .clock(clock), .reset(reset), .counter_out(counter_out) );

initial begin

// Initialize Inputs



clock = 1;reset = 1; #10; //cntd for upto 14 counts;

end

endmodule

Waveform:

Conclusion: Design of Counters in xilinx tool and is verified according to the truth Table.

SUCCESSIVE APPROXIMATION ADC

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8. Write Verilog Code of A successive approximation ADC circuits and their Test Bench for verification

Objective:To design SAR in verilog using xilinx tool and verify it on ISE simulator


Circuit Diagram: successive approximation ADC:

Design Description:

A successive approximation ADC is a type of analog-to-digital converter that converts a continuous analog waveform into a discrete digital representation via a binary search through all possible quantization levels before finally converging upon a digital output for each conversion

The successive approximation Analog to digital converter circuit typically consists of four chief

subcircuits:

1. A sample and hold circuit to acquire the input voltage (Vin).

2. An analog voltage comparator that compares Vin to the output of the

internal DAC and outputs the result of the comparison to the successive

approximation register (SAR).

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http://en.wikipedia.org/wiki/Processor_register

http://en.wikipedia.org/wiki/Digital-to-analog_converter

http://en.wikipedia.org/wiki/Voltage

http://en.wikipedia.org/wiki/Analog_to_digital_converter

http://en.wikipedia.org/wiki/Quantization_(signal_processing)

http://en.wikipedia.org/wiki/Binary_search

http://en.wikipedia.org/wiki/Digital

http://en.wikipedia.org/wiki/Analog_signal

http://en.wikipedia.org/wiki/Analog-to-digital_converter

VLSI Lab Manual

3. A successive approximation register subcircuit designed to supply an

approximate digital code of Vin to the internal DAC.

4. An internal reference DAC that supplies the comparator with an analog voltage

equivalent of the digital code output of the SAR for comparison with Vin.

The successive approximation register is initialized so that the most significant bit (MSB) is equal to a digital 1. This code is fed into the DAC, which then supplies the analog equivalent of this digital code (Vref/2) into the comparator circuit for comparison with the sampled input voltage. If this analog voltage exceeds Vin the comparator causes the SAR to reset this bit; otherwise, the bit is left a 1. Then the next bit is set to 1 and the same test is done, continuing this binary search until every bit in the SAR has been tested. The resulting code is the digital approximation of the sampled input voltage and is finally output by the DAC at the end of the conversion (EOC).

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http://en.wikipedia.org/wiki/Binary_search_algorithm

http://en.wikipedia.org/wiki/Digital

http://en.wikipedia.org/wiki/Most_significant_bit

http://en.wikipedia.org/wiki/Comparator

VLSI Lab Manual

PART - B

ANALOG DESIGN

Design the circuits with given specifications*, completing the design flow mentioned below:


i) DC Analysis

ii) Transient Analysis


c. Check for LVS

d. Extract RC and back annotate the same and verify the Design

e. Verify & Optimize Time, Power and Area to the given constraint***

Steps to use Tanner tool:

i.SCHEMATIC (S-edit):

Start the tanner EDA by using the desktop shortcut or by using the

Start Programs tanner EDA tanner tool v13.0 S-edit.

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ii) Layout (L-edit):

Start Programs tanner EDA tanner tool v13.0 L-edit

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INVERTER

Design Description:

In digital logic an Inverter or a NOT gateis a logic gate which implements logical negation.

Netlist:

v1 vdd GND 5v2 vref GND 3.87v3 in+ GND 3.2v4 in- in+ SIN (0 2m 1k) AC 1.tran .01m 5m.dc lin source v4 -5 5 .1.ac dec 10 1 10g.print tran v(out) v(in-).print dc v(out).print ac vp(out) vdb(out).lib "C:\IMS\Technology_file\Generic_025.lib" TT.op.END

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VLSI Lab Manual

Layout:

Waveform:

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VLSI Lab Manual

SINGLE STAGE AMPLIFIER

Design Description:

The need of the amplifier is to amplify the weak input signal coming from transducers so that while traveling a longer distance signal or power would not get distorted and at the output stage we want, if we required lesser gain we will go for single stage amplifier. The predicted output gain of single stage amplifier should be 35 dB.

Netlist:

v1 vdd GND 5v2 vref GND 3.87v3 vinm GND 3.2v4 vinp vinm SIN (0 2m 1k) AC 1.tran .01m 5m.dc lin source v4 -5 5 .1.ac dec 10 10 10g.print tran v(out) v(vinp).print dc v(out).print ac vp(out) vdb(out).lib "C:\IMS\Technology_file\Generic_025.lib" TT

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VLSI Lab Manual

.op

.end

Layout:

Waveform:

COMMON SOURCE AMPLIFIER

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VLSI Lab Manual

Design Description:

A common-source amplifier, which amplifies the input voltage about 30 times. The gain of this amplifier is determined partly the transconductance of the MOSFET. This depends on the bias point in the circuit. This means that a change in the gate voltage causes a change in the drain current.

The drain current goes through a resistor. The capacitor connected to the source is supposed to act as a short circuit at the input frequency, so it and the source resistor can be ignored. A change in input causes a change in drain voltage. The predicted output gain is of common source amplifier should be 56.18 dB.

Netlist:

v1 vdd GND 5v2 vbias GND 3.87v3 vinm GND 3.2v4 vinp vinm SIN (0 2m 1k) AC 1.tran .01m 5m.dc lin source v4 -5 5 .1.ac dec 10 1 10g.lib "C:\IMS\Technology_file\Generic_025.lib" TT.print tran v(out) v(vinp).print ac vdb(out) vp(out).print dc v(out)

BGSIT, BG Nagar

VLSI Lab Manual

.op

.end

Layout:

Waveform:

COMMON DRAIN AMPLIFIER

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VLSI Lab Manual

Design Description:

Common-drain amplifier is also known as source follower or grounded drain amplifier the voltage at the source follows that the gate giving the circuit its popular name of source follower. It finds application in situation in which we need to connect a voltage signal source that is providing a signal of reasonable magnitude but has a very hih internal resistance to much smaller load resistance that has a unity gain voltage buffer amplifier. The predicted output gain is of common drain amplifier should be 57dB.

Netlist:

v1 vdd GND 5

v2 vbias GND 3.79

v3 vinm GND 3.1

v4 vinp vinm SIN (0 2m 1k) AC 1

.tran .01m 5m

.dc lin source v4 -5 5 .1

.ac dec 10 1 10g

.lib "C:\IMS\Technology_file\Generic_025.lib" TT

.print tran v(out) v(vinp)

.print ac vdb(out) vp(out)

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VLSI Lab Manual

.print dc v(out)

.op

Layout:

Waveform:

R2R DAC

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VLSI Lab Manual

Design Description:

An alternative to the binary weighted-input DAC is so called R/2R DAC which uses fewer unique resistor values. DAC design required several different precise input resistor values :one unique value per binary input bit.

The bits, either at 0 or operating voltage, enter the network via a resistor of a double value than the rest of the network. Each bit contributes its part to the resulting voltage on the output

Netlist:

v1 vdd GND 5

v2 vin GND 2.5

v3 b0 GND PULSE (5 0 0 1n 1n 500n 1000n)

v4 b1 GND PULSE (5 0 0 1n 1n 1000n 2000n)

v5 b2 GND PULSE (5 0 0 1n 1n 2000n 4000n)

v6 b3 GND PULSE (5 0 0 1n 1n 4000n 8000n)

.tran 10n 8500n

.print tran v(out)

.lib "C:\IMS\Technology_file\Generic_025.lib" TT

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VLSI Lab Manual

.op

.end

Layout:

Waveform:

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Vlsi Lab Manua2(1)

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