DESIGNVLSI

A. Albert RajT. Latha

VLSI DESIGN

A. ALBERT RAJ T. LATHAAssistant Professor Assistant Professor

Department of Electronics and Instrumentation EngineeringNoorul Islam College of Engineering

Kanyakumari

New Delhi-1100012008

VLSI DESIGNA. Albert Raj and T. Latha

© 2008 by PHI Learning Private Limited, New Delhi. All rights reserved. No part of this book may bereproduced in any form, by mimeograph or any other means, without permission in writing from thepublisher.

ISBN-978-81-203-3431-1

The export rights of this book are vested solely with the publisher.

Published by Asoke K. Ghosh, PHI Learning Private Limited, M-97, Connaught Circus,New Delhi-110001 and Printed by Mudrak, 30-A, Patparganj, Delhi-110091.

Preface xiii

1. INTRODUCTION 1–4

1.1 Evolution of VLSI Device Technology 11.2 Metal Oxide Semiconductor (MOS) and VLSI Technology 3Summary 4

2. BASIC MOS STRUCTURE 5–33

2.1 Introduction 52.2 Basic MOS Transistor Operation 6

2.2.1 Enhancement Mode Transistor Action 72.2.2 Depletion Mode Transistor Action 10

2.3 MOS Transistor Switches 102.3.1 Complementary CMOS Switch 11

2.4 NMOS Fabrication 122.5 Basic CMOS Technology 15

2.5.1 The p-well CMOS Process 152.5.2 The n-well CMOS Process 162.5.3 The Twin-Well Process 192.5.4 Silicon-On-Insulator Process 19

2.6 CMOS Process Enhancements 212.6.1 Interconnect 222.6.2 Circuit Elements 25

2.7 BiCMOS Technology 292.7.1 BiCMOS Fabrication in an n-well Process 322.7.2 Some Aspects of Bipolar and CMOS Devices 32

Summary 32Review Questions 33Short Answer Questions 33

iii

Contents

iv • Contents

3. MOS DEVICE CHARACTERISTICS 34–62

3.1 Introduction 343.2 Static Behaviour of the MOS Transistor 35

3.2.1 The Threshold Voltage 353.2.2 Current–Voltage Relations 393.2.3 A Model for Manual Analysis 423.2.4 MOS Transistor Transconductance gm and Output Conductance gds 423.2.5 MOS Transistor Figure of Merit, w0 43

3.3 Dynamic Behaviour of MOS Transistor 433.3.1 MOS Structure Capacitances 433.3.2 Channel Capacitance 443.3.3 Junction Capacitance 453.3.4 Capacitive Device Model 46

3.4 The Actual MOS Transistor—Secondary Effects 463.4.1 Threshold Variations 463.4.2 Source–Drain Resistance 473.4.3 Variation in I-V Characteristics 483.4.4 Subthreshold Conduction 493.4.5 CMOS Latchup 50

3.5 NMOS Inverter 503.6 Determination of Pull-up to Pull-down Ratio (Zp.u/Zp.d) for an

NMOS Inverter Driven by Another NMOS Inverter 523.7 Pull-up to Pull-down Ratio for an NMOS Inverter Driven Through One

or More Pass Transistors 543.8 Device Models for Simulation 56

3.8.1 MOS Models 563.8.2 DC MOSFET Model 563.8.3 High Frequency MOSFET Model 573.8.4 SPICE Models 60

Summary 62Review Questions 62Short Answer Questions 62

4. CMOS INVERTER DESIGN 63–89

4.1 Introduction 634.2 CMOS Inverter—DC Characteristics 654.3 Design Parameters of CMOS Inverter 75

4.3.1 Symmetric CMOS Inverter 764.3.2 Noise Margins of CMOS Inverter 774.3.3 Temperature Dependence of VTC of CMOS Inverter 784.3.4 Supply Voltage Scaling in CMOS Inverters 784.3.5 Power and Area Considerations 79

4.4 Switching Characteristics of CMOS Inverter 804.4.1 Estimation of CMOS Inverter Delay 81

4.5 CMOS—Gate Transistor Sizing 854.6 Stage Ratio 86

Contents • v

4.7 Power Dissipation 864.7.1 Static Dissipation 874.7.2 Dynamic Dissipation 874.7.3 Short-circuit Dissipation 874.7.4 Total Power Dissipation 874.7.5 Power Economy 88

Summary 88Review Questions 88Short Answer Questions 88

5. MOS CIRCUIT DESIGN PROCESSES 90–115

5.1 Introduction 905.2 Why Design Rules 905.3 MOS Layers 915.4 Stick Diagrams 91

5.4.1 Stick Layout Using NMOS Design 945.4.2 Stick Layout Using CMOS Design 95

5.5 Design Rules and Layout 965.5.1 Lambda (l) Based Design Rules 975.5.2 Double Metal MOS Process Rules 1015.5.3 CMOS Lambda-based Design Rules 102

5.6 Elements of Physical Design 1095.6.1 Basic Concepts 1105.6.2 Design Hierarchies 111

Summary 114Review Questions 114Short Answer Questions 114

6. SPECIAL CIRCUIT LAYOUTS 116–136

6.1 Introduction 1166.2 Tally Circuits 1176.3 NAND–NAND, NOR–NOR, and AOI Logic 1196.4 Exclusive-OR Structures 1226.5 Barrel Shifter 1276.6 Transmission Gates 1306.7 Latches and Flip-flops 131

6.7.1 CMOS Static Latches 1326.7.2 CMOS Dynamic Latches 132

6.8 Fan-in and Fan-out of CMOS Logic Design 134

Summary 136Review Questions 136Short Answer Questions 136

vi • Contents

7. SUPER BUFFERS, BiCMOS AND STEERING LOGIC 137–157

7.1 Introduction 1377.2 RC Delay Lines 1387.3 Super Buffers 139

7.3.1 NMOS Super Super Buffer 1417.3.2 NMOS Tristate Super Buffers and Pad-Drivers 1427.3.3 CMOS Super Buffers 1437.3.4 BiCMOS Gates 144

7.4 Dynamic Ratioless Inverters 1467.5 Large Capacitive Loads 1477.6 Pass-Transistor Logic 1487.7 General Function Blocks 152

7.7.1 NMOS Function Blocks 1537.7.2 CMOS Function Blocks 155

Summary 156Review Questions 156Short Answer Questions 156

8. CMOS COMBINATIONAL LOGIC CIRCUITS 158–178

8.1 Introduction 1588.2 Static CMOS Design 159

8.2.1 Complementary CMOS 1598.2.2 Ratioed Logic 1638.2.3 Pass-Transistor Logic 164

8.3 Dynamic CMOS Design 1668.3.1 Dynamic Logic: Basic Principles 1668.3.2 Speed and Power Dissipation of Dynamic Logic 1678.3.3 Signal Integrity Issues in Dynamic Design 1688.3.4 Cascading Dynamic Gates 171

8.4 Complex Logic Gates in CMOS 172

Summary 177Review Questions 177Short Answer Questions 178

9. CMOS SEQUENTIAL LOGIC CIRCUITS 179–197

9.1 Introduction 1799.2 Timing Metrics for Sequential Circuits 1809.3 Classification of Memory Elements 1819.4 Static Latches and Registers 183

9.4.1 Bistability Principle 1839.4.2 Multiplexer-Based Latches 1839.4.3 Master–Slave Edge-Triggered Register 1859.4.4 Low Voltage Static Latches 187

9.5 Dynamic Latches and Registers 1879.5.1 Dynamic Transmission-Gate Edge-Triggered Registers 1889.5.2 C2MOS—A Clock Skew Insensitive Approach 1899.5.3 True Single-Phase Clocked Register (TSPCR) 190

Contents • vii

9.6 Alternative Register Styles 1929.6.1 Pulse Registers 1929.6.2 Sense Amplifier-Based Registers 192

9.7 Non-bistable Sequential Circuits 1939.7.1 The Schmitt Trigger 1939.7.2 Monostable Sequential Circuits 1949.7.3 Astable Circuits 195

Summary 196Review Questions 196Short Answer Questions 197

10. DESIGN OF ARITHMETIC BUILDING BLOCKS 198–225

10.1 Introduction 19810.2 Datapaths 19910.3 The Adder 200

10.3.1 The Binary Adder: Definitions 20010.3.2 The Full-Adder: Circuit Design Considerations 20210.3.3 The Binary Adder: Logic Design Considerations 207

10.4 The Multiplier 21710.4.1 Multiplier: Definitions 21810.4.2 Partial-Product Generation 21910.4.3 Partial-Product Accumulation 22010.4.4 Final Addition 223

Summary 224Review Questions 224Short Answer Questions 225

11. PROGRAMMABLE LOGIC DEVICES 226–258

11.1 Introduction 22611.2 NMOS PLAs 227

11.2.1 NMOS PLA Layouts 22711.3 Other Programmable Logic Devices 232

11.3.1 Field Programmable Logic Array (FPLA) 23211.3.2 Programmable Array Logic (PAL) 23311.3.3 Dynamic Logic Arrays (DLAs) 233

11.4 The Finite-State Machine as a PLA Structure 23511.5 Complex Programmable Logic Devices (CPLDs) 237

11.5.1 CPLD Packaging and Programming 23911.6 Field Programmable Gate Arrays (FPGAs) 242

11.6.1 FPGA Packaging and Programming 24311.6.2 The XILINX Programmable Gate Array 25011.6.3 Implementation in FPGAs 25611.6.4 Design Flow 256

Summary 257Review Questions 258Short Answer Questions 258

viii • Contents

12. CMOS CHIP DESIGN 259–284

12.1 Introduction 25912.2 Design Strategies 260

12.2.1 Structured Design Strategies 26012.2.2 Hierarchy 26112.2.3 Regularity 26112.2.4 Modularity 26112.2.5 Locality 261

12.3 CMOS Chip Design Options 26212.3.1 Application Specific Integrated Circuits (ASICs) 26212.3.2 Types of ASICs 26212.3.3 Economics of ASICs 27212.3.4 CMOS Chip Design with Programmable Logic 277

Summary 283Review Questions 283Short Answer Questions 284

13. ROUTING PROCEDURES 285–307

13.1 Introduction 28513.2 Global Routing 285

13.2.1 Goals and Objectives 28513.2.2 Measurement of Interconnect Delay 28613.2.3 Global Routing Methods 28913.2.4 Global Routing Between Blocks 28913.2.5 Global Routing Inside Flexible Blocks 29113.2.6 Timing-Driven Methods 29313.2.7 Back-Annotation 294

13.3 Detailed Routing 29413.3.1 Goals and Objectives 29813.3.2 Measurement of Channel Density 29813.3.3 Algorithms 29913.3.4 Left-Edge Algorithm 29913.3.5 Constraints and Routing Graphs 29913.3.6 Area-Routing Algorithms 30213.3.7 Multilevel Routing 30313.3.8 Timing-driven Detailed Routing 30313.3.9 Final Routing Steps 304

13.4 Special Routing 30413.4.1 Clock Routing 30413.4.2 Power Routing 305

Summary 306Review Questions 306Short Answer Questions 306

Contents • ix

14. CMOS TESTING 308–351

14.1 Introduction 30814.2 Need for Testing 308

14.2.1 Functionality Tests 30914.2.2 Manufacturing Tests 30914.2.3 Test Process 310

14.3 General Concepts of Testing 31014.3.1 Reliability 31114.3.2 Reliability Modelling 312

14.4 Manufacturing Test Principles 31414.4.1 Fault Models 31414.4.2 Gate Level Testing 31714.4.3 Observability 32114.4.4 Controllability 32114.4.5 Fault Coverage 32114.4.6 Automatic Test Pattern Generation (ATPG) 32214.4.7 Fault Grading and Fault Simulation 32614.4.8 Delay Fault Testing 32714.4.9 Statistical Fault Analysis 32814.4.10 Fault Sampling 329

14.5 Design Strategies for Test 33014.5.1 Design for Testability 33014.5.2 Ad hoc Testing 33014.5.3 Scan-Based Test Techniques 33314.5.4 Self-Test Techniques 33914.5.5 IDDQ Testing 342

14.6 Chip-Level Test Techniques 34314.6.1 Regular Logic Arrays 34314.6.2 Memories 34314.6.3 Random Logic 344

14.7 System-Level Test Techniques 34414.7.1 Boundary Scan 344

14.8 Layout Design for Improved Testability 350

Summary 350Review Questions 350Short Answer Questions 350

15. VERILOG HDL 352–365

15.1 Introduction 35215.2 Basic Concepts 35215.3 Structural Gate-Level Modelling 354

15.3.1 Verilog by Example 35415.4 Switch-Level Modelling 35915.5 Design Hierarchies 363

Summary 365Review Questions 365Short Answer Questions 365

Vlsi Design

Publisher : PHI Learning ISBN : 9788120334311 Author : RAJ, A.ALBERT, LATHA, T.

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