Visible Things Industrial IoT Gateway

Visible Things

Industrial IoT Gateway User’s Manual

All information contained in these materials, including products and product specifications,

represents information on the product at the time of publication and is subject to change by

Avnet without notice. Please review the latest information published by Avnet through various

means, including the Avnet Visible Things website

https://silica.avnet.com/wps/portal/silica/marketstechnologies/internet-of-things/

User M

an

ual

https://silica.avnet.com/wps/portal/silica/marketstechnologies/internet-of-things/

Avnet Visible Things Platform User’s Manual

Rev. 1.02 Jun 26, 2017

Disclaimer

By using this Avnet® Visible Things Industrial IoT Gateway, the user accepts the following

terms. The Gateway is not guaranteed to be error free, and the User assumes the entire risk as

to the results and performance of the Gateway. The Gateway is provided by Avnet on an “as is”

basis without warranty of any kind whether express or implied, including but not limited to the

implied warranties of satisfactory quality, fitness for a particular purpose, title and non-

infringement of intellectual property rights with regard to the Gateway. Avnet expressly disclaims

all such warranties. Avnet or its affiliates shall in no event be liable for any loss of profit, loss of

data, loss of contract, loss of business, damage to reputation or goodwill, any economic loss,

any reprogramming or recall costs (whether the foregoing losses are direct or indirect) nor shall

Avnet or its affiliates be liable for any other direct or indirect special, incidental or consequential

damages arising out of or in relation to the use of this Gateway, even if Avnet or its affiliates

have been advised of the possibility of such damages.

Precautions

This product is only intended for use in a laboratory environment under ambient temperature

and humidity conditions. A safe separation distance should be used between this and any

sensitive equipment. Its use outside the laboratory, classroom, study area, or similar such area

invalidates conformity with the protection requirements of the Electromagnetic Compatibility

Directive and could lead to prosecution.

The product generates, uses, and can radiate radio frequency energy and may cause harmful

interference to radio communications. However, there is no guarantee that interference will not

occur in a particular installation. If this equipment causes harmful interference to radio or

television reception, which can be determined by turning the equipment off or on, you are

encouraged to try to correct the interference by one or more of the following measures:

• Ensure attached cables do not lie across the equipment

• Reorient the receiving antenna

• Increase the distance between the equipment and the receiver

• Connect the equipment into an outlet on a circuit different from that which the receiver is

connected

• Power down the equipment when not in use

• Consult the dealer or an experienced radio/TV technician for help NOTE: It is recommended

that wherever possible shielded interface cables should be used.

The product is potentially susceptible to certain EMC phenomena. To mitigate against them it is

recommended that the following measure be undertaken:

• The user is advised that mobiles phones should not be used within 10m of the product when

in use.

• The user is advised to take ESD precautions when handling the equipment.

The Avnet Renesas Synergy Gateway does not represent an ideal reference design for an end

product and does not fulfill the regulatory standards for an end product.


Rev. 1.02 Jun 26, 2017

Contents Chapter 1. Overview ............................................................................................................... 1

Chapter 2. Preface ................................................................................................................. 1

Purpose .................................................................................................................................. 1

Precautions ............................................................................................................................ 1

Chapter 3. Board Layout ........................................................................................................ 2

Component Layout ................................................................................................................. 2

Board Dimensions .................................................................................................................. 3

Chapter 4. Block Diagram ...................................................................................................... 4

Chapter 5. Input Power Sources ............................................................................................. 5

5V Direct (J5) ......................................................................................................................... 5

Silicon Labs Si3402 Power Over Ethernet (PoE) PD Interface and Switching Regulator ........ 5

USB Port (J3) ......................................................................................................................... 5

Chapter 6. Renesas Synergy S7G2 Microcontroller ............................................................... 6

Chapter 7. Development Tools ............................................................................................... 6

Chapter 8. Board Support Package (BSP) ............................................................................. 8

Chapter 9. Memory ................................................................................................................. 8

32 MB External SDRAM ......................................................................................................... 8

4 MB External Serial NOR Flash, MX25R3235 ......................................................................11

Chapter 10. Peripherals .......................................................................................................12

TD-Next TDM114 Camera/ON Semiconductor MT9M114 Image Sensor (J1) .......................12

TDM114 General Description: ............................................................................................12

MT9M114 Image Sensor General Description: ..................................................................13

NXP TJA1042 CAN Transceiver (J2) .....................................................................................14

USB Device Full-Speed (J3) ..................................................................................................16

USB Host High-Speed (J4) ....................................................................................................17

Audio Amplifier (J8) ...............................................................................................................19

STMicro MP23AB02B Microphone with MAXIM Integrated MAX9814 Amplifier (MIC1) .........20

Debugging Options (J9, P2) ..................................................................................................22

USB J-Link On-Board (J9) .................................................................................................22

JTAG/SWD/Trace (P2) .......................................................................................................22

Ethernet Ports (P1, P3) .........................................................................................................25

Microchip LAN9353 Ethernet Switch ..................................................................................25

LCD (CN1) ............................................................................................................................27

SemTech SX8650 LCD Touch Controller ..............................................................................29


Rev. 1.02 Jun 26, 2017

I/O Expansion ........................................................................................................................30

I/O Expander (U18, I2C address 0x25) ..............................................................................30

I/O Expander (U19, I2C address 0x27) ..............................................................................31

Pmod Compatible Expansion Connectors .............................................................................31

Pmod1 (CN4) .....................................................................................................................33

Pmod2 (CN2) .....................................................................................................................36

Pmod3 (CN3) .....................................................................................................................39

Pmod4 (CN5) .....................................................................................................................42

Pmod5 (CN6) .....................................................................................................................45

Pmod6 (CN7) .....................................................................................................................47

Push Buttons (S1-S4) ........................................................................................................48

Molex MicroSD Card Slot (J7) ...............................................................................................49

Laird WIFI/Bluetooth Low Energy (BLE) ................................................................................50

WIFI Module ......................................................................................................................50

BLE Module .......................................................................................................................51

NFC Reader ..........................................................................................................................54

LEDs (LED1-LED4) ...............................................................................................................55

Chapter 11. Security ............................................................................................................57

Chapter 12. Programming Methods .....................................................................................57

Chapter 13. Additional Information .......................................................................................58

Hardware Partner Information ...............................................................................................58


Rev. 1.02 Jun 26, 2017

Table of Figures Figure 1 – Component Layout (Top) .......................................................................................... 2 Figure 2 – Component Layout (Bottom) ..................................................................................... 2 Figure 3 – Board Dimensions ..................................................................................................... 3 Figure 4 – Gateway System Block Diagram ............................................................................... 4 Figure 5 – Micron SDRAM Block Diagram ................................................................................. 9 Figure 6 – SDRAM Pin Connections .......................................................................................... 9 Figure 7 – SDRAM Pin Configuration ........................................................................................10 Figure 8 – Flash Pin Connections .............................................................................................11 Figure 9 – Flash Pin Configuration ............................................................................................11 Figure 10 - Camera Module Pin Connections ............................................................................13 Figure 11 – Camera Module Pin Configuration..........................................................................14 Figure 12 – CAN Transceiver Pin Connections .........................................................................15 Figure 13 – CAN Transceiver Pin Configuration ........................................................................15 Figure 14 – USB Full Speed Pin Connections ...........................................................................16 Figure 15 – USB Full Speed Pin Configuration..........................................................................16 Figure 16 – USB High Speed Pin Connections .........................................................................17 Figure 17 - USB High Speed Pin Configuration .........................................................................18 Figure 18 – Audio Amplifier Pin Connections ............................................................................19 Figure 19 – Audio Amplifier Pin Configuration ...........................................................................19 Figure 20 – Microphone Pin Connections..................................................................................21 Figure 21 – Microphone Pin Configuration ................................................................................21 Figure 22 – JTAG Pin Configuration ..........................................................................................22 Figure 23 -JTAG/SWD/Trace Pin Connections ..........................................................................23 Figure 24 – Trace Pin Configuration ..........................................................................................23 Figure 25 – JTAG OR SWD Pin Configuration ..........................................................................24 Figure 26 - Ethernet Pin Configuration ......................................................................................26 Figure 27 – LCD Pin Connections .............................................................................................27 Figure 28 – LCD Pin Configuration ............................................................................................28 Figure 29 – LCD Touch Controller Pin Configuration.................................................................29 Figure 30 – Pmod, I/O Expander Interconnections Diagram......................................................32 Figure 31 – MicroSD Card Reader Pin Connections .................................................................49 Figure 32 – MicroSD Card Reader Pin Configuration ................................................................50 Figure 33 – WIFI Module Pin Connections ................................................................................50 Figure 34 – WIFI Module Pin Configuration ...............................................................................51 Figure 35 – BLE Module Pin Connections .................................................................................52 Figure 36 – BLE Module Pin Configuration ...............................................................................53 Figure 37 – NFC Reader Pin Connections ................................................................................54 Figure 38 – NFC Reader Pin Configuration ...............................................................................55 Figure 39 – LED Pin Connections .............................................................................................56 Figure 40 – LED Pin Configuration ............................................................................................56 Figure 41 – Trusted Object Pin Connections .............................................................................57


Rev. 1.02 Jun 26, 2017

Table of Tables Table 1 – I/O Expander (U18), I2C Address 0x25 .....................................................................30 Table 2 – I/O Expander (U19), I2C Address 0x27 .....................................................................31 Table 3 – Pmod Compatibility Chart ..........................................................................................32 Table 4 – Pmod1 I/O Expander Bits ..........................................................................................33 Table 5 – Pmod1 UART Type 4 and SPI Type 2 Pin Connections ............................................33 Table 6 – Pmod1 UART Type 4A and SPI Type 2A Pin Connections ........................................34 Table 7 – Pmod1 GPIO Type 1 Pin Connections (UART/SPI Mode) .........................................34 Table 8 – Pmod1 I2C Pin Connections .....................................................................................35 Table 9 – Pmod1 UART Type 3 Pin Connections ......................................................................35 Table 10 – Pmod1 GPIO Type 1 Pin Connections (I2C Mode) ..................................................35 Table 11 – Pmod2 I/O Expander Bits ........................................................................................36 Table 12 – Pmod2 UART Type 4 and SPI Type 2 Pin Connections ..........................................36 Table 13 – Pmod2 UART Type 4A and SPI Type 2A Pin Connections ......................................37 Table 14 – Pmod2 GPIO Type 1 Pin Connections (SPI/UART Mode) .......................................37 Table 15 – Pmod2 I2C Pin Connections....................................................................................38 Table 16 – Pmod2 UART Type 3 Pin Connections ....................................................................38 Table 17 – Pmod2 GPIO Type 1 Pin Connections (I2C Mode) ..................................................38 Table 18 – Pmod3 I/O Expander Bits ........................................................................................39 Table 19 – Pmod3 UART Type 4 and SPI Type 2 Pin Connections ..........................................39 Table 20 – Pmod3 UART Type 4A and SPI Type 2A Pin Connections ......................................40 Table 21 – Pmod3 GPIO Type 1 Pin Connections (UART/SPI Mode) .......................................40 Table 22 – Pmod3 I2C Pin Connections....................................................................................41 Table 23 – Pmod3 UART Type 3 Pin Connections ....................................................................41 Table 24 – Pmod3 GPIO Type 1 Pin Connections (I2C Mode) ..................................................41 Table 25 – Pmod4 I/O Expander Bits ........................................................................................42 Table 26 – Pmod4 UART Type 4 and SPI Type 2 Pin Connections ..........................................42 Table 27 – Pmod4 UART Type 4A and SPI Type 2A Pin Connections ......................................43 Table 28 – Pmod4 GPIO Type 1 Pin Connections (UART/SPI Mode) .......................................43 Table 29 – Pmod4 I2C Pin Connections....................................................................................44 Table 30 – Pmod4 UART Type 3 Pin Connections ....................................................................44 Table 31 – Pmod4 GPIO Type 1 Pin Connections (I2C Mode) ..................................................44 Table 32 – Pmod5 Shared SPI CS Pins ....................................................................................45 Table 33 – Pmod5 I/O Expander Bits ........................................................................................45 Table 34 – Pmod5 UART Type 4 and SPI Type 2 Pin Connections ..........................................45 Table 35 – Pmod5 UART Type 4A and SPI Type 2A Pin Connections ......................................46 Table 36 – Pmod5 GPIO Type 1 Pin Connections ....................................................................46 Table 37 – Pmod6 I/O Expander Bits ........................................................................................47 Table 38 – Pmod6 I2C Pin Connections....................................................................................47 Table 39 – Pmod6 UART Type 3 Pin Connections ....................................................................47 Table 40 – Pmod6 GPIO Type 1 Pin Connections ....................................................................48 Table 41 – Push Buttons’ I/O Expander Bits .............................................................................48


Rev. 1.02 Jun 26, 2017 Page 1

Chapter 1. Overview IoT gateways perform several critical functions such as device connectivity, protocol translation,

data filtering and processing, security, updating, management and more. Newer IoT gateways

also operate as platforms for application code that processes data and becomes an intelligent

part of a device-enabled system. Our Industrial IoT Gateway was developed to enable our

customers to learn and develop their connected solution.

Chapter 2. Preface

Purpose This user manual has been created to provide as a reference for the hardware features of the

Visible Things Industrial IoT Gateway. Much of the information provided is valuable when

programming the device or debugging issues normally associated with prototyping.

This user manual is written with the assumption that users have completed the Start

Here Guide for the Visible Things Industrial IoT Gateway.

Precautions Electrostatic discharge (ESD) is one of the leading causes of failure in integrated circuits. Take

reasonable precautions to prevent ESD by using grounding straps and mats while working on or

around the Avnet Renesas Synergy Gateway or other integrated circuits. Also, use anti-static

packaging when carrying prototypes from place to place, as this is likely when enough charge

will be generated to cause damage.


Rev. 1.02 Jun 26, 2017 Page 2

Chapter 3. Board Layout

Component Layout

Figure 1 – Component Layout (Top)

Figure 2 – Component Layout (Bottom)


Rev. 1.02 Jun 26, 2017 Page 3

Board Dimensions

Figure 3 – Board Dimensions


Rev. 1.02 Jun 26, 2017 Page 4

Chapter 4. Block Diagram

Figure 4 – Gateway System Block Diagram


Rev. 1.02 Jun 26, 2017 Page 5

Chapter 5. Input Power Sources The Visible Things Industrial IoT Gateway (hereinafter referred to as ‘Gateway’) can be powered

in a variety of ways, depending on your application’s current requirements. The three power

inputs described below can be used simultaneously and are stepped down to 3.3V using two

Monolithic Power Systems MP2188 synchronous step down switchers.

5V Direct (J5) The barrel jack on the Gateway provides an input for 5VDC at a maximum of

3.5A, 17.5W. This is the recommended way to power the Gateway. Load

testing has shown that a 5V, 2A power supply can provide sufficient current

for most applications. After inserting a power supply, the green Jack Power

LED will turn on. This power source can power every element of the

Industrial IoT Gateway.

Silicon Labs Si3402 Power Over Ethernet (PoE) PD Interface and Switching

Regulator The Si3402 is the industry’s most highly-integrated, IEEE 802.3at Type 1-

compliant, PoE PD interface and pulse-width-modulated (PWM) switching

regulator. By setting a new bar for device integration, lowest overall BOM

cost, efficiency and reliability, the Si3402 enables designers to easily add

PoE functionality to their Ethernet products. When included in the design of a

PoE-enabled system, such as a wireless access point or VoIP phone, the

Si3402 converts the high voltage (typically ±48 V) supplied over Ethernet

copper UTP cabling into a regulated, low-voltage dc supply. In addition, the

Si3402 combines all the required IEEE 802.3at Type 1 detection,

classification and hot swap interfaces with a complete, high efficiency, PWM

switching regulator.

For more technical information visit https://www.silabs.com/.

The PoE Ethernet jack provides 5V at up to 0.9A (4.5W) to power the 3.3V and 1.8V switching

power supplies of the gateway. This allows for reduced wiring in applications that already

require an Ethernet connection, although it must be noted that not all Ethernet networks can

provide Power over Ethernet. See your IT administrator to determine whether your network can

provide Power over Ethernet. Always verify your application’s current requirements when using

only PoE to power the Gateway. After connecting a powered Ethernet cable to this port, the

PoE Power LED will turn on.

USB Port (J3) The USB Mini Type-AB Port on J3 provides the capability to supply 5V,

0.5A (2.5W) max with a powered USB connection. This USB port is also

used in applications that require the Gateway to function as a USB device.

For more information about the USB device functionality, see the section

USB Device Full-Speed (J3) in this user’s manual. Always verify your

application’s power requirements when using only USB to power the

Gateway. After inserting a powered USB cable to this port, the USB Power

LED will turn on.

https://products.avnet.com/shop/SearchDisplay?searchTerm=MP2188&storeId=715839035&catalogId=10001&langId=-1&sType=SimpleSearch&resultCatEntryType=2&searchSource=Q&searchType=100

https://products.avnet.com/shop/SearchDisplay?searchTerm=SI3402B&storeId=715839035&catalogId=10001&langId=-1&sType=SimpleSearch&resultCatEntryType=2&searchSource=Q&searchType=100

https://www.silabs.com/


Rev. 1.02 Jun 26, 2017 Page 6

Chapter 6. Renesas Synergy S7G2 Microcontroller The microcontroller unit (MCU) on the Gateway is a 32-bit, 240 MHz, Cortex® M4 processor

with 4 MB of internal flash and 640 KB of SRAM. MCUs from the Synergy family include

qualified commercial-grade software to enable rapid development of applications which require

a real-time operating system. The Synergy Software Package (SSP) integrates the full suite of

Express Logic® software including the ThreadX RTOS and suite of X-Ware stacks. For more

information on Express Logic software, see www.rtos.com.

Chapter 7. Development Tools To develop applications for the Gateway, it is highly recommended to use one of the two

development environments provided with purchase of the Gateway. All the available

development software is available on the Renesas Synergy Gallery website and includes:

e2 studio

• The Renesas Synergy™ Platform's Eclipse-based e2 studio Integrated Solution

Development Environment (ISDE) is your workbench, providing you all the tools you

need to create differentiated applications for Synergy MCU devices.

• An open tool platform, the Eclipse CDT (C/C++ Development Tooling) standard allows

plug-ins for many innovative tool functions. Renesas engineers created solution-based

plug-ins for Synergy that guide the design process in three intuitive phases covering

Synergy MCUs and software – the Preparation Phase, the Build Phase, and the Debug

Phase.

IAR Embedded Workbench® for Synergy

• IAR Embedded Workbench, the world’s most widely used embedded development

environment, is now completely integrated with the Renesas Synergy™ Platform. The

new product IAR EW for Synergy provides add-on functionality to simplify and accelerate

software development, and provide the best performance and smallest code size.

Renesas created the Synergy Standalone Configurator (SSC) which is available to IAR

EW for Synergy users as a separate download. The SSC includes the Synergy Project

Generator as well as the Synergy Project Editor, including configurators like the Clock

Configurator, Pin Configurator, RTOS Configurator, and SSP Module

Selector/Configurator.

Synergy Software Package (SSP)

• Part of the Renesas Synergy™ Platform, the Synergy Software Package (SSP) features

software that has been integrated, optimized, tested, and qualified by Renesas for

Synergy users – and is also maintained and warranted by Renesas on an ongoing basis.

• The SSP includes the ThreadX® real-time operating system (RTOS), the X-Ware™ suite

of stacks and middleware (NetX™, NetX Duo™, USBX™, GUIX™, FileX®) plus other

quality stacks, libraries, and drivers all connected by a rich Application Framework for

ease of use. A common robust API resides over these components enabling you to

focus on your own product application code without delays

http://www.rtos.com/

http://synergygallery.renesas.com/

https://synergygallery.renesas.com/addon/detail/56


Rev. 1.02 Jun 26, 2017 Page 7

TraceX®

• TraceX® is Express Logic's host-based analysis tool that provides developers with a

graphical view of real-time system events and enables them to visualize and better

understand the behavior of their real-time systems. With TraceX, developers can see

clearly the occurrence of system events like interrupts and context switches that occur

out of view of standard debugging tools. The ability to identify and study these events,

and to pinpoint the timing of their occurrence in the context of the overall system’s

operation enables developers to resolve programming problems by finding unexpected

behavior and letting them investigate specific areas further.

GUIX Studio™

• GUIX Studio™ provides a complete WYSIWYG screen design environment which allows

the user to drag-and-drop graphical elements used to build the UI screens. GUIX Studio

automatically generates C code compatible with the GUIX™ library, ready to be

compiled and run on the target. Developers can produce pre-rendered fonts for use

within an application using the integrated GUIX Studio font generation tool. Fonts can be

generated in monochrome or anti-aliased formats, and are optimized to save space on

the target. Fonts can include any set of characters, including Unicode characters for

multi-lingual applications.

Renesas Verified Software Add-Ons

• A selection of specialty software components developed, licensed, and serviced by

Renesas VSA partner companies

• Tested and verified by Renesas to be compatible with the SSP per Renesas SSP

interoperability requirements

• Continuously tested for SSP interoperability with each new SSP maintenance release

• Free evaluation version available, full licensing required from the VSA partner company

for end-product production

Renesas Qualified Software Add-Ons

• A selection of specialty software components, licensed and serviced directly by Renesas

• Developed under the same quality standards and guidelines as the SSP

• Tightly integrated and optimized for use with SSP and API structure

• Free evaluation version available, full licensing required from Renesas for end-product

production


Rev. 1.02 Jun 26, 2017 Page 8

Chapter 8. Board Support Package (BSP) To allow users to begin application development quickly, add-on Board Support Packages

(BSP) have been developed to pre-configure the S7G2 MCU’s pins to support the various

peripherals on board the Gateway including the touch driver. This allows you to focus on

application development instead of spending hours tracing signals through schematics. To

install the BSP, download the *.pack files from the Avnet Visible Things website. Once you have

the file, ensure e2studio or IAR is closed and copy the file into the Packs directory of your

e2studio or SSC directory.

If you installed e2studio into its default directory, this folder will be located at

C:\Renesas\e2_studio\internal\projectgen\arm\Packs.

If you use IAR Embedded Workbench with SSC, and installed it into its default directory, it will

be located at C:\Renesas\Synergy\SSC\internal\projectgen\arm\Packs.

NOTE: If you use both IAR and e2studio, you must install the pack in BOTH locations.

Once the *.pack file has been placed into the directory, open e2studio or IAR and either

development environment’s New Synergy C Project wizard will be updated to include the

Gateway as a new board option to select.

Chapter 9. Memory

32 MB External SDRAM The 256Mb 16Mbx16 SDRAM is a high-speed CMOS, dynamic random-access memory in an

industry standard 54 ball VFBGA package. It is internally configured as a quad-bank DRAM with

a synchronous interface (all signals are registered on the positive edge of the clock signal,

CLK). Each of the x16’s 67,108,864-bit banks are organized as 8192 rows by 512 columns by

16 bits. The 256Mb SDRAM uses an internal pipelined architecture to achieve high-speed

operation. This architecture is compatible with the 2n rule of prefetch architectures, but it also

allows the column address to be changed on every clock cycle to achieve a highspeed, fully

random access. The 256Mb SDRAM is designed to operate in 3.3V memory systems. An auto

refresh mode is provided, along with a power-saving, power-down mode. All inputs and outputs

are LVTTL-compatible.

SDRAMs offer substantial advances in DRAM operating performance, including the ability to

synchronously burst data at a high data rate with automatic column-address generation, the

ability to interleave between internal banks to hide pre-charge time, and the capability to

randomly change column addresses on each clock cycle during a burst access.

Micron is a longtime leader in the SDRAM space, offering solutions from 64Mb to 256Mb, as

well as a full suite of simulation models and technical support. The MT48LC16M16A2B4-6A:G

is supported on a cost effective 50nm process technology, with assured lifecycle support for

years to come.

For more technical information visit http://www.micron.com/

This memory is accessed through the S7G2 microcontroller (MCU) External Memory Interface

peripheral which is pre-configured on projects created using the provided Board Support

Package (BSP).

https://products.avnet.com/shop/SearchDisplay?searchTerm=MT48LC16M16A2B4&storeId=715839035&catalogId=10001&langId=-1&sType=SimpleSearch&resultCatEntryType=2&showResultsPage=true&searchSource=Q&searchType=100&pageView=&beginIndex=0&pageSize=3&avnSearchType=all

http://www.micron.com/


Rev. 1.02 Jun 26, 2017 Page 9

Figure 5 – Micron SDRAM Block Diagram

Figure 6 – SDRAM Pin Connections


Rev. 1.02 Jun 26, 2017 Page 10

Figure 7 – SDRAM Pin Configuration


Rev. 1.02 Jun 26, 2017 Page 11

4 MB External Serial NOR Flash, MX25R3235 Macronix Serial Multi I/O (MXSMIO™) Flash provides not only Single I/O, but also Multi-I/O

interfaces. MX66xxx35 or MX25xxx33/35/39/73/75 series offering Dual I/O or Quad I/O

operations which double or quadruple the read performance of systems for high-end consumer

applications.

This memory is accessed through the S7G2 MCU’s dedicated SPI1 peripheral port.

Figure 8 – Flash Pin Connections

Figure 9 – Flash Pin Configuration


Rev. 1.02 Jun 26, 2017 Page 12

Chapter 10. Peripherals The Gateway has a large variety of peripherals available to use in a wide array of projects. A

Board Support Package (BSP) is provided with the purchase of the Gateway and is used to

greatly simplify configuration of the specific I/O needed for a given project. After installing the

BSP, creating a New Synergy C Project dialog inside of e2 studio or IAR Embedded

Workbench will allow for the selection of the Gateway. Creating a new project with this board

choice will create a default pin configuration that will be used to configure the S7G2 MCU

through the Synergy Configurator in e2 studio or the Synergy Standalone Configurator in IAR

Embedded Workbench. There are certain options that are not configured by default, but are

optional depending on your project requirements. Refer to the following sections to determine

configuration requirements specific to your project and I/O needs.

TD-Next TDM114 Camera/ON Semiconductor MT9M114 Image Sensor (J1)

TDM114 General Description: The TD-Next TDM114 camera module solution is a compact 8x8mm solderless digital camera

module which supports 720p HD imaging definition based on ON Semiconductor’s MT9M114

Image Sensor. The TDM114 module features a small size, low power consumption with internal

analog and digital features, this module is manufactured with quality control process and

individual inspection.

Optical Features:

• Pixel size: 1.9μm x 1.9μm

• 720p HD video at 30 frames/s

• Selectable output data format: YCbCr, 565RGB, 555RGB, 444RGB, processed Bayer,

BT656, RAW8- and RAW8+2-bit

• Rolling shutter, progressive scan

• 8/10 bits CMOS parallel Interface

• Lens

o Focal length (EFL): 1.84mm to 2.3mm

o F/NO: ~2.6

o Horizontal Field of view (HFOV) 55° to 90°

Electrical Features:

• Power supply

o Analog: 2.5 - 3.1V

o Interface: 1.7 - 1.95V or 2.5 - 3.1V

o Digital: 1.7 - 1.95V

• Typical power requirements

o Standby mode: 80μA

o Active mode: 60mA @ 720p, 30 frames/s

• Operating temperature: -10°C / 50°C

http://cammodules.td-next.com/720p-tdm114/


Rev. 1.02 Jun 26, 2017 Page 13

MT9M114 Image Sensor General Description: The ON Semiconductor MT9M114 is a 1/6-inch 1.26 MP High-Definition (HD) System-On-A-

Chip (SOC) Digital CMOS digital image sensor with an active-pixel array of 1296H x 976V. It

includes sophisticated camera functions such as auto exposure control, auto white balance,

black level control, flicker avoidance, and defect correction. It is designed for low light

performance. The MT9M114 produces extraordinarily clear, sharp digital pictures, making it the

perfect choice for a wide range of applications

The camera module with is connected via ribbon cable to J1. The camera uses the S7G2

MCU’s Parallel Data Capture peripheral to transfer image data over a 6-bit bus, and the shared

I2C bus on channel 3 is used for controlling the camera.

Figure 10 - Camera Module Pin Connections

https://products.avnet.com/shop/SearchDisplay?searchTerm=MT9M114&storeId=715839035&catalogId=10001&langId=-1&sType=SimpleSearch&resultCatEntryType=2&searchSource=Q&searchType=100


Rev. 1.02 Jun 26, 2017 Page 14

Figure 11 – Camera Module Pin Configuration

NXP TJA1042 CAN Transceiver (J2) The TJA1042 high-speed CAN transceiver provides an interface between a Controller Area

Network (CAN) protocol controller and the physical two-wire CAN bus. The transceiver is

designed for high-speed CAN applications in the automotive industry, providing the differential

transmit and receive capability to (a microcontroller with) a CAN protocol controller.

The TJA1042 belongs to the third generation of high-speed CAN transceivers from NXP

Semiconductors, offering significant improvements over first- and second-generation devices

such as the TJA1040. It offers improved Electromagnetic Compatibility (EMC) and Electrostatic

Discharge (ESD) performance, and features:

• Ideal passive behavior to the CAN bus when the supply voltage is off

• A very low-current Standby mode with bus wake-up capability

• TJA1042T/3 and TJA1042TK/3 can be interfaced directly to microcontrollers with supply

voltages from 3 V to 5 V

The TJA1042 implements the CAN physical layer as defined in the current ISO11898 standard

(ISO11898-2:2003, ISO11898-5:2007) and the pending updated version of ISO 11898-2:2016.

Pending the release of the updated version of ISO11898-2:2016 including CAN FD and SAE

J2284-4/5, additional timing parameters defining loop delay symmetry are specified. This

implementation enables reliable communication in the CAN FD fast phase at data rates up to 5

Mbit/s.

These features make the TJA1042 an excellent choice for all types of HS-CAN networks, in

nodes that require a low-power mode with wake-up capability via the CAN bus.

https://products.avnet.com/shop/SearchDisplay?searchTerm=TJA1042&storeId=715839035&catalogId=10001&langId=-1&sType=SimpleSearch&resultCatEntryType=2&searchSource=Q&searchType=100


Rev. 1.02 Jun 26, 2017 Page 15

A Controlled Area Network (CAN) bus is a vehicle bus standard

designed to allow microcontrollers to communicate with each other

in applications without a host computer. It is a message-based

protocol, designed originally for multiplex electrical wiring within

automobiles, but is also used in many other contexts.

The Gateway provides a two-wire serial CAN interface for

communicating with other devices.

Figure 12 – CAN Transceiver Pin Connections

Figure 13 – CAN Transceiver Pin Configuration


Rev. 1.02 Jun 26, 2017 Page 16

USB Device Full-Speed (J3) The Gateway can be connected as a USB device via the Full-

Speed Micro USB Type AB connector J3. For more detailed

information about using the USBX framework, refer to the

Synergy X-Ware component documentation on the Synergy

Gallery

Figure 14 – USB Full Speed Pin Connections

Figure 15 – USB Full Speed Pin Configuration


Rev. 1.02 Jun 26, 2017 Page 17

USB Host High-Speed (J4) The on-board USB high speed connector, a standard Type-A USB

port, allows the Gateway to be configured as a USB host. For more

detailed information about using the USBX framework, please refer

to the Synergy X-Ware component documentation on the Renesas

Synergy Gallery.

Figure 16 – USB High Speed Pin Connections


Rev. 1.02 Jun 26, 2017 Page 18

Figure 17 - USB High Speed Pin Configuration


Rev. 1.02 Jun 26, 2017 Page 19

Audio Amplifier (J8) The Gateway has an unpopulated pair of connections that can be used to

connect an external speaker. The Gateway does not come with a speaker

pre-installed. The speaker volume can be controlled using a PWM signal

generated by channel 2 of the General-Purpose Timer 2 (GPT2),

controlled through software by adjusting the timer channel’s pulse width

property.

Figure 18 – Audio Amplifier Pin Connections

Figure 19 – Audio Amplifier Pin Configuration


Rev. 1.02 Jun 26, 2017 Page 20

STMicro MP23AB02B Microphone with MAXIM Integrated MAX9814

Amplifier (MIC1) The ST Microelectronics MP23AB02B MEMS microphone is a compact, low-power microphone

built with a low-profile sensing element. The sensing element, capable of detecting acoustic

waves, is manufactured using a specialized silicon micromachining process to produce audio

sensors. The MP23AB02B has an acoustic overload point of 124 dBSPL with a 64dB signal-to-

noise ratio. The MP23AB02B is available in a package compliant with reflow soldering and is

guaranteed to operate over an extended temperature range from -40 °C to +85 °C.

Features

• Single supply voltage operation

• Low power consumption

• Omnidirectional sensitivity

• High signal-to-noise ratio

• High bandwidth

• Package compliant with reflow soldering

For more technical information visit https://www.ST.com/.

The MAX9814 is a low-cost, high-quality microphone amplifier with automatic gain control

(AGC) and low-noise microphone bias. The device features a low-noise preamplifier, variable

gain amplifier (VGA), output amplifier, microphone-bias-voltage generator and AGC control

circuitry.

The low-noise preamplifier has a fixed 12dB gain, while the VGA gain automatically adjusts from

20dB to 0dB, depending on the output voltage and the AGC threshold. The output amplifier

offers selectable gains of 8dB, 18dB, and 28dB. With no compression, the cascade of the

amplifiers results in an overall gain of 40dB, 50dB, or 60dB. A tri-level digital input programs the

output amplifier gain. An external resistive divider controls the AGC threshold and a single

capacitor programs the attack/release times. A tri-level digital input programs the ratio of attack-

to-release time. The hold time of the AGC is fixed at 30ms. The low-noise microphone-bias-

voltage generator can bias most electret microphones.

The MAX9814 is available in the space-saving, 14-pin TDFN package. This device is specified

over the -40°C to +85°C extended temperature range.

For more technical information visit https://www.maxim-ic.com/

The microphone is connected to the S7G2 MCU through an amplifier

with automatic gain control and other features.

https://products.avnet.com/shop/SearchDisplay?searchTerm=MP23AB02B&storeId=715839035&catalogId=10001&langId=-1&sType=SimpleSearch&resultCatEntryType=2&searchSource=Q&searchType=100

https://www.st.com/

https://www.maxim-ic.com/


Rev. 1.02 Jun 26, 2017 Page 21

Figure 20 – Microphone Pin Connections

Figure 21 – Microphone Pin Configuration


Rev. 1.02 Jun 26, 2017 Page 22

Debugging Options (J9, P2)

USB J-Link On-Board (J9) The Gateway comes with SEGGER© J-Link On-Board

using a ST Micro STM32F072C8U6 to remove the need

for special debugging cables. Connecting to the Gateway

is as simple as connecting a host PC to the J-Link OB

Debug USB connector with a USB Type-A to Micro-AB

cable. This connection can also serve as a virtual COM

port which allows for sending serial data such as debug

text over the same cable.

The pins used for J-Link On-Board are pre-configured when creating a new Synergy C Project

within e2 studio or IAR Embedded Workbench.

Figure 22 – JTAG Pin Configuration

JTAG/SWD/Trace (P2) Advanced debugging features can be accessed by users who have a trace port

analyzer. This connection also provides access to the same JTAG pins as

through the J-Link OB connector. To perform Single Wire Debug (SWD)

functionality, the pin configuration must change as the JTAG and SWD

functions share pins on the S7G2.

https://products.avnet.com/shop/SearchDisplay?searchTerm=STM32F072C8U6&storeId=715839035&catalogId=10001&langId=-1&sType=SimpleSearch&resultCatEntryType=2&searchSource=Q&searchType=100


Rev. 1.02 Jun 26, 2017 Page 23

Figure 23 -JTAG/SWD/Trace Pin Connections

Figure 24 – Trace Pin Configuration


Rev. 1.02 Jun 26, 2017 Page 24

Figure 25 – JTAG OR SWD Pin Configuration

NOTE: JTAG Operation Mode must be Disabled before Enabling SWD


Rev. 1.02 Jun 26, 2017 Page 25

Ethernet Ports (P1, P3) The Gateway comes with two Ethernet

10/100 ports. The port shown on the right

in the image below also provides Power

over Ethernet (POE) functionality, allowing

the device to be powered by an

appropriately equipped Ethernet

connection. The Gateway also includes an

Ethernet switch.

Microchip LAN9353 Ethernet Switch Microchip's LAN9353 is a high-performance, small-footprint, full-featured 3-port managed

Ethernet switch. This device is application-optimized for consumer, embedded and Industrial

electronic designs which require a highly integrated, cost effective device with switching

functionality, flexibility and ease of integration. The LAN9353/9353i supports compact PCB

design and MII/RMII/Turbo MII (Media Independent, Reduced Media Independent and Turbo

Media Independent Interfaces). This device supports Turbo MII mode to accomplish network

speeds up to 200 Mbps. The LAN9353 can also be configured to support Dual RMII operation.

The virtual PHY feature mimics a single PHY connection through the MII/RMII/Turbo MII

interface to the host SoC, which reduces software development time. This feature also allows

system designers to swap the single PHY and Ethernet switch to create multiple SKUs from the

same software driver.

The LAN9353 combines all the functions of a 10/100 switch system, including the Switch Fabric,

packet buffers, Buffer Manager, Media Access Controllers (MACs), PHY transceivers, and serial

management. IEEE 1588v2 is supported via the integrated IEEE 1588v2 hardware time stamp

unit, which supports end-to-end and peer-to-peer transparent clocks. The LAN9353 complies

with the IEEE 802.3 (full/half-duplex 10BASE-T and 100BASE-TX) Ethernet protocol, IEEE

802.3az Energy Efficient Ethernet (EEE) (100Mbpsonly), and 802.1D/802.1Q network

management protocol specifications, enabling compatibility with industry standard Ethernet and

Fast Ethernet applications. 100BASE-FX is supported via an external fiber transceiver.

This device complies with IEEE 802.3 10BASE-T and 100BASE-TX Ethernet protocol

specifications, enabling compatibility with industry standard Ethernet and Fast Ethernet

applications.

For more technical information visit https://www.Microchip.com/

For more detailed information about using the NetX framework, please refer to the Synergy X-

Ware component documentation on the Renesas Synergy Gallery.

https://products.avnet.com/shop/SearchDisplay?searchTerm=LAN9353&storeId=715839035&catalogId=10001&langId=-1&sType=SimpleSearch&resultCatEntryType=2&searchSource=Q&searchType=100

https://www.microchip.com/


Rev. 1.02 Jun 26, 2017 Page 26

Figure 26 - Ethernet Pin Configuration


Rev. 1.02 Jun 26, 2017 Page 27

LCD (CN1) The Gateway comes with a 4-wire

resistive touch, 4.3” 480x272 WQVGA

TFT touch display connected to the

Gateway’s LCD connector. The display

uses a 9 LED backlight that can vary

its brightness using a pulse-width

modulated signal (PWM). All the pins

are pre-configured in projects created

with the provided BSP.

Figure 27 – LCD Pin Connections


Rev. 1.02 Jun 26, 2017 Page 28

Figure 28 – LCD Pin Configuration


Rev. 1.02 Jun 26, 2017 Page 29

SemTech SX8650 LCD Touch Controller The Gateway comes with a SemTech SX8650 touch controller to handle touch input and

convert touches into coordinates.

Figure 29 – LCD Touch Controller Pin Configuration


Rev. 1.02 Jun 26, 2017 Page 30

I/O Expansion The Gateway comes with two I/O expanders to increase MCU I/O. The additional I/O provided

by these expanders are not capable of high frequency switching, so they are routed to support

other systems. These expanders are controlled through the Synergy S7G2 MCU’s I2C port 3

and are capable of generating interrupts when configured properly. Examples for how to control

the I/O expanders can be found in the section Error! Reference source not found. at the end o

f this user manual. Reference the schematic and tables below to determine how to control the

expanders for your application.

I/O Expander (U18, I2C address 0x25) This expander is used to control and interface with Pmod connectors 1 through 4. Port 0 is used

for controlling the Pmod connector’s mode and reset. Bits 0 through 3 control the Pmod

connector’s reset line while bits 4 through 7 control whether each Pmod connector is using the

UART/SPI mode or the I2C mode. (The pinouts are different depending on the communication

mode, this hardware makes it easy to change the way the Pmod connector’s pins are routed to

the MCU). Port 1 is used for reading/writing to the additional IO available on Pmod connectors 1

through 4. Pmod connectors 5 and 6 do not interface with this I/O expander.

Port Bit Pmod Function Direction

Port 0 Bit 0 Pmod 4 RESET Input/Output

Bit 1 Pmod 3 RESET Input/Output



Bit 4 Pmod 4 COMMS Mode Output




Port 1 Bit 0 Pmod 4 IO7 Input/Output

Bit 1 Pmod 4 IO8 Input/Output






Bit 7 Pmod 1 IO8 Input/Output Table 1 – I/O Expander (U18), I2C Address 0x25


Rev. 1.02 Jun 26, 2017 Page 31

I/O Expander (U19, I2C address 0x27) This expander is used to control power to all 6 Pmod connectors and interface with the four

push buttons S1 through S4. Port 0 exclusively controls the Pmod power, except for bit 0 and bit

7, which are not connected. Port 1, bits 2-5 are connected to the push buttons. The push

buttons are active high, therefore pressing them provides a HIGH signal (1) to the

corresponding pins. Port 1, bit 6 must be set to LOW (0) to enable I2C communication to the

Trusted Objects ® Secure Element. For more information about the Secure Element, see the

section Hardware Partner Information. For port 1, bits 0, 1, and 7 are not connected.

Port Bit Component Function Direction

Port 0 Bit 0

Bit 1 Pmod 1 Power Output






Bit 7

Port 1 Bit 0

Bit 1

Bit 2 Button 1 I/O Input




Bit 6 Secure Element Enable Output

Bit 7 Table 2 – I/O Expander (U19), I2C Address 0x27

Pmod Compatible Expansion Connectors Pmod expansion connectors can be used with the large array of sensors and add-on modules

available from many different suppliers. Digilent provides a large assortment of Pmod

Compatible devices at http://store.digilentinc.com/pmod-modules/. Some modules communicate

via the I2C protocol, while others use UART or SPI. For details about the different Pmod

specifications, see the Pmod specification manual. More information about the Pmod Standard

can also be found here.

The following table shows which Pmod specifications are supported by each PMOD on the

Gateway. The Pmod ports on the Gateway are configured through software using the I/O

Expanders which are described in the section I/O Expansion above.

Details for how to configure each specific Pmod connector is described in the various sections

to follow.

http://store.digilentinc.com/pmod-modules/

https://www.digilentinc.com/Pmods/Digilent-Pmod_%20Interface_Specification.pdf

https://reference.digilentinc.com/reference/pmod/specification


Rev. 1.02 Jun 26, 2017 Page 32

I2C Type 1 Type 2 Type 2A Type 3 Type 4 Type 4A Type 5 Type 6

Gateway PMOD

I2C GPIO SPI Expanded SPI

UART UART Expanded UART

H-Bridge

Dual H-Bridge

1 Y Y Y Y Y Y Y N N

2 Y Y Y Y Y Y Y N N

3 Y Y Y Y Y Y Y N N

4 Y Y Y Y Y Y Y N N

5 N Y Y Y N Y Y Y Y

6 Y Y N N N N N N N

Table 3 – Pmod Compatibility Chart

Figure 30 – Pmod, I/O Expander Interconnections Diagram


Rev. 1.02 Jun 26, 2017 Page 33

Pmod1 (CN4) Pmod1 can be configured for most Pmod interfaces. To enable power to Pmod1, the POWER

pin from the I/O Expander U19 Port 0 bit 1 must be set HIGH (1). Depending on the type of

Pmod being used, set the I/O Expander COMMS Mode bit as shown below:

UART Types 4, 4A and SPI Types 2, 2A

To configure Pmod1 for these types of Pmods, the COMMS Mode pin from the I/O Expander

U18 Port 0 bit 7 must be set LOW (0).

I2C and UART Type 3


U18 Port 0 bit 7 must be set HIGH (1).

GPIO Type 1

GPIO Type 1 Pmods can be used regardless of the COMMS Mode bit.

Always verify any Pmod’s pinout before inserting it as damage may occur if they are

inserted upside down.

I/O Expander Configuration

Function I2C Address Port Bit

POWER 0x27 0 1

RESET 0x25 0 3

COMMS Mode 0x25 0 7

IO7 0x25 1 6

IO8 0x25 1 7 Table 4 – Pmod1 I/O Expander Bits

UART/SPI Comms Mode

UART Type 4 and SPI Type 2 Pmods

UART Type 4 Pmods and SPI Type 2 Pmods only have 6 pins instead of the 12 provided by the

Gateway’s connector. Insert these Pmods into the upper row of the connector (connector pins 1

through 6).

Pmod S7G2

Pin Pin Function by Type

Port Pin Pin Function

UART (4, 4A) SPI (2, 2A) UART SPI

1 RTS CS PA05 CTS CTS_RTS_SS

2 RX MISO PA02 TXD_MOSI TXD_MOSI

3 TX MOSI PA03 RXD_MISO RXD_MISO

4 CTS SCK PA04 RTS SCK

5 GND GND GND GND GND

6 VCC (3.3V) VCC (3.3V) VCC (3.3V) VCC (3.3V) VCC (3.3V) Table 5 – Pmod1 UART Type 4 and SPI Type 2 Pin Connections


Rev. 1.02 Jun 26, 2017 Page 34

UART Type 4A and SPI Type 2A Pmods

UART Type 4A Pmods and SPI Type 2A Pmods use all 12 pins and should be inserted only one

way.

Pmod S7G2




1 RTS CS PA05 CTS CTS_RTS_SS

2 RX MISO PA02 TXD_MOSI TXD_MOSI

3 TX MOSI PA03 RXD_MISO RXD_MISO

4 CTS SCK PA04 RTS SCK


6 VCC (3.3V) VCC (3.3V) VCC (3.3V) VCC (3.3V) VCC (3.3V)

7 INT INT P400 IRQ0 IRQ0

8 RESET RESET I/O Expander N/A N/A

9 GPIO GPIO I/O Expander N/A N/A



12 VCC (3.3V) VCC (3.3V) VCC (3.3V) VCC (3.3V) VCC (3.3V) Table 6 – Pmod1 UART Type 4A and SPI Type 2A Pin Connections

GPIO Type 1 Pmods

If clearance is not an issue, two GPIO Type 1 standard Pmods can be used together when the

connector is configured in UART/SPI Comms Mode. Do not turn a second Type 1 Pmod

upside down to get it to fit! Damage may occur as a result of inserting a Pmod upside

down!

Pmod S7G2

Pin Pin Function Port Pin Pin Function

Up

pe

r R

ow

1 GPIO PA05 GPIO

2 GPIO PA02 GPIO

3 GPIO PA03 GPIO

4 GPIO PA04 GPIO

5 GND GND GND

6 VCC (3.3V) VCC (3.3V) VCC (3.3V)

Low

er

Ro

w 1 GPIO P400 GPIO

2 GPIO I/O Expander GPIO



5 GND GND GND

6 VCC (3.3V) VCC (3.3V) VCC (3.3V) Table 7 – Pmod1 GPIO Type 1 Pin Connections (UART/SPI Mode)


Rev. 1.02 Jun 26, 2017 Page 35

I2C Comms Mode

The I2C Comms Mode can be used for both I2C standard and UART Type 3 standard Pmods.

I2C Pmods

I2C Pmods only have 8 pins instead of the 12 provided by the Gateway’s

connector. Insert these Pmods into the left-most side of the connector.

Pmod S7G2


1 SCL PA02 SDA

2 SCL PA02 SDA

3 SDA PA03 SCL

4 SDA PA03 SCL

5 GND GND GND

6 GND GND GND

7 VCC (3.3V) VCC (3.3V) VCC (3.3V)

8 VCC (3.3V) VCC (3.3V) VCC (3.3V) Table 8 – Pmod1 I2C Pin Connections

UART Type 3 Pmods

UART Type 3 Pmods only have 6 pins instead of the 12 provided by the Gateway’s connector.

Insert these Pmods into the either the upper or lower row of the connector as the upper and

lower row signals are connected to the same S7G2 MCU pins when the Pmod connector is

configured in I2C Comms Mode.

Pmod S7G2

Pmod Pin Pmod Pin Function S7G2 Pin S7G2 Pin Function

1 RTS PA05 CTS

2 CTS PA04 RTS

3 TX PA03 RXD_MISO

4 RX PA02 TXD_MISO

5 GND GND GND

6 VCC (3.3V) VCC (3.3V) VCC (3.3V) Table 9 – Pmod1 UART Type 3 Pin Connections

GPIO Type 1 Standard Pmods

GPIO Type 1 Pmod can be used when the connector is configured in UART/SPI Comms Mode.

These types of Pmods can be inserted in either row of the connector.

Pmod S7G2


1 GPIO PA05 GPIO

2 GPIO PA04 GPIO

3 GPIO PA03 GPIO

4 GPIO PA02 GPIO

5 GND GND GND

6 VCC (3.3V) VCC (3.3V) VCC (3.3V) Table 10 – Pmod1 GPIO Type 1 Pin Connections (I2C Mode)


Rev. 1.02 Jun 26, 2017 Page 36







I2C and UART Type 3



GPIO Type 1






POWER 0x27 0 2

RESET 0x25 0 2

COMMS Mode 0x25 0 6

IO7 0x25 1 4


UART/SPI Comms Mode




through 6).

Pmod S7G2




1 RTS CS PB02 CTS CTS_RTS_SS

2 RX MISO PB04 TXD_MOSI TXD_MOSI

3 TX MOSI PB05 RXD_MISO RXD_MISO

4 CTS SCK PB03 RTS SCK




Rev. 1.02 Jun 26, 2017 Page 37



way.

Pmod S7G2




1 RTS CS PB02 CTS CTS_RTS_SS

2 RX MISO PB04 TXD_MOSI TXD_MOSI

3 TX MOSI PB05 RXD_MISO RXD_MISO

4 CTS SCK PB03 RTS SCK









GPIO Type 1 Pmods




down!

Pmod S7G2


Up

pe

r R

ow

1 GPIO PB02 GPIO

2 GPIO PB04 GPIO

3 GPIO PB05 GPIO

4 GPIO PB03 GPIO

5 GND GND GND

6 VCC (3.3V) VCC (3.3V) VCC (3.3V)

Low

er

Ro

w 1 GPIO P001 GPIO




5 GND GND GND

6 VCC (3.3V) VCC (3.3V) VCC (3.3V) Table 14 – Pmod2 GPIO Type 1 Pin Connections (SPI/UART Mode)


Rev. 1.02 Jun 26, 2017 Page 38

I2C Comms Mode


I2C Pmods



Pmod S7G2


1 SCL PB04 SDA

2 SCL PB04 SDA

3 SDA PB05 SCL

4 SDA PB05 SCL

5 GND GND GND

6 GND GND GND

7 VCC (3.3V) VCC (3.3V) VCC (3.3V)


UART Type 3 Pmods





Pmod S7G2


1 RTS PB02 CTS

2 CTS PB03 RTS

3 TX PB05 RXD_MISO

4 RX PB04 TXD_MISO

5 GND GND GND





Pmod S7G2


1 GPIO PB02 GPIO

2 GPIO PB03 GPIO

3 GPIO PB05 GPIO

4 GPIO PB04 GPIO

5 GND GND GND



Rev. 1.02 Jun 26, 2017 Page 39







I2C and UART Type 3



GPIO Type 1






POWER 0x27 0 3

RESET 0x25 0 1

COMMS Mode 0x25 0 5

IO7 0x25 1 2


UART/SPI Comms Mode




through 6).

Pmod S7G2




1 RTS CS P711 CTS CTS_RTS_SS

2 RX MISO P709 TXD_MOSI TXD_MOSI

3 TX MOSI P708 RXD_MISO RXD_MISO

4 CTS SCK P710 RTS SCK




Rev. 1.02 Jun 26, 2017 Page 40



way.

Pmod S7G2
















GPIO Type 1 Pmods




down!

Pmod S7G2


Up

pe

r R

ow

1 GPIO P711 GPIO

2 GPIO P709 GPIO

3 GPIO P708 GPIO

4 GPIO P710 GPIO

5 GND GND GND

6 VCC (3.3V) VCC (3.3V) VCC (3.3V)

Low

er

Ro

w 1 GPIO P002 GPIO




5 GND GND GND



Rev. 1.02 Jun 26, 2017 Page 41

I2C Comms Mode


I2C Pmods



Pmod S7G2


1 SCL P709 SDA

2 SCL P709 SDA

3 SDA P708 SCL

4 SDA P708 SCL

5 GND GND GND

6 GND GND GND

7 VCC (3.3V) VCC (3.3V) VCC (3.3V)


UART Type 3 Pmods





Pmod S7G2


1 RTS P711 CTS

2 CTS P710 RTS

3 TX P708 RXD_MISO

4 RX P709 TXD_MISO

5 GND GND GND





Pmod S7G2


1 GPIO P711 GPIO

2 GPIO P710 GPIO

3 GPIO P708 GPIO

4 GPIO P709 GPIO

5 GND GND GND



Rev. 1.02 Jun 26, 2017 Page 42




NOTE: To use Pmod4 without interference from Bluetooth, make sure the Bluetooth is

disabled by setting P914 low.




I2C and UART Type 3



GPIO Type 1






POWER 0x27 0 4

RESET 0x25 0 0

COMMS Mode 0x25 0 4

IO7 0x25 1 0


UART/SPI Comms Mode




through 6).

Pmod S7G2











Rev. 1.02 Jun 26, 2017 Page 43



way.

Pmod S7G2
















GPIO Type 1 Pmods




down!

Pmod S7G2


Up

pe

r R

ow

1 GPIO P514 GPIO

2 GPIO P509 GPIO

3 GPIO P510 GPIO

4 GPIO P508 GPIO

5 GND GND GND

6 VCC (3.3V) VCC (3.3V) VCC (3.3V)

Low

er

Ro

w 1 GPIO P004 GPIO




5 GND GND GND



Rev. 1.02 Jun 26, 2017 Page 44

I2C Comms Mode


I2C Pmods



Pmod S7G2


1 SCL P509 SDA

2 SCL P509 SDA

3 SDA P510 SCL

4 SDA P510 SCL

5 GND GND GND

6 GND GND GND

7 VCC (3.3V) VCC (3.3V) VCC (3.3V)


UART Type 3 Pmods





Pmod S7G2


1 RTS P514 CTS

2 CTS P508 RTS

3 TX P510 RXD_MISO

4 RX P509 TXD_MISO

5 GND GND GND





Pmod S7G2


1 GPIO P514 GPIO

2 GPIO P508 GPIO

3 GPIO P510 GPIO

4 GPIO P509 GPIO

5 GND GND GND



Rev. 1.02 Jun 26, 2017 Page 45

Pmod5 (CN6) Pmod5 can be configured for a few different Pmod interfaces. To enable power to Pmod5, the

POWER pin from the I/O Expander U19 Port 0 bit 5 must be set HIGH (1).

Also, Pmod5 shares its communication pins with the WIFI and the NFC. When writing software

to communicate with a device on Pmod5, the corresponding CS pins for the WIFI and NFC must

be set HIGH (1), while the CS for the Pmod must be set LOW (0).

Shared SPI - CS Pins

Function CS Pin Number

Pmod5 SPI CS P515

WIFI SPI CS P207

NFC SPI CS PA07 Table 32 – Pmod5 Shared SPI CS Pins





POWER 0x27 0 1 Table 33 – Pmod5 I/O Expander Bits




through 6).

Pmod S7G2











Rev. 1.02 Jun 26, 2017 Page 46



way.

Pmod S7G2











8 RESET RESET P805 GPIO GPIO

9 GPIO GPIO P909 GPIO GPIO

10 GPIO GPIO P513 GPIO GPIO



GPIO Type 1 Pmods

If clearance is not an issue, two GPIO Type 1 standard Pmods can be used together. Do not

turn a second Type 1 Pmod upside down to get it to fit! Damage may occur as a result of

inserting a Pmod upside down!

Pmod S7G2


Up

pe

r R

ow

1 GPIO P515 GPIO

2 GPIO P203 GPIO

3 GPIO P202 GPIO

4 GPIO P204 GPIO

5 GND GND GND

6 VCC (3.3V) VCC (3.3V) VCC (3.3V)

Low

er

Ro

w 1 GPIO P006 GPIO

2 GPIO P805 GPIO

3 GPIO P909 GPIO

4 GPIO P513 GPIO

5 GND GND GND

6 VCC (3.3V) VCC (3.3V) VCC (3.3V) Table 36 – Pmod5 GPIO Type 1 Pin Connections


Rev. 1.02 Jun 26, 2017 Page 47

Pmod6 (CN7) Pmod6 can be configured for a couple Pmod interfaces. To enable power to Pmod6, the

POWER pin from the I/O Expander U19 Port 0 bit 6 must be set HIGH (1).





POWER 0x27 0 6 Table 37 – Pmod6 I/O Expander Bits

I2C Pmods



Pmod S7G2


1 SCL P206 SDA

2 SCL P206 SDA

3 SDA P205 SCL

4 SDA P205 SCL

5 GND GND GND

6 GND GND GND

7 VCC (3.3V) VCC (3.3V) VCC (3.3V)


UART Type 3 Pmods



lower row signals are connected to the same S7G2 MCU pins.

Pmod S7G2


1 RTS P809 CTS

2 CTS P810 RTS

3 TX P205 RXD_MISO

4 RX P206 TXD_MISO

5 GND GND GND



Rev. 1.02 Jun 26, 2017 Page 48




Pmod S7G2


1 GPIO P809 GPIO

2 GPIO P810 GPIO

3 GPIO P205 GPIO

4 GPIO P206 GPIO

5 GND GND GND

6 VCC (3.3V) VCC (3.3V) VCC (3.3V) Table 40 – Pmod6 GPIO Type 1 Pin Connections

Push Buttons (S1-S4)

Button states can be accessed through the I/O expander U19.

For details, see the section “I/O Expansion” above.



S1 0x27 1 2

S2 0x27 1 3

S3 0x27 1 4

S4 0x27 1 5 Table 41 – Push Buttons’ I/O Expander Bits


Rev. 1.02 Jun 26, 2017 Page 49

Molex MicroSD Card Slot (J7) The Molex MicroSD Card Reader Connector (1040310811) is connected

to a Secure Digital Input Output (SDIO) switch that allows the same set

of pins to be used to communicate with either the SD card or the WIFI

Module. This is controlled by the MCU_SDIO_uSD_WL line. When this

signal is HIGH (1), the switch will read/write to the WIFI module. When

LOW (0), it reads from the SD card. Note: for the MicroSD card

communication to work properly, the WIFI’s SPI pins 202, 203, and

204 must be disabled.

Figure 31 – MicroSD Card Reader Pin Connections

https://products.avnet.com/shop/SearchDisplay?searchTerm=1040310811&storeId=715839035&catalogId=10001&langId=-1&sType=SimpleSearch&resultCatEntryType=2&searchSource=Q&searchType=100


Rev. 1.02 Jun 26, 2017 Page 50

Figure 32 – MicroSD Card Reader Pin Configuration

Laird WIFI/Bluetooth Low Energy (BLE) The Gateway comes with a dual-purpose Laird/LS Research

Sterling-LWB Module 450-0152R which uses a BCM4343W

wireless module capable of both WIFI and BLE.

WIFI Module The WIFI portion of the WIFI/BLE module is connected to a SDIO

switch that allows the same set of pins to be used to communicate

with either the SD card or the WIFI Module. This is controlled by

the MCU_SDIO_uSD_WL line. When this signal is high, the switch

will read/write to the WIFI module. When low, it reads from the SD

card.

Figure 33 – WIFI Module Pin Connections

https://products.avnet.com/shop/SearchDisplay?searchTerm=450-0152R&storeId=715839035&catalogId=10001&langId=-1&sType=SimpleSearch&resultCatEntryType=2&searchSource=Q&searchType=100

https://products.avnet.com/shop/SearchDisplay?searchTerm=450-0152R&storeId=715839035&catalogId=10001&langId=-1&sType=SimpleSearch&resultCatEntryType=2&searchSource=Q&searchType=100


Rev. 1.02 Jun 26, 2017 Page 51

Figure 34 – WIFI Module Pin Configuration

BLE Module The BLE portion of the module is connected via UART. Synergy configuration and software

provides an unusual but flexible way to handle CTS/RTS signals for asynchronous UART

communications. Instead of setting the CTS and RTS pins individually in the UART Peripheral

section of the Synergy Configurator, a single pin is selected for CTS/RTS. Once the UART

driver module is added to the Threads tab of the Synergy Configurator, then the properties must

be adjusted to select whether a RTS signal is needed. If it is, then the GPIO for the RTS line is

selected within the software that initializes the UART driver.


Rev. 1.02 Jun 26, 2017 Page 52

Figure 35 – BLE Module Pin Connections


Rev. 1.02 Jun 26, 2017 Page 53

Figure 36 – BLE Module Pin Configuration


Rev. 1.02 Jun 26, 2017 Page 54

NFC Reader The Near Field Communication (NFC) reader uses a NXP PN5180

and communicates via SPI with the S7G2 MCU. This NFC

reader/writer supports all NFC tag types (type 1, type 2, type 3, type

4A, and type 4B) and supports the following RF operating modes:

• ISO/IEC 14443-A up to 848 Kbit/s, MIFARE

• ISO/IEC 14443-B up to 848 Kbit/s

• JIS X 6319-4 (comparable with FeliCa scheme)

• ISO/IEC 15693

• ISO/IEC 18000-3 Mode 3

• ISO/IEC 18092 (NFC-IP1)

• ISO/IEC 21481 (NFC-IP-2)

• ISO/IEC 14443-type A Card emulation up to 848 Kbit/s

Figure 37 – NFC Reader Pin Connections

https://products.avnet.com/shop/SearchDisplay?searchTerm=PN5180&storeId=715839035&catalogId=10001&langId=-1&sType=SimpleSearch&resultCatEntryType=2&searchSource=Q&searchType=100


Rev. 1.02 Jun 26, 2017 Page 55

Figure 38 – NFC Reader Pin Configuration

LEDs (LED1-LED4) The four on-board LEDs can be used in a variety of applications.

The LEDs are defined in the provided Board Support Package

(BSP) and are contained in an array.

Pin Name Pin Number

Mode Pull Up

Drive Capacity

Output Type

IRQ Pin Function

LED1 (Green) PB06 Output Low CMOS GPIO

LED2 (Blue) PB07 Output Low CMOS GPIO

LED3 (Orange) P313 Output Low CMOS GPIO

LED4 (Red) P314 Output Low CMOS GPIO


Rev. 1.02 Jun 26, 2017 Page 56

Figure 39 – LED Pin Connections

Figure 40 – LED Pin Configuration


Rev. 1.02 Jun 26, 2017 Page 57

Chapter 11. Security The Gateway comes with a Trusted Objects TO136-A-DFN6 security device. For detailed

information on how to use this device’s features, contact your Avnet sales representative.

Pin Name Pin Number

Mode Pull Up

Drive Capacity

Output Type

IRQ Pin Function

SE I2C BUS EN

I2C Address: 0x27, PORT1, BIT6

SCL P706 Peripheral None Low CMOS RXD3_SCL3_MISO3

SDA P707 Peripheral None Low CMOS TXD3_SDA3_MOSI3

Figure 41 – Trusted Object Pin Connections

Chapter 12. Programming Methods The Gateway can be programmed either through J-Link

OB or SWD protocols. To simplify programming, the

Gateway is designed with J-Link on-board. This allows

programming to be done directly from either of the

Synergy supported development environments using

only a USB Type-A to USB Micro Type-AB cable. This

removes the need for special programming cables and

is the recommended way to program/debug

applications.

http://www.trusted-objects.com/solutions/solutions-at-a-glance/


Rev. 1.02 Jun 26, 2017 Page 58

Chapter 13. Additional Information

Hardware Partner Information Hardware partners played an integral role in the definition, development, and deployment of this

Gateway. Without their numerous contributions, this project would not have been possible.

• Future Designs, Inc. – http://www.teamfdi.com

• Laird – https://www.lairdtech.com

• Microchip Technology, Inc. – http://www.microchip.com

• Micron Technology, Inc. – https://www.micron.com

• NXP Semiconductors – http://www.nxp.com

• Renesas Electronics – http://synergygallery.renesas.com

• Silicon Labs – http://www.silabs.com

• STMicroelectronics – http://www.st.com

• Trusted Objects – http://www.trusted-objects.com

http://www.teamfdi.com/

https://www.lairdtech.com/

http://www.microchip.com/

https://www.micron.com/

http://www.nxp.com/

http://synergygallery.renesas.com/

http://www.silabs.com/

http://www.st.com/

http://www.trusted-objects.com/


Rev. 1.02 Jun 26, 2017 Page 59


Rev. 1.02 Jun 26, 2017 Page 60


Rev. 1.02 Jun 26, 2017 Page 61


Rev. 1.02 Jun 26, 2017 Page 62


Rev. 1.02 Jun 26, 2017 Page 63


Rev. 1.02 Jun 26, 2017 Page 64

Visible Things Industrial IoT Gateway

Documents

Transcript of Visible Things Industrial IoT Gateway