Virtuoso Design Platform Update

Virtuoso Design Platform Update

Yonatan Kliger, April-2019Custom IC, Application Engineer Director

2 © 2018 Cadence Design Systems, Inc. All rights reserved.

Virtuoso Design PlatformA brief history

+30 Years of Continuous Innovation

Schematic-Driven Layout

Parameterized Cells

Analog Design Environment

Open Access

Design Constraints

Electrically Aware Design

Advanced Node

IC4

IC5

IC6

ICADV12


Virtuoso IC Design PlatformRelease: What’s new?

• Two new Virtuoso® releases– Virtuoso IC6.1.8

– Virtuoso ICADVM18.1

• Virtuoso IC6.1.8– Mature nodes and methodologies

– Continue to be supported and enhancement

• Virtuoso ICADVM18.1– Virtuoso Advanced Methodologies release

– Supports wide spectrum of technologies

– New! Special support for advanced nodes down to 5nm

– New! Advanced design automation

– New! Expanded Virtuoso System Design Platform capabilities

– New system design solutions: Virtuoso RF Solution, Virtuoso Photonics Solution

– Will replace ICADV12.x release (ICADV12.x EoL)

5 © 2018 Cadence Design Systems, Inc. Cadence confidential.

Advanced Node With Support Down To 5nmØ Comprehensive Advanced Node Support Across all Major Foundries

Ø Advanced Statistical Algorithms Improves Analysis by 20%Ø Advanced Grid System, Improves Layout Efficiency by >3X

Advanced Design AutomationØ Enhanced Spectre® Integration with 3X throughput Improvements

Ø Simulation Driven Layout For Robust Layout DesignØ Advanced Layout Automation & Concurrent Team Design

Enhanced System Design PlatformØ Enables Heterogeneous System Design

Ø Seamless Integration With Cadence®SiP and Sigrity™PlatformsØ Simultaneous Editing Across Multiple Technologies

ICADVM

18.1


Virtuoso Design Platform – Mixed-Signal & System Design Solutions

System Analysis

8 © 2018 Cadence Design Systems, Inc. Cadence confidential.

Advanced node with support down to 5nmØ Comprehensive advanced-node support across all major foundriesØ Advanced statistical algorithms improves analysis by 20%Ø Advanced grid system, improves layout efficiency by >3X

Advanced design automationØ Enhanced Spectre® Integration with 3X throughput ImprovementsØ Simulation-driven layout for robust layout designØ Advanced layout automation and concurrent team design

Enhanced system design platformØ Enables heterogeneous system designØ Seamless integration with Cadence® SiP and Sigrity™ platformsØ Simultaneous editing across multiple technologies

ICADVM

18.1

PhotonicsRF/mmWave Advanced PackagingSystem Design

Analog & Mixed-SignalAdvanced FinFET Processes

P&R AutomationSimulation Driven Design


Virtuoso ICADVM18.1 – Advanced Methodologies ReleaseWhat’s new?


Advanced node with support down to 5nm➢ Comprehensive advanced-node support across all major foundries

➢ Advanced statistical algorithms improves analysis by 20%

➢ Advanced grid system, improves layout efficiency by >3X

Advanced design automation➢ Enhanced Spectre® Integration with 3X throughput Improvements

➢ Simulation-driven layout for robust layout design

➢ Advanced layout automation and concurrent team design

Enhanced system design platform➢ Enables heterogeneous system design

➢ Seamless integration with Cadence® SiP and Sigrity™ platforms

➢ Simultaneous editing across multiple technologies

ICADVM

18.1


Virtuoso ADE Product SuiteThe right tool for the job

• Virtuoso ADE Explorer

– Highly interactive, single testbench analyzer that assists engineers at the earliest stages of circuit design

• Virtuoso ADE Assembler

– Interactive, multi-testbench environment that is designed to pull together all the parts of the design and their various specs to begin centering the design for manufacturing

• Virtuoso Variation Option

– Extensive statistical verification for designs requiring high-sigma validation and for advanced nodes

• Virtuoso ADE Verifier

– Introduces a formal method for doing overall electrical specification verification of analog circuits


Virtuoso ADE Product SuiteYou can save it in a Plotting Template too!

• Enable sensible and predictable manipulation of the sizing of sub windows

• Allow meaningful drag to empty space

• Provide the ability to easily swap subwindows

• Choose a preferred grid size (up to 6x8)


9

Virtuoso implementation

ClioSoft Confidential © 2019 ClioSoft Inc.

SOS data mgmt.

operations natively

integrated


ClioSoft Confidential © 2019 ClioSoft Inc.10

Powerful way to navigate

and operate on your

design

Icons propagate to

indicate status

Select and operate on

multiple libraries, cells or

views (not single select as in

Lib Manager)

Customize to display

desired attributes as

columns

Rich filter and sort

options

Visualize and operate

on design hierarchy

Feature rich design manager/browser


ClioSoft Confidential © 2019 ClioSoft Inc.11

Visual Design Diff (VDD)

Invoke VDD to identify

modifications made to

schematic/layout

Select versions to be

compared

Option to ignore

cosmetic differences

Visualize and compare

entire cell hierarchy

Identify additions,

deletions, properties

changed

Step through the

changes


Introducing Quantus™ Smart View

Up to 7X Faster than Current Extracted View

Up to 7X Smaller Size than Extracted View

and up to 3X Smaller than DSPF

10X Faster Virtuoso® ADE Netlisting Time


Virtuoso ICADVM18.1Introducing a new and advanced layout environment

Virtuoso® Layout Suite EXL

Layout

XL

Layout

EAD

Advanced

Automation


Virtuoso Advanced Methodologies ICADVM18.1Introducing: Virtuoso Layout Suite EXL – An advanced layout environment

• Virtuoso® Layout Suite XL– Connectivity- and constraint-driven layout environment

– Subsumes all shape-based features, functions, and APIs

• Virtuoso Layout Suite EXL– New custom layout environment for advanced methodologies

– Subsumes all Virtuoso Layout Suite XL features and functions

– Includes Virtuoso Layout Suite EAD features and plug-ins

– Includes selected Virtuoso Layout Suite GXL capabilities, ModGens, and pin-to-trunk routing

– In-design RC extraction and EM-IR analysis

– New! Concurrent layout editing

– New! Custom rows infrastructure for advanced structured methodology

– New! Track-based and row-based automatic placement and routing

– New! Layout planning and routing planning and analysis

– New! Simulation-driven layout for planning and implementation

– New! Quantus™ Field Solver integration into EAD

– *New! Editing support for RF module design and advanced packaging

Layout EXLLayout XL

New Binder /Improved Extractor

ConcurrentLayout Editing

Wire Editor

Design-rules & Constraint Driven

Smart Vias

Schematic-Driven Layout

Core LayoutEditing

*requires additional licensing – next slide


Virtuoso ICADVM18.1To find out more…











ICADVM

18.1


Virtuoso Advanced Node Solution Ecosystem update

• Over 150 customers using Virtuoso® Advanced Node in production today

• Major growth in advanced node custom/analog space– Many new technology advancements and more in the works

– Real opportunity to revolutionizing the custom/analog space

• More than just Tier 1 suppliers– Many new IP companies feeding advanced node ecosystem

• Certified for 20nm,16nm,12nm, 10nm, 7nmand now 5nm


Virtuoso Advanced-Node Layout DesignAddressing the challenges of advanced process technologies down to 5nm

• Unique multi-grid system for placement and routing…Novel way to abstract complex design rules

• New! Automatic and assisted placers

• New! In-design fill

• New! Device-level, row-based routing

• New! 5nm constraints











ICADVM

18.1


Virtuoso System Design PlatformCross-Platform Solution for the Next Wave of System Design

Virtuoso and Spectre® Solutions (Schematic, Layout, ADE, and Simulation)

Cadence® SiP(Advanced IC Package/Module Design)

Pa

cka

ge

PC

BIC

Allegro® PCB(Analog, RF, and Digital PCB Design)

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Sig

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Virtuoso System Design Platform


New Virtuoso RF SolutionInnovations for the next wave of RFIC and RF module design

RF module and RFIC co-design environment

Edit-in-Concert™️ – simultaneous editing across

multiple technologies with Multi-PDK support

Single “golden” schematic for implementation,

verification, and electromagnetic analysis

Seamless integration of electromagnetic extraction

and analysis solutions

Interoperability with Cadence® SIP


Partnering for System Design Enablement

© 2017 Cadence Design Systems, Inc..4

ICADVM

18.1

RF Module and RFIC co-design environment

Multi-PDK Support and simultaneous editing across multiple technologies

Single “Golden” schematic for Implementation, verification and electromagnetic analysis

Seamless Integration of electromagnetic extraction and analysis solutions

Interoperability with Cadence SIP

The New Cadence Virtuoso RF Solution and AXIEM 3D Planar EM Software Integration

Traditionally, each major stage in the IC development process has operated in isolation supported by a unique and dedicated set of design tools, models, languages and data formats, which can cause design failures due to the manual translation of data between numerous disjointed tools. To address this issue and streamline the RFIC and RF module design flow, Cadence delivered the following capabilities within the new Virtuoso RF solution:

• RFIC and RF Module co-design: Provides a robust design environment enabling simultaneous editing of multiple ICs on a complex RF module while streamlining design to manufacturing tasks

• Single “golden” schematic: Offers schematic-driven layout implementation, EM analysis and simulation and physical verification checks of RFIC and RF module design through a single schematic source, reducing design failures

• Smart electromagnetic (EM) simulation interface: Includes an integration between the Cadence® Sigrity™ PowerSI® 3D EM Extraction Option and the Virtuoso RF Solution, which automates hours of manual work required to run critical passive component and interconnect EM simulations so users can run multiple in-design experiments

As part of the collaboration between the two companies, the Cadence interface has been extended to include an integration with the AXIEM 3D planar EM simulator, within the Cadence Virtuoso RF Solution design environment. The AXIEM software’s fast solver technology readily addresses passive structures, transmission lines, large planar antenna and patch array problems with more than 100,000 unknowns, providing the accuracy, capacity and speed engineers need to help them ensure design integrity upon the first attempt. It also incorporates NI’s proprietary full-wave planar Method of Moments (MoM) technology that enables discrete- and fast-frequency sweeps.

The integrated Cadence and NI EM solutions equip engineers with a variety of EM analysis methods for designing RFICs and RF modules.


Virtuoso RF Solution – RF Module and RFIC Co-Design Environment

Unified EM Analysis Environment

Common EM View

Multiple EM Analysis Techniques

Quantus™

RLCK

AXIEM

MoM

Sigrity™

3D EM

Cadence®

SiP

Virtuoso

Layout

Virtuoso

Schematic

Virtuoso®

ADE

Sigrity/AXIEM

Golden Schematic

• Highly optimized design environment for RF module and RFIC design

• Single ”golden” schematic for LVS verification, simulation, and EM analysis

• Interoperability with Cadence SiP Layout

• Integrated electromagnetic (EM) extractors and simulators

Virtuoso

EM Integration

© 2018 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence, the Cadence logo, and the other Cadence marks found at www.cadence.com/go/trademarks are trademarks or registered trademarks of Cadence Design

Systems, Inc. Accellera and SystemC are trademarks of Accellera Systems Initiative Inc. All Arm products are registered trademarks or trademarks of Arm Limited (or its subsidiaries) in the US and/or elsewhere. All MIPI

specifications are registered trademarks or service marks owned by MIPI Alliance. All PCI-SIG specifications are registered trademarks or trademarks of PCI-SIG. All other trademarks are the property of their respective owners.

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Virtuoso Design Platform Update

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