VIPIX, pSuperB, (SuperB)

Atlas/FTK

M. Villa04/11/2010

VIPIX (2009-2011)

• Sviluppo di sensori a pixel in integrazione verticale– High bandwidth– High rate (100 MHz/cm2)– Data push – Time identification 100 ns– Spatial resolution 12 um– Low budget material (<<1 Xo)

• Caratterizzazione dei sensori su fascio– Trigger/DAQ – Memorie associative

Opto Electronicsand/ or Voltage Regulation

Digital Layer

Analog Layer

Sensor Layer

Physicist’s Dream

50 um

Power I n

Optical I n Optical Out

MAPS 2D Hybrid 2D MAPS 3D Hybrid 3D

AREO APSEL3D, 4D

APSEL3D_TC

SORTEX FE4D32x128

SQUARE 3DMAPX 3DHPX

Readout architecture core version

Sensor Technology

Mixing interdetto

NomiIndicativi prossime sottomis-sioni

Caratteristiche ed innovazioni introdotte nelle varie architetture:•1 : AREO (Apsel family Read Out)

• Apsel family read out• MP management logic• Parallel hit encoding• Sparsified column readout

• 2 : SORTEX (SORTed EXtraction)• Time sorted hit extraction• horizontal parallelization (submatrices)• zone sparsification / output compression• I2C-like interface

• 3: SQUARE (Sequenced QUery Advanced REadout)• No MP• Matrix TS query for time sequenced readout• Single column parallel sparsified readout (higher efficiency)• higher Time Resolution (more robust time sorting for short BC)

4

Type MAPS Techn. STM 0.13Matrix 8x32

Type 3D MAPS Techn. Tezz. C. 0.13Matrix 8x32

Type Hybrid Techn. STM 0.13Matrix 32x128

Type MAPSTechn. STM 0.13Matrix 32x128

APSEL3D

APSEL3D _TC

APSEL4D

FE4D32x128 alias SuperPX0

(Più o meno in scala fra loro)

Architetture scalate per matrici di dimensioni ridote

2006

2007

2009

NP!!

2009

arrivato ieri

Chip dimensions for Layer0 pixel module

12.8 mm

10 m

mR

eado

ut=

10-30mm

2A

rea

~3

xa

rea

from

FE

32

x1

28

1-3 mm

14.79-16.79 mm

10.5

6 m

m

0.25 mm

~ 7

5 P

ad –

pit

ch 1

30

m Beam axis

12-05-2010

0.120 mm cut line

0.5 mm~

75 Pad

– pitch

130 m

~ 75 P

ad – p

itch 130

m

Piste data line di 2 sottomatrici 0.16 mm

Piste data line di 2 sottomatrici 0.16 mm

Submatrix 1

Submatrix 2

Submatrix 3

Submatrix 4

256x192 pixel matrix

50 m pitch

Active area=128mm2

Produrremo un ritaglio!

6.4 mm

5 m

mR

eado

ut=

8mm

2A

rea

~x

2x

are

a fro

m F

E3

2x

12

8

1.6 mm

8.99 mm

5.56

mm

Chip dimensions for APSELVI 128x96 Chartered/Tezzaron

0.25 mm

~ 3

8 P

ad –

pit

ch 1

30

m Beam axis

6-07-2010

0.120 mm cut line

0.5 mm~

38 Pad

– pitch

130 m

~ 38 P

ad – p

itch 130

m

Piste data line di 2 sottomatrici 0.16 mm

Piste data line di 2 sottomatrici 0.16 mm

Submatrix 1: 128x48

Submatrix 2: 128x48

128x96 pixel matrix

50 m pitch

Active area=32mm2

Parallelamente…. DAQ: EDRO V2• Born as a SLIM5 DAQ

board– Recycling several

boards: CMS muon trigger mezzanine, VME, CMS barrel sorter, S-Link & TTCrq

• Used happily in beam tests• Reused in ATLAS as the

LUCID DAQ board:– Bunch-by-bunch

luminosity evaluation• Next use:

– ZDC luminosity measurements

– VIPIX DAQ– Vertical Slice “DO”

board

Can interface with an Associative Memory

board for triggering purposes

VIPIX DAQ duties

Obbiettivo principale: Test beam settembre 2011

• Installare in gennaio-giugno tutta l’infrastruttura di beam test a Bologna:– 4 piani strip; 4 scintillatori;– 2 maps digitali (Apsel-like) + 1 analogico– 1-4 MAPS Perugine (RAPS)– 1 chip MIMOROMA3

pSuperB: progetto pilota SuperB (R&D only)

• Coinvolgimento di Bologna sulle tematiche del vertex detector: 80-90 % overlap con VIPIX– Chip di lettura– DAQ

Elevate sinergie con il PRIN 2009 se verra’ approvato

The SuperB Silicon Vertex TrackerBaBar SVT• 5 Layers of double-sided Si strip

sensor

• Low-mass design. (Pt < 2.7

GeV)• Stand-alone tracking for slow

particles.• 97% reconstruction efficiency• Resolution ~15μm at normal

incidence

t r

eso

luti

on

(p

s)

MAPS (2 layers)

Hybrid Pixels

(single layer)

B decay mode, =0.28, beam pipe X/X0=0.42%, hit resolution =10 m

40 cm30 cm

20 cm

Layer0

old beam pipe

new beam pipe

• Layer0 subject to large background and needs to be extremely thin:

> 5MHz/cm2, > 1MRad/yr, < 1 %X0

•Can use Babar SVT design for R>3cm•Reduced beam energy asymmetry (7x4 GeV vs. 9x3.1 GeV) requires improved vertex resolution

•Layer0 very close to the IP (R~ 1.5 cm) with low material budget

•Background levels depends steeply on radius•Layer0 needs to have fine granularity and radiation tolerance

R&D on strip/pixel options

Hybrid pixel: • Prototype Front-end chip for hybrid pixel (32x128, 50 um pitch) tested

– Results in fair agreement with simulation

• Pixel sensor matrix produced and tested: good quality• FE chip + sensor matrix bump-bonding in june and test in lab in September

CMOS MAPS: • Pixel readout architecture for next matrix (3D MAPS with 2 CMOS layers

interconnected, ~Dec 2010) could work in data push and triggered mode– triggered readout reduces pixel module complexity (lower speed for links & less

material for pixel bus)

• Layer0 with striplets (technology mature but need some work):

– Readout chip! (totally missing)

– Module assembly with multilayer fanout (still uncovered !)

– HDI/transition card electronics (partly covered by M.Citterio assuming similar to pixel option…not enough!)

12

DAQ reading chain for L0-L5HDI +Transition card+FEB+ROM DAQ chain independent

on the chosen FE options

Frascati, 28/09/10

Pi+Bo+Bg/Pv Milano Bologna

ATLAS/FTK

• Progetto di tracking veloce in ATLAS basato sulle memorie associative

• Si dovrebbe collocare tra il primo livello di trigger ed il secondo. E’ denominato L1.5

• “Feature extraction on L1 data”

• Approvato in ATLAS in primavera• 2 Steps:

– 2012 Vertical-slice test (parassitaggio su un quadrante)

– 2013… Installazione su tutto ATLAS

Siamo coinvolti

Ci vogliono ma nonabbiamo dato la disponibilita’ per ora

Francesco Crescioli 14

Event selection –triggerLHC frequency 40 MHz

Events frequency on tape/disc 100 Hz

Selection is necessary

3 trigger levels

first level (HW)

HLT (SW)

second level

Event FilterFTK

FTK: HW processor to reconstruct charged tracks at LVL2

Pt>1 GeV

Inside the whole ID

~off-line quality

Works in parallel with DAQCan be added even after the data taking has began

Francesco Crescioli 15

Fast Tracker – Struttura internaRicieves hits from DAQComunicates with Associative Memory boardsSends hits & found roads to the Fitter6 boards in parallelEach DO handles 1-2 layers

Performs pattern recognition on Super Bins Send back found roads to DO

Roads and hits with high risolution are composed and the Linear Fitis executed to select real tracks, stored in a buffer ready for the LVL2 CPUs

Struttura modulare

Piu` processori possono lavorare in parallelo

E` possibile iniziare con una versione prototipale e poi aggiungere

EDRO in Vertical slice

Guadagni con FTK• Miglior rapporto segnale/fondo; migliore

capacità di discriminazione ai livelli di trigger bassi maggiore statistica finale

Bs→μμ Results (CDF – ATLAS – ATLAS + FTK)

CDF with 780 pb-1 of data 16/3/2006

BR < 1.0x10-7 @95% CLATLAS (2006)

LVL1 2 muons Pt>6 GeV

30 fb-1 21 B events 60 Backgr.

BR < 6.6x10-9 @90% CL

ATLAS + FTK

LVL1 singolo muone Pt>6 GeV

30 fb-1 2nd Pt>6 GeV

66 events (|η|<1 prototype)

178 events (|η|<2.5|)

background LVL2 Rate for 2nd

Pt>3 GeV O(10Hz)

Joint venture

• Vertical Slice:– Pisa: AM board aggiornata – Americani: Interfaccia vs rivelatori a Pixel– Frascati: ricezione hit e clustering (EPMC)– Bologna: Data organizer

(firmware/software)

Elevate sinergie con il PRIN 2009 se verra’ approvato

Mezzanina ricezione hits

• Compatibilita’ EDRO;• Usabile anche per SuperB

• Progetto finito; produzione 10 pezzi a breve

Riassumendo• Impegni certi:

– VIPIX: sviluppo architetture RO, layout 2 chips– VIPIX: test beam 2011 – Software/firmware– pSuperB/SuperB: sovrapposizione VIPIX– ATLAS/FTK: commitment fino alla vertical slice (2012)– ATLAS/FTK: sviluppo software e firmware (Ing. Ele.)

• Impegni possibili/da decidere:– ATLAS/FTK oltre il test del 2012– SuperB (se approvato) quante forze?– Oltre il 2011: continuazione di VIPIX?

• Impegni probabili: Prin2009/Vipix+FTK-like• Impegni chiusi: Prin2007