Counterlibrary ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity counter is port(clk,rst:in std_logic; counter_out:out std_logic_vector(3 downto 0) ); end counter; architecture counter_a of counter is signal count:std_logic_vector(3 downto 0); begin process(clk,rst) begin if(rst='0')then count<="0000"; else if(clk'event and clk='1')then count<=count+1; end if; end if; end process; counter_out<=count; end counter_a;

Test Benchlibrary ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity counter_tb is end counter_tb; architecture counter_tb_a of counter_tb is component counter is port ( clk : in std_logic; rst : in std_logic; counter_out : out std_logic_vector(3 downto 0) ); end component; signal clk : std_logic:='0'; signal rst : std_logic:='0'; begin cnt : counter port map ( clk => clk, rst => rst, counter_out => open );

clk <= not clk after 5 ns; rst <= '1' after 100 ns; end counter_tb_a; ANDlibrary ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity my_and is port(a:in std_logic; b:in std_logic; c:out std_logic); end my_and; architecture my_and_strut of my_and is begin process(a,b) begin if(a='1' and b='1') then c<= '1'; else c<='0'; end if; end process; end my_and_strut;

my_and_data

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity my_and_data is port(a:in std_logic; b:in std_logic; c:out std_logic); end my_and_data; architecture my_and_data_strut of my_and_data is begin c<=a and b; end my_and_data_strut;

my_or

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity my_or is port(a:in std_logic; b:in std_logic; c:out std_logic); end my_or; architecture my_or_strut of my_or is begin process(a,b) begin

if(a='0' and b='0') then c<= '0'; else c<='1'; end if; end process; end my_or_strut;

OR_DATAlibrary ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity my_or_data is port(a:in std_logic; b:in std_logic; c:out std_logic); end my_or_data; architecture my_or_data_strut of my_or_data is begin c<=a or b; end my_or_data_strut;EXOR

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity my_exor is port(a:in std_logic; b:in std_logic; c:out std_logic); end my_exor; architecture my_exor_strut of my_exor is begin process(a,b) begin if(a=b) then c<= '0'; else c<='1'; end if; end process; end my_exor_strut;

EXOR DATAlibrary ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity my_exor_data is port(a:in std_logic; b:in std_logic; c:out std_logic); end my_exor_data; architecture my_exor_data_strut of my_exor_data is begin c<=a xor b; end my_exor_data_strut;NAND

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity my_nand is port(a:in std_logic; b:in std_logic; c:out std_logic); end my_nand; architecture my_nand_strut of my_nand is begin process(a,b) begin if(a='1' and b='1') then c<= '0'; else c<='1'; end if; end process; end my_nand_strut; NAND DATAlibrary ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity my_nand_data is port(a:in std_logic; b:in std_logic; c:out std_logic); end my_nand_data; architecture my_nand_data_strut of my_nand_data is begin c<=a nand b; end my_nand_data_strut;

NOR library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity my_nor is port(a:in std_logic; b:in std_logic; c:out std_logic); end my_nor; architecture my_nor_strut of my_nor is begin process(a,b) begin if(a='0' and b='0') then c<= '1'; else c<='0'; end if; end process; end my_nor_strut;

NORDATAlibrary ieee;

use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity my_nor_data is port(a:in std_logic; b:in std_logic; c:out std_logic); end my_nor_data; architecture my_nor_data_strut of my_nor_data is begin c<=a nor b; end my_nor_data_strut;

HALF ADDER (STRUCT) library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity my_hadder_structure is port(x:in std_logic; y:in std_logic; c:out std_logic; s:out std_logic); end my_hadder_structure; architecture my_hadder_structure_strut of my_hadder_structure is component my_and port(a:in std_logic; b:in std_logic; c:out std_logic); end component; component my_exor port(a:in std_logic; b:in std_logic; c:out std_logic); end component; begin u0:my_and port map(a=>x, b=>y,c=>c); u1:my_exor port map(a=>x, b=>y, c=>s); end my_hadder_structure_strut;

HALF ADDER (BEH)library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity my_hadder is port(a:in std_logic; b:in std_logic; c:out std_logic; s:out std_logic); end my_hadder; architecture my_hadder_strut of my_hadder is begin process(a,b)

begin if(a=b) then s<= '0'; else s<='1'; end if; if(a='1' and b='1') then c<= '1'; else c<='0'; end if; end process; end my_hadder_strut;

HALF ADDER (DATA) library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity my_hadder_data is port(a:in std_logic; b:in std_logic; c:out std_logic; s:out std_logic); end my_hadder_data; architecture my_hadder_data_strut of my_hadder_data is begin s<=a xor b; c<=a and b; end my_hadder_data_strut;

FULL ADDER (STRUCT) library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;use ieee.std_logic_unsigned.all;entity my_fuladder_structure isport(A:in std_logic;B:in std_logic;C:in std_logic;S:out std_logic;COUT:out std_logic);end my_fuladder_structure;architecture my_fuladder_structure_strut of my_fuladder_structure is component my_and port(a:in std_logic; b:in std_logic; c:out std_logic); end component; component my_or port(a:in std_logic; b:in std_logic; c:out std_logic); end component; component my_exor port(a:in std_logic; b:in std_logic; c:out std_logic);

end component; signal S1: std_logic; signal D1: std_logic; signal C1: std_logic; beginu0:my_and port map(a=>A, b=>B,c=>S1);u1:my_exor port map(a=>A, b=>B, c=>D1);u2:my_and port map(a=>D1, b=>C,c=>C1);u3:my_exor port map(a=>D1, b=>C, c=>S);u4:my_or port map(a=>S1, b=>C1, c=>COUT);end my_fuladder_structure_strut;

FULL ADDER (BEH)USING VARIABLElibrary ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity my_fuladder is port(a:in std_logic; b:in std_logic; c:in std_logic; s:out std_logic; cout:out std_logic); end my_fuladder; architecture my_fuladder_strut of my_fuladder is begin process(a,b,c) variable s1:std_logic; variable c1:std_logic; variable d1:std_logic; begin s1:=a xor b; c1:=s1 and c; d1:=a and b; if(s1=c)then s<= '0'; else s<='1'; end if; if(d1 ='0' and c1='0')then cout<='0'; else cout<='1'; end if; end process; end my_fuladder_strut;

USING SIGNAL

library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;use ieee.std_logic_unsigned.all;entity my_fuladder isport(a:in std_logic;b:in std_logic;c:in std_logic;s:out std_logic;cout:out std_logic);end my_fuladder;architecture my_fuladder_strut of my_fuladder issignal s1:std_logic;signal c1:std_logic;signal d1:std_logic;beginprocess(a,b,c,s1,c1,d1)

begin

if(a=b) then s1<= '0';else s1<='1';end if;

if(s1=c)then s<= '0';else s<='1';end if;

if(s1 ='1' and c='1')thenc1<='1';else c1<='0';end if;

if(a ='1' and b='1')thend1<='1';else d1<='0';end if;

if(d1 ='0' and c1='0')thencout<='0';else cout<='1';end if;

end process;end my_fuladder_strut;

FULL ADDER (DATA)library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;use ieee.std_logic_unsigned.all;

entity my_fuladder_data isport(a:in std_logic;b:in std_logic;c:in std_logic;s:out std_logic;cout:out std_logic);end my_fuladder_data;architecture my_fuladder_data_strut of my_fuladder_data isbegins<=a xor b xor c;cout<= (a and b) or ((a xor b) and c);end my_fuladder_data_strut;2*4 DECODERlibrary ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity my_2by4decoder_structure is port(A:in std_logic; B:in std_logic; E:in std_logic; Z0:out std_logic; Z1:out std_logic; Z2:out std_logic; Z3:out std_logic); end my_2by4decoder_structure; architecture my_2by4decoder_structure_strut of my_2by4decoder_structure issignal ABAR:std_logic;signal BBAR:std_logic;component my_notport(a:in std_logic; b:out std_logic);end component; component my_3inputand port(a:in std_logic; b:in std_logic; c:in std_logic; z:out std_logic); end component;beginu0:my_not port map(a=>A,b=>ABAR);u1:my_not port map(a=>B,b=>BBAR);u2:my_3inputand port map(a=>E,b=>ABAR,c=>BBAR,z=>Z0);u3:my_3inputand port map(a=>E,b=>ABAR,c=>B,z=>Z1);u4:my_3inputand port map(a=>E,b=>A,c=>BBAR,z=>Z2);u5:my_3inputand port map(a=>E,b=>A,c=>B,z=>Z3);end my_2by4decoder_structure_strut; 4*16 DECOER(USING 2*4 DECODER)library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity my_4by16decoder_structure isport(a0:in std_logic;a1:in std_logic;

a2:in std_logic;a3:in std_logic;E:in std_logic;Z0:out std_logic;Z1:out std_logic;Z2:out std_logic;Z3:out std_logic;Z4:out std_logic;Z5:out std_logic;Z6:out std_logic;Z7:out std_logic;Z8:out std_logic;Z9:out std_logic;Z10:out std_logic;Z11:out std_logic;Z12:out std_logic;Z13:out std_logic;Z14:out std_logic;Z15:out std_logic);end my_4by16decoder_structure;

architecture my_4by16decoder_structure_strut of my_4by16decoder_structure issignal D0:std_logic;signal D1:std_logic;signal D2:std_logic;signal D3:std_logic;

component my_2by4decoder_structure port(A:in std_logic; B:in std_logic; E:in std_logic; Z0:out std_logic; Z1:out std_logic; Z2:out std_logic; Z3:out std_logic); end component; beginu0:my_2by4decoder_structure port map(A=>a0,B=>a1,E=>'1',Z0=>D0,Z1=>D1,Z2=>D2,Z3=>D3);

u1:my_2by4decoder_structure port map(A=>a2,B=>a3,E=>D0,Z0=>Z0,Z1=>Z1,Z2=>Z2,Z3=>Z3);u2:my_2by4decoder_structure port map(A=>a2,B=>a3,E=>D1,Z0=>Z4,Z1=>Z5,Z2=>Z6,Z3=>Z7);u3:my_2by4decoder_structure port map(A=>a2,B=>a3,E=>D2,Z0=>Z8,Z1=>Z9,Z2=>Z10,Z3=>Z11);u4:my_2by4decoder_structure port map(A=>a2,B=>a3,E=>D3,Z0=>Z12,Z1=>Z13,Z2=>Z14,Z3=>Z15);end my_4by16decoder_structure_strut;

8*3 ENCODERlibrary ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all;

entity my_8by3encoder_data is port(D0:in std_logic; D1:in std_logic; D2:in std_logic; D3:in std_logic; D4:in std_logic; D5:in std_logic; D6:in std_logic; D7:in std_logic; E:in std_logic; A:OUT std_logic; B:OUT std_logic; C:OUT std_logic ); end my_8by3encoder_data; architecture my_8by3encoder_data_strut of my_8by3encoder_data is begin A<=D4 OR D5 OR D6 OR D7; B<=D2 OR D3 OR D6 OR D7; C<=D1 OR D3 OR D5 OR D7; end my_8by3encoder_data_strut;2*1 MUXlibrary ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity my_2by1mux_structure isport(A:in std_logic;B:in std_logic;S:in std_logic;Z:out std_logic);end my_2by1mux_structure;architecture my_2by1mux_structure_strut of my_2by1mux_structure is component my_not port(a:in std_logic; b:out std_logic); end component; component my_or port(a:in std_logic; b:in std_logic; c:out std_logic); end component; component my_and port(a:in std_logic; b:in std_logic; c:out std_logic); end component; signal D0: std_logic; signal D2: std_logic; signal D1: std_logic; begin

u0:my_not port map(a=>S, b=>D0);

u2:my_and port map(a=>D0, b=>A,c=>D1);

u3:my_and port map(a=>S, b=>B,c=>D2);u4:my_or port map(a=>D1, b=>D2,c=>Z);end my_2by1mux_structure_strut;

4*1 MUX(USING 2*1 MUX)library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity my_4by1mux_structure isport(A:in std_logic;B:in std_logic;C:in std_logic;D:in std_logic;S0:in std_logic;S1:in std_logic;Z:out std_logic);end my_4by1mux_structure;architecture my_4by1mux_structure_strut of my_4by1mux_structure is component my_2by1mux_structure port(A:in std_logic;B:in std_logic;S:in std_logic;

Z:out std_logic); end component; signal X: std_logic; signal Y: std_logic; beginu0:my_2by1mux_structure port map(A=>A, B=>B,S=>S0,Z=>X);

u1:my_2by1mux_structure port map(A=>C, B=>D,S=>S0,Z=>Y);

u2:my_2by1mux_structure port map(A=>X, B=>Y,S=>S1,Z=>Z);

end my_4by1mux_structure_strut;

1*8 DMUXlibrary ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity my_1by8demux_structure isport(S2:in std_logic;S1:in std_logic;S0:in std_logic;

A:in std_logic;

Z0:out std_logic;Z1:out std_logic;Z2:out std_logic;Z3:out std_logic;Z4:out std_logic;Z5:out std_logic;Z6:out std_logic;Z7:out std_logic);

end my_1by8demux_structure;

architecture my_1by8demux_structure_strut of my_1by8demux_structure issignal D0:std_logic;signal D1:std_logic;signal D2:std_logic;

component my_not port(a:in std_logic; b:out std_logic); end component; beginu0:my_not port map(a=>S0,b=>D0);

u1:my_not port map(a=>S1,b=>D1);u2:my_not port map(a=>S2,b=>D2);Z0<=A AND D2 AND D1 AND D0;Z1<=A AND D2 AND D1 AND S0;Z2<=A AND D2 AND S1 AND D0;Z3<=A AND D2 AND S1 AND S0;Z4<=A AND S2 AND D1 AND D0;Z5<=A AND S2 AND D1 AND S0;Z6<=A AND S2 AND S1 AND D0;Z7<=A AND S2 AND S1 AND S0;end my_1by8demux_structure_strut;

D F/F (WITH SYN RESET)library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity my_dflipflop isport(D:in std_logic;CLK:in std_logic;RST:in std_logic;Q:out std_logic);end my_dflipflop;architecture my_dflipflop_strut of my_dflipflop is begin process(CLK,D,RST) begin if(CLK'event and CLK='1') then if(RST='0')then

Q<='0'; else Q<=D; end if; end if; end process; end my_dflipflop_strut;

T F/F (WITH ASYN RESET)library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity my_tflipflop isport(T:in std_logic;CLK:in std_logic;RST:in std_logic;Q:inout std_logic);end my_tflipflop;architecture my_tflipflop_strut of my_tflipflop is begin process(CLK,RST) begin if(RST='0')then Q<='0'; else if(CLK'event and CLK='1') then if(T='0')then Q<=Q; else Q<= not Q; end if; end if; end if; end process; end my_tflipflop_strut;

D F/F (WITH SYN PRESET(PRI) & CLEAR)library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity my_dflipflopwithPC isport(D:in std_logic;CLK:in std_logic;PRESET:in std_logic;CLEAR:in std_logic;Q:out std_logic);end my_dflipflopwithPC;architecture my_dflipflopwithPC_strut of my_dflipflopwithPC is begin process(CLK,D,PRESET,CLEAR) begin if(CLK'event and CLK='1') then if(PRESET='1')then

Q<='1'; else IF(CLEAR='0')THEN Q<='0'; ELSE Q<=D; end if; end if; end if; end process; end my_dflipflopwithPC_strut;

D F/F(WITH ASYN SET AND RESET)library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity my_asyncdflipflop isport(D:in std_logic;CLK:in std_logic;SET:in std_logic;RST:in std_logic;Q:inout std_logic);end my_asyncdflipflop;architecture my_asyncdflipflop_strut of my_asyncdflipflop is begin process(CLK,D,RST,SET) begin if(RST='0')then Q<='0'; else if(SET='1')then Q<='1'; elsif(CLK'event and CLK='1') then Q<=D; end if; end if; end process; end my_asyncdflipflop_strut;

D F/F (WITH SYN SET & RESET USING D F/F WITH ASYN SET & RESET(PRI))library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity my_synchDflipflopwithSR isport(D:in std_logic;CLK:in std_logic;SET:in std_logic;RST:in std_logic;Q:inout std_logic);end my_synchDflipflopwithSR;architecture my_synchDflipflopwithSR_strut of my_synchDflipflopwithSR is signal S1:std_logic; signal R1:std_logic;

component my_asyncdflipflop port(D:in std_logic;CLK:in std_logic;SET:in std_logic;RST:in std_logic;Q:inout std_logic);

end component; begin S1<=SET OR D; R1<=S1 AND RST;

u0:my_asyncdflipflop port map(D=>R1,CLK=>CLK,SET=>'0',RST=>'1',Q=>Q); end my_synchDflipflopwithSR_strut;

4 BIT MULTIPLICATIONlibrary ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity my_4bitmul is port(a : in std_logic_vector(3 downto 0); -- multiplicand b : in std_logic_vector(3 downto 0); -- multiplier p : out std_logic_vector(7 downto 0)); -- product end my_4bitmul; architecture my_4bitmul_strut of my_4bitmul is begin p<=a * b; end my_4bitmul_strut;

3 BIT SYNC UPDOWN COUNTER(WITH ASYN RESET)library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity my_updowncounter is port(clk,rst,mode:in std_logic; counter_out:out std_logic_vector(2 downto 0) ); end my_updowncounter; architecture my_updowncounter_strut of my_updowncounter is signal count:std_logic_vector(2 downto 0); begin -- count<="000"; process(clk,rst,mode) begin if(rst='0')then count<="000"; elsif(clk'event and clk='1')then

if(mode='1')then count<=count+1; else count<=count-1; end if; end if; end process; counter_out<=count; end my_updowncounter_strut; 3 BIT SYNC UPDOWN COUNTER(WITH SYN RESET)library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity my_updownsynchresetcounter is port(clk,rst,mode:in std_logic; counter_out:out std_logic_vector(2 downto 0) ); end my_updownsynchresetcounter; architecture my_updownsynchresetcounter_strut of my_updownsynchresetcounterr is signal count:std_logic_vector(2 downto 0); begin -- count<="000"; process(clk,rst,mode) begin if(clk'event and clk='1')then if(rst='0')then count<="000"; elsif(mode='1')then count<=count+1; else count<=count-1; end if; end if; end process; counter_out<=count; end my_updownsynchresetcounter_strut;

SYN PRELOADED COUNTER(WITH ASYN RESET)

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity my_preloadedcounter is port(clk,rst,mode,load:in std_logic; loadvalue :in std_logic_vector(2 downto 0); counter_out:out std_logic_vector(2 downto 0) ); end my_preloadedcounter; architecture my_preloadedcounter_strut of my_preloadedcounter is signal count:std_logic_vector(2 downto 0);

begin process(clk,rst,load,mo,loadvalue) begin if (rst='0')then count<="000"; else if(clk'event and clk='1')then if(load='1') then count<=loadvalue; else if(mode='1')then count<=count+1; else count<=count-1; end if; end if; end if; end if; end process; counter_out<=count; end my_preloadedcounter_strut;

universal shift register

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all;

entity unishift is port(SinLEFT,SinRIGHT,CLK,RST:in STD_LOGIC; Pin:in STD_LOGIC_VECTOR(3 downto 0); Mode:in STD_LOGIC_VECTOR(1 downto 0); Pout:out STD_LOGIC_VECTOR(3 downto 0); Sout:inout STD_LOGIC); end unishift; architecture unishift_strut of unishift is signal tmp1:STD_LOGIC_VECTOR(3 downto 0);signal tmp2:STD_LOGIC; begin process(CLK,RST) begin if(RST = '0') then sout<='0';

pout<="0000"; tmp1<="0000"; tmp2<='0'; elsif(CLK'event and CLK='1') then case Mode is

when "00" => sout<=tmp2; when "01" => tmp1<=tmp1(2 downto 0) & SinRIGHT; sout<=tmp1(3); tmp2<=tmp1(3); when "10" => tmp1<=SinLEFT & tmp1(3 downto 1); sout<=tmp1(0); tmp2<=tmp1(0); when "11" => Pout<=Pin; when others=> null;

end case;

end if; end process;

end unishift_strut;

ALU library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity my_ALU is port(A:in std_logic_vector(7 downto 0); B:in std_logic_vector(7 downto 0); SEL:in std_logic_vector(2 downto 0); Cin:in std_logic; Y:out std_logic_vector(7 downto 0));

end my_ALU;architecture my_ALU_strut of my_ALU is begin process(A,B) begin case SEL is

when "000" => Y<=A+'1';when "001" => Y<=B+'1';when "010" => Y<=A+B;when "011" => Y<=A+B+Cin;when "100" => Y<= not A;when "101" => Y<=A xor B;when "110" => Y<=A nand B;when "111" => Y<=A xnor B; when others => null;

end case; end process;end my_ALU_strut;