VHDL 프로그래밍VHDL 프로그래밍

5. VHDL 주요 구조

학습 목표학습 목표

Procedure와 function을 사용할 줄 알기

Package를 사용할 줄 알기

event 속성의 사용 방법 알기event 속성의 사용 방법 알기

파일 입출력 사용법 알기파일 출력 사용 알기

type casting 의 개념 알기

타인이 작성한 VHDL code를 판독할 수 있다다

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ContentContent

Procedure와 function

PackagesPackages

Attributes

File processing

AliasAlias

Type casting and type qualification

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VHDL subprogramsVHDL subprograms

일반적인 컴퓨터 언어와 같이 자주 사용하거나 중복 사용되는 부분을 표현하기 위한 도구

FunctionProcedureProcedure

Software의 function이나 procedure와 유사순차적 알고리즘을 정의순차적 알고리즘을 정의선언부와 몸체로 구성됨A hit t b d 나 k 에서 사용됨Architecture body나 package에서 사용됨

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VHDL subprogramsVHDL subprograms

Functionsargument를 입력으로 이용하나의 Return 값을 가짐수행 simulation 시간은 0Examples: Resolution, type conversion, operator overloading, mathematic function

P d ( 문과 유사)Procedures (process문과 유사)No return valueInput/Output/Inout arguments 를 가짐내부에 wait 문 사용 가능E l TEXTIO d i dExamples: TEXTIO : read, write procedure

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Subprogram syntax (declaration)Subprogram syntax (declaration)

Declaration

procedure <proc_name>

(<formal parameter>);(<formal_parameter>);

function <function_name>

( <formal_parameter>) return

<type name> ;<type_name> ;

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Subprogram syntax (body)Subprogram syntax (body)

P d b dProcedure bodyprocedure <proc_name>

( <formal parameter list> ) is( <formal_parameter_list> ) is<procedure_declarative_part>beginbegin<sequential statements>end <proc name> ;end <proc_name> ;

Function body function <func name> (<formal parameter list>) function func_name ( formal_parameter_list )

return <type_name> is<function_declarative_part>begin<sequential statements>

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end <func_name> ;

Subprogram syntax: 인자 부분Subprogram syntax: 인자 부분

Formal parameter부의 사용 제약

class procedure function

constant in in

signal in, out, inout insignal in, out, inout in

variable in out inout 허용되지않음variable in, out, inout 허용되지않음

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Function의 제약사항Function의 제약사항

Signal assignment문을 가질 수 없음

Function은 delay 없이 return함.

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Function의 예Function의 예

library IEEE;

use IEEE.std_logic_1164.all;begin

edge := (clock = ‘1’ andentity dff is

port(

D CLOCK : in std logic;

clock’event);

return edge;

d i i d ;D, CLOCK : in std_logic;

Q, Qbar : out std_logic

);

end rising_edge;

begin

process);

end dff;

architecture beh of dff is

process

begin

wait until (rising_edge(clock));

function rising_edge(signal clk : std_logic) returnboolean is

Q <= D after 5 ns;

Qbar <= not D after 5 ns;boolean is

variable edge : boolean := FALSE;

end process;

end beh;

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Type conversion function의 예Type conversion function의 예

function to_bitvector(s : std_logic_vector) returnbit_vector is

Variable outval : bit vector(s’length 1 downto 0);Variable outval : bit_vector(s length-1 downto 0);beginfor i in s’range loopfor i in s range loopcase s(i) is

when ‘0’ => outval(i) := ‘0’;when 0 => outval(i) := 0 ;when ‘1’ => outval(i) := ‘1’;when others => outval := ‘0’;when others > outval : 0 ;

end case;end loop;end loop;return outval;end to bitvector;

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end to_bitvector;

Procedure의 예Procedure의 예procedure dff(

Concurrent procedure callentity serial_adder isport( reset, clk, a, b : in std logic;

procedure dff(signal d, clk, reset : in std_logic; signal q, qbar : out std_logic ) isport( reset, clk, a, b in std_logic;

r : out std_logic );end serial_adder;architecture struct of serial_adder is

issignal s1, s2 : std_logic;

beginif ( t ‘0’) th < ‘0’ ft 5Component add is

port(a, b, c : in std_logic;

if (reset = 0 ) then q <= 0 after 5 ns;

elsif (rising_edge(clk)) then q <= d after 5 ns;

z, co : out std_logic);end component;

after 5 ns; end if;end dff;

beginC1 : add port map(a => a, b => b, c

=> s1 co => s2);=> s1, co => s2);Dff(clk => clk, reset => reset, d => s2,

q => s1, qbar => open);r <= s1;

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end struct;

PackagesPackages

공통적인 함수, 프로시저, 상수, type 등의 공유 목적유 목적

std, ieee, synopsys, modelsim, xilinx, l lib 등에서 다양한 k 제공altera library 등에서 다양한 package 제공

User Package 사용 가능User Package 사용 가능

구성P k P k d l ti P kPackage := Package declaration + Package Body

Package Body 없이 Package declaration 부만존재 가능

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PackagesPackages

Package Declaration syntaxpackage <package name> ispackage <package_name> is

<package_declarative_part>

end <package_name>;

선언부에 포함될 수 있는 것선언부에 포함될 수 있는 것type declaration, subprogram declaration,

t t d l ti bt d l ticonstant declaration, subtype declaration,

signal declaration, file declaration, alias declaration, component declaration, attribute declaration, attribute specification,

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use clause

PackagesPackages

Package Body Syntaxpackage body <package name> ispackage body <package_name> is

<package_body_declarative_part>

end <package_name> ;

Body에 포함될 수 있는 것y

subprogram body, subprogram declaration, use clauseuse clause

package body 내부에서만 사용하기 위한subtype declaration constant declarationsubtype declaration, constant declaration, file declaration, alias declaration

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Std logic 1164 packageStd_logic_1164 package

Package Declarationpackage PACK1164 istype std uloigc is (

subtype UX01 is resolvedstd_ulogic RANGE ‘U’ to ‘1’;

Package Declaration

type std_uloigc is (‘U’, -- Uninitialized ‘X’, -- Forcing Unknown‘0’ -- Forcing 0

subtype std_logic is resolvedstd_ulogic;

type std_logic_vector is array( )0 , Forcing 0

‘1’, -- Forcing 1‘Z’, -- High Impedance‘W’ W k U k

(NATURAL RANGE <>) ofstd_logic;

function “and” (lh : std_ulogic; h : td l i ) RETURN UX01;W , -- Weak Unknown

‘L’, -- Weak 0‘H’, -- Weak 1

)

rh : std_ulogic) RETURN UX01;function “and (lh, rh :

std_logic_vector) RETURNstd logic vector;‘-’); -- Don’t care

type std_ulogic_vector is array(NATURAL RANGE <>) oftd l i ;

std_logic_vector;function “and (lh, rh :

std_ulogic_vector) RETURNstd ulogic vector;std_ulogic;

function resolved (s : std_ulogic_vector) RETURNstd ulogic;

std_ulogic_vector;end PACK1164;

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std_ulogic;

Std logic 1164 packageStd_logic_1164 package

Package BodyPackage Bodypackage body PACK1164 is type stdlogic table is array (std ulogic std ulogic) of std ulogic;type stdlogic_table is array (std_ulogic, std_ulogic) of std_ulogic;constant resolv_tab : stdlogic_table := (

| U X 0 1 Z W L H |-- | U X 0 1 Z W L H - |( ‘U’, ‘U’, ’U’, ‘U’, ‘U’, ‘U’, ‘U’, ‘U’, ‘U’), -- |U|( ‘U’, ‘X’, ‘X’, ‘X’, ‘X’, ‘X’, ‘X’, ‘X’, ‘X’), -- |X|( ‘U’, ‘X’, ‘0’, ‘X’, ‘0’, ‘0’, ‘0’, ‘0’, ‘X’), -- |0|( ‘U’, ‘X’, ‘X’, ‘1’, ‘1’, ‘1’, ‘1’, ‘1’, ‘X’), -- |1|( ‘U’, ‘X’, ‘0’, ‘1’, ‘Z’, ‘W’, ‘L’, ‘H’, ‘-’), -- |Z|( ‘U’, ‘X’, ‘0’, ‘1’, ‘W’, ‘W’, ‘W’, ‘W’, ‘W’), -- |W|( ‘U’ ‘X’ ‘0’ ‘1’ ‘L’ ‘W’ ‘L’ ‘W’ ‘X’) -- |L|( U , X , 0 , 1 , L , W , L , W , X ), |L|( ‘U’, ‘X’, ‘0’, ‘1’, ‘H’, ‘W’, ‘W’, ‘H’, ‘X’), -- |H|( ‘U’, ‘X’, ‘X’, ‘X’, ‘X’, ‘X’, ‘X’, ‘X’, ‘X’) ); -- |-|

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Std logic 1164 packageStd_logic_1164 package

function resolved (s : std_ulogic_vector) returnstd_ulogic is

variable result : std_ulogic := ‘Z’;beginif(s’LENGTH = 1) thenreturn s(s’LOW);elsefor i in s’range loop

lt l t b ( lt (i))result := resolv_tab (result, s(i));end loop ;

d if;end if;return result;end resolved;

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end resolved;

Std logic 1164 packageStd_logic_1164 package

constant and_tab : stdlogic_table := (-- | U X 0 1 Z W L H - |( ‘U’ ‘U’ ’0’ ‘U’ ‘U’ ‘U’ ‘0’ ‘U’ ‘U’) |U|( U , U , 0 , U , U , U , 0 , U , U ), -- |U|( ‘U’, ‘X’, ‘0’, ‘X’, ‘X’, ‘X’, ‘0’, ‘X’, ‘X’), -- |X|( ‘0’, ‘0’, ‘0’, ‘0’, ‘0’, ‘0’, ‘0’, ‘0’, ‘0’), -- |0|( , , , , , , , , ), | |( ‘U’, ‘X’, ‘0’, ‘1’, ‘X’, ‘X’, ‘0’, ‘1’, ‘X’), -- |1|( ‘U’, ‘X’, ‘0’, ‘1’, ‘X’, ‘X’, ‘0’, ‘X’, ‘X’), -- |Z|( ‘U’ ‘X’ ‘0’ ‘X’ ‘X’ ‘X’ ‘0’ ‘X’ ‘X’) |W|( U , X , 0 , X , X , X , 0 , X , X ), -- |W|( ‘0’, ‘0’, ‘0’, ‘0’, ‘0’, ‘0’, ‘0’, ‘0’, ‘0’), -- |L|( ‘U’, ‘X’, ‘0’, ‘1’, ‘X’, ‘X’, ‘0’, ‘1’, ‘X’), -- |H|( , , , , , , , , ), | |( ‘U’, ‘X’, ‘0’, ‘X’, ‘X’, ‘X’, ‘0’, ‘X’, ‘X’) );-- |-|

function “and” (1h, rh : std_ulogic) return UX01 isbeginbegin return (and_tab(lh, rh));end “and”;

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User Package 사용 예User Package 사용 예

Package Declaration: gfx_pkg.vhd

library IEEE;

use IEEE.std_logic_1164.all;

package gfx_pkg is p g g p g

type primitives is (pointp, rectp, textp, text2p, srcbltp);

-- direction of memory data accessdirection of memory data access

constant MEM_FORWARD : std_logic := '0';

constant MEM BACKWARD : std logic := '1';constant MEM_BACKWARD : std_logic : 1 ;

end gfx_pkg;

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User Package 사용 예User Package 사용 예

Package 사용: gfx.vhdlibrary IEEE;use IEEE STD LOGIC 1164 all;library IEEE;use IEEE.STD_LOGIC_1164.all;

library WORK;use WORK.gfx_pkg.all;

entity inner gfx isentity inner_gfx is

port (

t : i td l i ;reset_n : in std_logic;

vdclk : in std_logic;

prim : in primitives;

begin_span : out std_logic);

end inner_gfx ;

…

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AttributesAttributes

VHDL의 각 object는 값 (value) 외에도속성 (attribute) 을 가질 수 있음속성 (attribute) 을 가질 수 있음

Predefined attribute를 표준으로 제공

User defined attribute 사용 가능

Object data type function name 등도Object, data type, function name 등도attribute를 가질 수 있음

Attribute 사용 형식:<type name or object name> ’<type_name or object_name> <attribute_name>

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대표적인 predefined attributes대표적인 predefined attributes

left, right, high, low, length, range

사용 예

type Day is (Sun, Mon, Tue, Wed, Thu, Fri, Sat);type word is array(15 downto 0);

사용 예

type word is array(15 downto 0);signal theword : word ;D ‘l ft S d’l ft 15 가장 왼쪽값Day‘left= Sun, word’left=15 --가장 왼쪽값Day‘right=Sat, word’right=0 --가장 오른쪽값Day‘high=Sat, word’high=15 --가장 큰값Day’low=Sun, word’low=0 --가장 작은값y , 가장 작Day’length=7, word’length=16 –-원소의 개수theword’range = 15 downto 0

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theword range 15 downto 0

대표적인 predefined attributes대표적인 predefined attributes

i l 관련 tt ib tsignal 관련 attributeS’EVENT : S에 event가 발생한 순간에 true 값을 리턴

( )if (clock’event and clock = ‘1’) then ...end ifS’ACTIVE : 현재 delta 시간 내에 S가 active 되면 trueS’STABLE [(time)] : 명시된 시간 동안 S에 event가 없었다S STABLE [(time)] : 명시된 시간 동안 S에 event가 없었다면 trueS’QUITE [(time)] : 명시된 시간 동안 S에 변화가 없었다면truetrueS’LAST_EVENT : S에 event가 발생한 가장 최근 시각부터현재까지 경과된 시간을 리턴S’LAST VALUE S에 최근의 가 발생하기 직전에 SS’LAST_VALUE : S에 최근의 event가 발생하기 직전에 S가 가졌던 값S’LAST_ACTIVE : S가 active 하게 된 가장 최근 시각부터현재까지 경과된 시간S’DELAY [(time)] : 명시된 시간만큼 delay시킨 S와 같은type의 signal을 리턴

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type의 signal을 리턴

Setup time과 hold time 검사 예Setup time과 hold time 검사 예

check: processbeginbeginwait until rising_edge(clk);assert (D’stable(setup time))assert (D stable(setup_time))

report (“Setup Time Violation”)severity error ;severity error ;

wait for hold_time;assert (D’stable(hold time))( ( _ ))report (“Hold Time Violation”)severity error ;y

end process ;

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FILE 사용 (VHDL87 version)FILE 사용 (VHDL87 version)

VHDL87-Syntax:

file <identifier>: <file_type_name> is [in|out] <logical_file_name>;

VHDL-87 Example:

“ ”file INFILE : TEXT is in “sample.dat”

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FILE (VHDL-93 )- syntaxFILE (VHDL 93 ) syntax

VHDL 93 S tVHDL-93-Syntaxfile <identifier>: <file_type_name> [ [open file_open_mode] is

<logical_file_name> ];g _ _ ]open_file_mode ::= READ_MODE | WRITE_MODE |

APPEND_MODE

VHDL 93 Example:VHDL-93-Example:file INFILE : TEXT open READ_MODE is “sample.dat”;

또는또는

파일 열기

file INFILE : TEXT ;

variable fstatus : FILE_OPEN_STATUS ;

FILE_OPEN(fstatus, INFILE, “sample.dat”, READ_MODE);

또는

FILE_OPEN(INFILE, “sample.dat”, READ_MODE);

파일 닫기

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파일 닫기

FILE_CLOSE (INFILE);

TEXTIO package 선언의 일부TEXTIO package 선언의 일부

PACKAGE TEXTIO IStype LINE is access STRINGtype TEXT is file of STRING;type SIDE is (RIGHT, LEFT);subtype WIDTH is NATURAL;ypfile INPUT : TEXT is in “STD_INPUT”;file OUTPUT : TEXT is out “STD_OUTPUT”;procedure READLINE (variable F : in TEXT; L : inout LINE);procedure READLINE (variable F : in TEXT; L : inout LINE);procedure READ (L : inout LINE; VALUE : out BIT);procedure READ (L : inout LINE; VALUE : out BIT_VECTOR);procedure READ (L : inout LINE; VALUE : out BIT; GOOD: outprocedure READ (L : inout LINE; VALUE : out BIT; GOOD: out

boolean);procedure READ (L : inout LINE; VALUE : out BIT_VECTOR; GOOD : out boolean);GOOD : out boolean);

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TEXTIO package 선언의 일부TEXTIO package 선언의 일부

procedure READ (L : inout LINE; VALUE : out integer);procedure READ (L : inout LINE; VALUE : out TIME);p ( )procedure WRITELINE (F : out TEXT; L : inout LINE);procedure WRITE (L : inout LINE; VALUE : in BIT;JUSTIFIED : in SIDE : RIGHT; FIELD : in WIDTH : 0);JUSTIFIED : in SIDE := RIGHT; FIELD : in WIDTH := 0);procedure WRITE (L : inout LINE; VALUE : in BIT_VECTOR;JUSTIFIED : in SIDE := RIGHT; FIELD : in WIDTH := 0);)procedure WRITE (L : inout LINE; VALUE : in integer;JUSTIFIED : in SIDE := RIGHT; FIELD : in WIDTH := 0);procedure WRITE (L : inout LINE; VALUE : in TIME;procedure WRITE (L : inout LINE; VALUE : in TIME;JUSTIFIED : in SIDE := RIGHT; FIELD : in WIDTH := 0);end TEXTIO;

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예제: 읽고 쓰기예제: 읽고 쓰기

use STD.TEXTIO.all;entity CALC isend CALC;

while (not ENDFILE(INFILE)) loopreadline(INFILE, RD_BUF);read(RD BUF VAL);end CALC;

architecture BEH of CALC isbegin

read(RD_BUF, VAL);read(RD_BUF, ADD);read(RD_BUF,MINUS);g

process file INFILE : text is in “calc.in”;file OUTFILE : text is out

( , )write(WR_BUF, VAL, right, 10);write(WR_BUF, VAL+ADD, right 10);file OUTFILE : text is out

“calc.out”;variable VAL, ADD, MINUS :

i t

right, 10);write(WR_BUF, VAL-MINUS, right, 10);

it li (OUTFILE WR BUF)integer;variable RD_BUF, WR_BUF :

LINE;

writeline(OUTFILE, WR_BUF);end loop;wait;

beginwait;end process ;end BEH;

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TEXTIO 처리과정TEXTIO 처리과정

READLINE

READ WRITELINE

WRITE내부

typeLINE LINEtype

화일화일 화일화일 line line

Li t 의 버퍼 사용!!31/42

Line type의 버퍼 사용!!

Calc in 파일 및 calc out 파일 내용Calc.in 파일 및 calc.out 파일 내용

<calc.in 파일 내용>

21 20 18

0 3 6

1E2 5_4 23_

123_000 100_0 3E5

l 파일 내용<calc.out 파일 내용>

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AliasAlias

variable이나 signal의 일부 또는 전부에다른 이름을 붙여주는 방법다른 이름을 붙여주는 방법

coding시 발생하는 실수를 최소화 할g시 발생하는 실수를 최 화 할수 있음

가독성 가가독성 증가

사용 예 : 16bit instruction set의 구성사용 예 : 16bit instruction set의 구성

d (3) d (4) d d (1) d(8)mode(3) cmd (4) opd_mode(1) opd(8)

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Alias 사용 예architecture arch of instr decoder is

Alias 사용 예architecture arch of instr_decoder issignal instr : std_logic_vector(15 donwto 0);alias mode : std_logic_vector(2 downto 0) is instr(15 downto 13);alias cmd : std_logic_vector(3 downto 0) is instr(12 downto 9);_ g _ ( ) ( );alias opd_mode : std_logic is instr(8);alias opd : std_logic(7 downto 0) is instr(7 downto 0);...begin...process(mode, cmd) begincase mode is

when “000” =>d icase cmd is

when “0000” => ......

end case ;end case ;end case;

end process ;

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...end arch;

Alias 사용 예Alias 사용 예

REAL_NUMBER format에서 sign, mantisa, exponent를 나누는 예exponent를 나누는 예variable REAL_NUMBER : BIT_VECTOR(0 to 31);

( )alias sign : bit is REAL_NUMBER(0);

alias exponent : bit_vector(1 to 7) isREADL NUMBER(1 t 7)READL_NUMBER(1 to 7);

alias mantisa : bit_vector(23 downto 0) isREAL NUMBER(8 d t 31);REAL_NUMBER(8 downto 31);

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Type casting & qualificationType casting & qualification

Type casting

자료형의 변환 방법자료형의 변환 방법

사용법: 자료형 이름(변환하고자 하는 신호)( )

예

t i d tcnt_u: unsigned type

cnt: std logic vector typed_ og _ o yp

cnt_u <= unsigned(cnt);

가급적 i f i 을 이용할 것가급적 type conversion function을 이용할 것

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Type casting & qualificationType casting & qualification

Type qualification (for constants)상수값의 명시를 위해 사용상수값의 type 명시를 위해 사용

사용법: 자료형 이름’(상수값)사용법: 자료형 이름 (상수값)예: cnt <= cnt + std_logic_vector’(“0001”);

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Type casting 예제Type casting 예제

CNT <= CNT + “0001” 의 실행 예CNT : std logic vectorCNT : std_logic_vector

type UNSIGNED is array (NATURAL range <>) of STD LOGIC:STD_LOGIC:

function “+” (L,R: UNSIGNED) return S LOGIC V C OSTD_LOGIC_VECTOR;

덧셈 연산을 위해 L, R 값이 UNSIGNED덧셈 연산을 위해 L, R 값이 UNSIGNED 값이 되도록 type casting

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Type casting 예제Type casting 예제

CNT <= CNT + “0001” 의 실행 코드

library IEEE;use IEEE.std_logic_1164.all;

IEEE td l i ith lluse IEEE.std_logic_arith.all;entity CONVTYPE isport(port(

rst, clk : in std_logic;CNTR : out std_logic_vector(3 downto 0));

d CONVTYPEend CONVTYPE;

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Type casting 예제Type casting 예제architecture RTL of CONVTYPE is

signal CNT : std_logic_vector(3 downto 0);beginbegin

CNTR <= CNT ;process(clk, rst)beginif(rst = ‘1’) then

CNT <= std logic vector’(“0000”);CNT <= std_logic_vector ( 0000 );-- QUALIFICATION

elsif (clk’event and clk = ‘1’) thenCNT <= UNSIGNED(CNT) -- TYPE CASTING+ UNSIGNED’(“0001”); -- QUALIFICATION

end if;end if;end process;

end RTL;

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std logic arith package 예std_logic_arith package 예

package std logic arith is

operator overloading : “+”의 예package std_logic_arith is

type UNSIGNED is array (NATURAL range <>) of STD_LOGIC;type SIGNED is array (NATURAL range <>) of STD LOGIC;type SIGNED is array (NATURAL range <>) of STD_LOGIC;subtype SMALL_INT is INTEGER range 0 to 1;

attribute builtin_subprogram: string;_ p g g

function "+"(L: UNSIGNED; R: UNSIGNED) return UNSIGNED;function "+"(L: SIGNED; R: SIGNED) return SIGNED;function "+"(L: UNSIGNED; R: SIGNED) return SIGNED;function "+"(L: UNSIGNED; R: INTEGER) return UNSIGNED;function "+"(L: UNSIGNED; R: STD_ULOGIC) return UNSIGNED;function "+"(L: UNSIGNED; R: UNSIGNED) return STD_LOGIC_VECTOR;function "+"(L: SIGNED; R: SIGNED) return STD_LOGIC_VECTOR;function "+"(L: UNSIGNED; R: INTEGER) return STD_LOGIC_VECTOR;f ti " "(L STD ULOGIC R UNSIGNED) t STD LOGIC VECTOR

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function "+"(L: STD_ULOGIC; R: UNSIGNED) return STD_LOGIC_VECTOR;

Type conversion functionsType conversion functions

에서 제공std_logic_arith package 에서 제공function CONV_INTEGER(ARG: SIGNED) return INTEGER;function CONV_INTEGER(ARG: UNSIGNED) return INTEGER;function CONV_UNSIGNED(ARG: INTEGER; SIZE: INTEGER) return UNSIGNED;function CONV_UNSIGNED(ARG: UNSIGNED; SIZE: INTEGER) return UNSIGNED;f i CONV UNSIGNED(ARG STD ULOGIC SIZE INTEGER) UNSIGNEDfunction CONV_UNSIGNED(ARG: STD_ULOGIC; SIZE: INTEGER) return UNSIGNED;function CONV_SIGNED(ARG: INTEGER; SIZE: INTEGER) return SIGNED;function CONV_SIGNED(ARG: UNSIGNED; SIZE: INTEGER) return SIGNED;f ti CONV SIGNED(ARG: SIGNED; SIZE: INTEGER) t SIGNED;function CONV_SIGNED(ARG: SIGNED; SIZE: INTEGER) return SIGNED;function CONV_SIGNED(ARG: STD_ULOGIC; SIZE: INTEGER) return SIGNED;function CONV_STD_LOGIC_VECTOR(ARG: INTEGER; SIZE: INTEGER)

return STD LOGIC VECTOR;return STD_LOGIC_VECTOR;function CONV_STD_LOGIC_VECTOR(ARG: UNSIGNED; SIZE: INTEGER)

return STD_LOGIC_VECTOR;function CONV STD LOGIC VECTOR(ARG: SIGNED; SIZE: INTEGER)function CONV_STD_LOGIC_VECTOR(ARG: SIGNED; SIZE: INTEGER)

return STD_LOGIC_VECTOR;function CONV_STD_LOGIC_VECTOR(ARG: STD_ULOGIC; SIZE: INTEGER)

return STD LOGIC VECTOR;

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return STD_LOGIC_VECTOR;