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NETAJI SUBHAS INSTITUTE OF TECHNOLOGY

Azad Hind Fauj Marg, Sector-3, DwarkaNew Delhi-110078.

Project Report

On

COMPOSITE COLOR GENERATION

USING RGB LED

Submitted By: Under the Guidance of:ARUN GOELRoll-No.711/SP/11 Mr. D.V.Gadre ELECTRONICS DEPTT. NSIT,NEW DELHI

ACKNOWLEDGEMENT

I wish to express my thanks to Mr D.V.Gadre for their valuable guidance and co-operation during different phases of my project.

He guided me time to time and gave me dynamic ideas and suggestions without which I am not able to complete my project successfully.

I want to thank all the visible and non-visible hands also, who helped me to complete my project with great success.

(ARUNGOEL)

TABLE OF CONTENTS:

1. Introduction

2. Block Diagram

3. Implementation

3.1 Hardware Implementation3.1.1 Component description

3.2 Software Implementation3.2.1 VHDL Code3.2.2 RTL OF CPLD

4. Schematics

5. References

INTRODUCTION

There are three basic colors of nature i.e. red, green and blue. By appropriate combination of intensity of these colors, it is possible to generate any color.

To generate different colors, RGB LED is used .By varying the current (average current) through the RGB led , different colors can be generated. For this purpose, pulse width modulation circuit is used.

Since this is a digital project, an analog to digital converter is required to convert the applied analog voltage to required digital level. This project is implemented on CPLD XC9572 PC-44 with the help of software platform Xilinx8.2i written in VHDL.

BLOCK DIAGRAM OF COMPOSITE COLOR GENERATION USING RGB LED

ANALOG TO DIGITAL

CONVERTOR

PULSE WIDTH

MODULATION CIRCUIT

POWER SUPPLY

CIRCUIT

CIRCUIT

RGB LED

REFERENCEINPUT

VOLTAGE

IMPLEMENTATION

2.1) HARDWARE IMPLEMENTATION

Analog to Digital Convertor (ADC ) and Pulse Width Modulation Circuit (PWM) is implemented inside CPLD and programmed using VHDL . The system consists of a clock input of 112Hz .

2.1.1)COMPONENT DISCRIPTION

1) POWER SUPPLY CIRCUIT :

a) Four Diodes IN-4007( Bridge rectifier circuit as Partial Idiot Proof Circuit).

b) One Regulator IC LM-7805(For 5v regulated output)

c) One Heat sink(For elimination of heat from the regulator IC)

d) One Cylindrical Capacitor( 10 micro farad/50 volt )

e) Nine -Ceramic Capacitors( 0.01 uf,0.1 uf )

f) 39 NOS - Resistances –1k(36nos),10k(1nos),68k(1nos),470ohm

g) One – LED (Power Supply Indicator)

2) CLOCK :

The frequency of the clock is 112 Hz. Following components are used for the generation of clock:

a) IC 555 Timer

b) One capacitors of value as 10 micro farad and two capacitor of .01uF .

c) Two resistance of 470 ohm .

3) JTAG CONNECTOR:

JTAG (JOINT TEST ACTION GROUP) connector has been used to program the CPLD.

4) CPLD:

CPLD Used: XILINX XC-9572-15 PC 44 IC.

5) RGB LED:

Common Anode type one RGB LEB with one resistance of value 470 ohm and two resistance of 1K ohm.

6) CURRENT SOURCE

a) One Regulator IC LM-7809( 9v regulated output for Current Source)

b) One Heat sink(For elimination of heat from the regulator IC)

c) One PNP Transistor BC 557

d) One Zener Diode(Vz=1.5 V)

e) FIVE Diode IN4007

f) Two Resistance of value 15K, four Resistance of Value 100K and one of 33K

g) One Capacitor 1uF/50V

7) ELECTRONIC SWITCH

a) One NPN Transistor BC 547

b) One Resistance of value 1KOhm.

2.2) SOFTWARE IMPLEMENTATION

The coding is done on Xilinx ISE 8.2i using VHDL.

A behavioral model of design is followed for the definition of the module of the design, like counter2bit, counter6bit, latch6bit etc. This is followed by a structural integration of th to form the device. The CPLD used was XC-9572PC84.

2.2.1)VHDL Code--------------------------------------------------------------------------------------------------------------------------------------------------------------------

------------------------------------------------------------------------------------ Company: Nsit------------------------------------------------------------------------------------------------------------------------------------------------------------------------ Engineer: ARUN GOEL-- Create Date: 18:04:54 11/12/2011 -- Design Name: COMPOSITE COLOR GENERATION USING RGB LED-- Module Name: compositecolorgeneration - Behavioral -- Project Name: COMPOSITE COLOR GENERATION USING RGB LED-- Target Devices: XILINIX XC 9572-15 PC44

-- Tool versions: -- Description: ---- Dependencies: ---- Revision: -- Revision 0.01 - File Created-- Additional Comments: ------------------------------------------------------------------------------------library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating---- any Xilinx primitives in this code.--library UNISIM;--use UNISIM.VComponents.all;

entity compositecolorgeneration isPort(opampinput :in std_logic;clock :in std_logic;redpin :out std_logic;greenpin :out std_logic;bluepin :out std_logic;switch :out std_logic;ofo :out std_logic);end compositecolorgeneration;

architecture Behavioral of compositecolorgeneration iscomponent comp2bit Port ( color : in STD_LOGIC_VECTOR(1 DOWNTO 0); count : in STD_LOGIC_VECTOR(1 DOWNTO 0); c : out STD_LOGIC);end component;

component controlcircuit Port ( ip : in STD_LOGIC; clk : in STD_LOGIC;

overflowinput : in STD_LOGIC; latch : out STD_LOGIC; rstcounter : out STD_LOGIC; sw : out STD_LOGIC; overflowout : out STD_LOGIC; rstlatch : out STD_LOGIC; rst_2_counter : out STD_LOGIC);end component;

component counter2bit Port ( reset : in STD_LOGIC; clock : in STD_LOGIC; count : out STD_LOGIC_VECTOR (1 downto 0));end component;

component counter_6bit Port ( reset : in STD_LOGIC; enb : in STD_LOGIC; clk : in STD_LOGIC; overflow : out STD_LOGIC;

c : out STD_LOGIC_VECTOR (5 downto 0));end component;

component latch6bit Port ( a : in STD_LOGIC_VECTOR (5 downto 0);

b : out STD_LOGIC_VECTOR (5 downto 0); clk : in STD_LOGIC;

latch : in STD_LOGIC; resetlatch : in STD_LOGIC);end component;

signal tempcountbus:std_logic_vector(5 downto 0);signal tempcounterreset,tempcounteroverflow:std_logic;signal templatchbus:std_logic_vector(5 downto 0);

signal templatch,tempresetlatch:std_logic;signal tempresetcounter_2:std_logic;signal tempcounter_2bus:std_logic_vector(1 downto 0);--signal tempredcomp0,tempredcomp1,tempredcomp2,tempgreencomp0,tempgreencomp1,tempgreencomp2,tempbluecomp0,tempbluecomp1,tempbluecomp2:std_logic;signal tempredbus,tempgreenbus,tempbluebus:std_logic_vector(1 downto 0);begin

stage_6bitcounter:counter_6bit PORT MAP(tempcounterreset,opampinput,clock,tempcounteroverflow,tempcountbus);stage_latch6bit:latch6bit PORT MAP(tempcountbus,templatchbus,clock,templatch,tempresetlatch);stage_2bitcounter:counter2bit PORT MAP(tempresetcounter_2,clock,tempcounter_2bus);tempredbus(0)<=templatchbus(0);tempredbus(1)<=templatchbus(3);

tempgreenbus(0)<=templatchbus(1);tempgreenbus(1)<=templatchbus(4);

tempbluebus(0)<=templatchbus(2);tempbluebus(1)<=templatchbus(5);

stage_red:comp2bit PORT MAP(tempredbus,tempcounter_2bus,redpin);stage_green:comp2bit PORT MAP(tempgreenbus,tempcounter_2bus,greenpin); stage_blue:comp2bit PORT MAP(tempbluebus,tempcounter_2bus,bluepin); stage_FSM:controlcircuit PORT MAP (opampinput,clock,tempcounteroverflow,templatch,tempcounterreset,switch,ofo,tempresetlatch,tempresetcounter_2);

end Behavioral;

------------------------------------------------------------------------------------ Company: -- Engineer: -- -- Create Date: 20:20:03 11/10/2011 -- Design Name: -- Module Name: counter_9bit - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: ---- Dependencies: ---- Revision: -- Revision 0.01 - File Created-- Additional Comments: ------------------------------------------------------------------------------------library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating---- any Xilinx primitives in this code.--library UNISIM;--use UNISIM.VComponents.all;

entity counter_6bit isPort ( reset : in STD_LOGIC; enb : in STD_LOGIC; clk : in STD_LOGIC; overflow : out STD_LOGIC;

c : out STD_LOGIC_VECTOR (5 downto 0));end counter_6bit;

architecture Behavioral of counter_6bit issignal tempcount:std_logic_vector(5 downto 0);begin process(reset,clk) begin

if (reset='1') then tempcount <= "000000"; elsif(rising_edge(clk) and enb='1') then if (tempcount="111111") then overflow<='1'; tempcount <= tempcount + "000001"; else tempcount <= tempcount + "000001"; overflow<='0'; end if; end if; end process;

c<= tempcount;end Behavioral;

------------------------------------------------------------------------------------ Company: -- Engineer: -- -- Create Date: 00:24:34 11/11/2011 -- Design Name: -- Module Name: latch9bit - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: ---- Dependencies: ---- Revision: -- Revision 0.01 - File Created-- Additional Comments: ------------------------------------------------------------------------------------library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating---- any Xilinx primitives in this code.--library UNISIM;--use UNISIM.VComponents.all;

entity latch6bit is Port ( a : in STD_LOGIC_VECTOR (5 downto 0); b : out STD_LOGIC_VECTOR (5 downto 0); clk : in STD_LOGIC;

latch : in STD_LOGIC; resetlatch : in STD_LOGIC);end latch6bit;

architecture Behavioral of latch6bit is

begin process(clk) begin

if rising_edge(clk) then if resetlatch='1' then b<="000000"; elsif latch='1' then b<=a;

end if;end if;

end process;

end Behavioral;

-- Create Date: 16:46:42 11/04/2011 -- Design Name: -- Module Name: counter3bit - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: ---- Dependencies: ---- Revision: -- Revision 0.01 - File Created-- Additional Comments: ------------------------------------------------------------------------------------library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating---- any Xilinx primitives in this code.--library UNISIM;--use UNISIM.VComponents.all;

entity counter2bit is Port ( reset : in STD_LOGIC; clock : in STD_LOGIC; count : out STD_LOGIC_VECTOR (1 downto 0));end counter2bit;

architecture Behavioral of counter2bit issignal tempc : std_logic_vector(1 downto 0);beginprocess(clock,reset)beginif reset='1' then tempc <="00";elsif rising_edge(clock) thentempc <= tempc + '1';end if;end process;count <= tempc;end Behavioral;

RTL of CompositeColorGeneration

SCHEMATICS

REFERENCES

BOOKS

Fundamentals of Digital Logic Design with VHDL By Stephen Brown & Zvonko Vranesic

Design and Applications of Analog Integrated Circuits By Sidney Scolof

WEBSITES

www.datasheet.com www.dataarchieve.com www.google.co.in www.xilinix.com