Vhdl lab manual
20
EXPERIMENT-1 Aim : Write a VHDL program to implement a multiplexer. (i) 4:1 Multiplexer : library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity mux4to1 is Port ( s : in STD_LOGIC_VECTOR (1 downto 0); a : in STD_LOGIC_VECTOR (3 downto 0); z : out STD_LOGIC); end mux4to1; architecture Behavioral of mux4to1 is begin process(s,a) begin if(s="00") then z<= a(0); elsif(s="01") then z<= a(1); elsif(s="10") then z<= a(2);
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Transcript of Vhdl lab manual
EXPERIMENT-1
Aim : Write a VHDL program to implement a multiplexer.
(i) 4:1 Multiplexer :
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity mux4to1 is
Port ( s : in STD_LOGIC_VECTOR (1 downto 0);
a : in STD_LOGIC_VECTOR (3 downto 0);
z : out STD_LOGIC);
end mux4to1;
architecture Behavioral of mux4to1 is
begin
process(s,a)
begin
if(s="00") then
z<= a(0);
elsif(s="01") then
z<= a(1);
elsif(s="10") then
z<= a(2);
else
z<= a(3);
end if;
end process;
end Behavioral;
OUTPUT :
(ii) 8:1 Multiplexer :
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity mux8to1 is
Port ( s : in STD_LOGIC_VECTOR (2 downto 0);
a : in STD_LOGIC_VECTOR (7 downto 0);
z : out STD_LOGIC);
end mux8to1;
architecture Behavioral of mux8to1 is
begin
process(s,a)
begin
if(s="000") then
z<= a(0);
elsif(s="001") then
z<= a(1);
elsif(s="010") then
z<= a(2);
elsif(s="011") then
z<= a(3);
elsif(s="100") then
z<= a(4);
elsif(s="101") then
z<= a(5);
elsif(s="110") then
z<= a(6);
else
z<= a(7);
end if;
end process;
end Behavioral;
OUTPUT :
EXPERIMENT-2
Aim : Write a VHDL program to implement a demultiplexer.
(i) 1:4 Demultiplexer :
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity demux1to4 is
Port ( s : in STD_LOGIC_VECTOR (1 downto 0);
i : in STD_LOGIC;
a : out STD_LOGIC_VECTOR (3 downto 0));
end demux1to4;
architecture Behavioral of demux1to4 is
begin
process(i,s)
begin
if(i='1') then
if(s="00") then
a<= "0001";
elsif(s="01") then
a<= "0010";
elsif(s="10") then
a<= "0100";
elsif(s="11") then
a<= "1000";
end if;
else
a<= "0000";
end if;
end process;
end Behavioral;
OUTPUT :
(ii) 1:8 Demultiplexer :
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity demux1to8 is
Port ( s : in STD_LOGIC_VECTOR (2 downto 0);
i : in STD_LOGIC;
a : out STD_LOGIC_VECTOR (7 downto 0));
end demux1to8;
architecture Behavioral of demux1to8 is
begin
process(i,s)
begin
if(i='1') then
if(s="000") then
a<= "00000001";
elsif(s="001") then
a<= "00000010";
elsif(s="010") then
a<= "00000100";
elsif(s="011") then
a<= "00001000";
elsif(s="100") then
a<= "00010000";
elsif(s="101") then
a<= "00100000";
elsif(s="110") then
a<= "01000000";
elsif(s="111") then
a<= "10000000";
end if;
else
a<= "00000000";
end if;
end process;
end Behavioral;
OUTPUT :
EXPERIMENT-3
Aim : Write a VHDL program to implement a 3:8 decoder.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity decoder3to8 is
Port ( i : in STD_LOGIC_VECTOR (2 downto 0);
en : in STD_LOGIC;
a : out STD_LOGIC_VECTOR (7 downto 0));
end decoder3to8;
architecture Behavioral of decoder3to8 is
begin
process(i,en)
begin
if(en='1') then
if(i="000") then
a<= "00000001";
elsif(i="001") then
a<= "00000010";
elsif(i="010") then
a<= "00000100";
elsif(i="011") then
a<= "00001000";
elsif(i="100") then
a<= "00010000";
elsif(i="101") then
a<= "00100000";
elsif(i="110") then
a<= "01000000";
elsif(i="111") then
a<= "10000000";
end if;
else
a<= "00000000";
end if;
end process;
end Behavioral;
OUTPUT :
EXPERIMENT-4
Aim: Write a VHDL program to implement a 4 bit adder.
--program for 1 bit full adder.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity fa is
Port ( x : in STD_LOGIC;
y : in STD_LOGIC;
c : in STD_LOGIC;
s : out STD_LOGIC;
co : out STD_LOGIC);
end fa;
architecture Behavioral of fa is
begin
s<= x xor y xor c;
co<= (x and y)or(y and c)or(c and x);
end Behavioral;
--program for 4 bit full adder.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity fa_4bit is
Port ( a : in STD_LOGIC_VECTOR (3 downto 0);
b : in STD_LOGIC_VECTOR (3 downto 0);
cin : in STD_LOGIC;
sum : out STD_LOGIC_VECTOR (3 downto 0);
cout : out STD_LOGIC);
end fa_4bit;
architecture Structural of fa_4bit is
signal cs : std_logic_vector (2 downto 0);
component fa
port (x : in STD_LOGIC;
y : in STD_LOGIC;
c : in STD_LOGIC;
s : out STD_LOGIC;
co : out STD_LOGIC);
end component;
begin
f1 : fa port map(a(0),b(0),cin,sum(0),cs(0));
f2 : fa port map(a(1),b(1),cs(0),sum(1),cs(1));
f3 : fa port map(a(2),b(2),cs(1),sum(2),cs(2));
f4 : fa port map(a(3),b(3),cs(2),sum(3),cout);
end Structural;
OUTPUT :
EXPERIMENT-5
Aim: Write a VHDL program to implement a 4 bit comparator.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity comprator_4bit is
Port ( a : in STD_LOGIC_VECTOR (3 downto 0);
b : in STD_LOGIC_VECTOR (3 downto 0);
less : out STD_LOGIC;
equal : out STD_LOGIC;
greater : out STD_LOGIC);
end comprator_4bit;
architecture Behavioral of comprator_4bit is
begin
process(a,b)
begin
if (a>b) then
greater <= '1';
equal <= '0';
less <= '0';
elsif (a<b) then
greater <= '0';
equal <= '0';
less <= '1';
else
greater <= '0';
equal <= '1';
less <= '0';
end if;
end process;
end Behavioral;
OUTPUT :
EXPERIMENT-6
Aim: Write a VHDL program to design a 2 bit ALU containing 4
arithmetic and 4 logical operations.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity alu_2bit is
Port ( a : in STD_LOGIC_VECTOR (1 downto 0);
b : in STD_LOGIC_VECTOR (1 downto 0);
sel : in STD_LOGIC_VECTOR (2 downto 0);
cin : in STD_LOGIC;
y : out STD_LOGIC_VECTOR (1 downto 0));
end alu_2bit;
architecture Behavioral of alu_2bit is
signal arith,logic : STD_LOGIC_VECTOR (1 downto 0);
begin
with sel(1 downto 0) select
arith <= a + 1 when "00",
a + b + cin when "01",
a - b when "10",
b + 1 when others;
with sel(1 downto 0) select
logic <= not a when "00",
a and b when "01",
a or b when "10",
a xor b when others;
with sel(2) select
y <= arith when '0',
logic when others;
end Behavioral;
OUTPUT :
EXPERIMENT-7
Aim: Write a VHDL program to design a D Flip Flop.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity dff is
Port ( d,clk, reset: in std_logic;
q : out std_logic);
end dff;
architecture Behavioral of dff is
begin
process (clk, d)
begin
if ( (d'event or clk'event) and clk='1') then
if RESET ='1' then
q <= '0' ;
else
q <= d after 1 us;
end if;
end if;
end process;
end Behavioral;
OUTPUT :
EXPERIMENT-8
Aim: Write a VHDL program to design a D Flip Flop.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity dff is
Port ( d,clk, reset: in std_logic;
q : out std_logic);
end dff;
architecture Behavioral of dff is
begin
process (clk, d)
begin
if ( (d'event or clk'event) and clk='1') then
if RESET ='1' then
q <= '0' ;
else
q <= d after 1 us;
end if;
end if;
end process;
end Behavioral;
OUTPUT :
