Verilog Problems
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VERILOG PROBLEMS (CAD for VLSI) Problem 1 : (i) Design a single-bit full adder module. (ii) Design a four-bit adder using such four full adders (as designed above). Problem 2 : Design a priority arbiter (see the above figure) having following features: (i) Priority of ‘req1’ is higher than the priority of ‘req2’; i.e., whenever ‘req1’ is high, ‘gnt1’ goes high in the next positive edge of the ‘clk’. (ii) Whenever ‘req1’ is low and ‘req2’ is high, ‘gnt2’ goes high in the next positive edge of the ‘clk’. (iii) When no requests are given, then both ‘gnt1’ and ‘gnt2’ remains low in next ‘clk’. (iv) Make sure that your design should make ‘gnt1’ and ‘gnt2’ mutually exclusive. (v) Use ‘rst’ signal to initialize your circuit and initially ‘gnt1’ and ‘gnt2’ must remain low. [ Hint: First build an FSM of the arbiter and then try to code that within a module ] Now try to design a suitable test bench for this priority arbiter. Full Adder Full Adder Full Adder Full Adder A0 B0 A1 B1 A2 B2 A3 B3 carry_out carry_in S0 S1 S2 S3 PRIORITY ARBITER req1 req2 rst clk gnt1 gnt2
description
verilog questions
Transcript of Verilog Problems
VERILOG PROBLEMS (CAD for VLSI) Problem 1:
(i) Design a single-bit full adder module. (ii) Design a four-bit adder using such four full adders (as designed above).
Problem 2:
Design a priority arbiter (see the above figure) having following features:
(i) Priority of ‘req1’ is higher than the priority of ‘req2’; i.e., whenever ‘req1’ is high, ‘gnt1’ goes high in the next positive edge of the ‘clk’.
(ii) Whenever ‘req1’ is low and ‘req2’ is high, ‘gnt2’ goes high in the next positive edge of the ‘clk’.
(iii) When no requests are given, then both ‘gnt1’ and ‘gnt2’ remains low in next ‘clk’.
(iv) Make sure that your design should make ‘gnt1’ and ‘gnt2’ mutually exclusive. (v) Use ‘rst’ signal to initialize your circuit and initially ‘gnt1’ and ‘gnt2’ must
remain low. [ Hint: First build an FSM of the arbiter and then try to code that within a module ] Now try to design a suitable test bench for this priority arbiter.
Full Adder
Full Adder
Full Adder
Full Adder
A0 B0 A1 B1 A2 B2 A3 B3
carry_out
carry_in
S0 S1 S2 S3
PRIORITY ARBITER
req1
req2
rst
clk
gnt1
gnt2
Problem 3:
gh ‘initial’ block provided in Verilog.
Hint: For example, suppose the bit-stream is 100110.
Design a circuit which senses a bit-stream (one bit in every clock), and in every clock, it
MODULO-3 CIRCUIT
bit-stream remainder
clk
produces the remainder by dividing the numerical value of the bit-stream (scanned up to that clock) by three (i.e., bit-stream value % 3).
Also, initialize the remainder as 00 throu
[ Clock passed bit-stream scanned remainder-output 1 1 1 (as 12 = 110 & 1%3 = 1)
Try to build the FSM and design the FSM module in Verilog ]
roblem 4
2 10 2 (as 102 = 210 & 2%3 = 2) 3 100 1 (as 1002 = 410 & 4%3 = 1) 4 1001 0 (as 10012 = 910 & 9%3 = 0)…….. etc ……………………etc…………………………..etc……………………………
P :
× 8 bit RAM having asynchronous read and synchronous write capability. .
roblem 5
Design a 256When rw = 1, read operation is performed and when rw = 0, write operation is performed
P :
t Grey Counter. The count starts with ‘reset’ signal and the grey counter al
Hint: In a grey counter, the present and next binary value of the count differs only in
01 11 10 00 … ]
Design a 3-bicounts when ‘enable’ signal remains high and it stops counting whenever ‘enable’ signgoes low. [ one bit position.
For example, the 2-bit grey counter counts as: 00
256 × 8 bit RAM
address
data rw
clk
Practice Examples (Try Youself):
1. Ring Counter, Johnson Counter.
isting of Master, Slave and Arbiter Module. er each and the
b. ber
2. GCD Calculator. 3. Bus Protocol cons
a. First try to build individual FSM for master, slave, arbitcode them. Later, place three modules together in a top module. Increase complexity of the design gradually by increasing the numof master and slave modules.
