Verilog module new rev a
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Jim Duckworth, WPI Verilog Module Rev A1
Verilog
Verilog for Synthesis
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Jim Duckworth, WPI Verilog Module Rev A2
Verilog background
• 1983: Gateway Design Automation released Verilog HDL
“Verilog” and simulator
• 1985: Verilog enhanced version – “Verilog-XL”
• 1987: Verilog-XL becoming more popular (same year
VHDL released as IEEE standard)
• 1989: Cadence bought Gateway
• 1995: Verilog adopted by IEEE as standard 1364
– Verilog HDL, Verilog 1995
• 2001: First major revision (cleanup and enhancements)
– Standard 1364-2001 (or Verilog 2001)
• System Verilog under development
– Better system simulation and verification support
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Jim Duckworth, WPI Verilog Module Rev A3
Books
• “Starters Guide to Verilog 2001” by Ciletti, 2004, Prentice Hall 0-13-141556-5
• “Fundamentals of Digital Logic with Verilog Design” by Brown and Vranesic, 2003, McGraw-Hill, 0-07-282878-7
• “Modeling, Synthesis, and Rapid Prototyping with the Verilog HDL”, by Ciletti, 1999, Prentice-Hall, 0-13-977398-3
• “Advanced Digital Design with the Verilog HDL”, by Ciletti, 2003, Prentice-Hall, 0-13-089161-4
• “HDL Chip Design” by Smith, 1996, Doone Publications, 0-9651934-8
• “Verilog Digital Design” by Arnold, 1999, Prentice Hall, 0-13-639253-9
• “Verilog Styles for Synthesis of Digital Systems” by Smith and Franzon, 2000, Prentice Hall, 0-201-61860-5
• “Verilog HDL” by Palnitkar”, 2003, Prentice Hall, 0-13-044911-3
• “Verilog for Digital Design” by Vhadi and Lysecky, 2007, Wiley, 978-0-470-05262-4
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Jim Duckworth, WPI Verilog Module Rev A4
Create Verilog Module
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Jim Duckworth, WPI Verilog Module Rev A5
Module Created
• No separate entity and arch –
just module
• Ports can be input, output, or
inout
• Note: Verilog 2001 has
alternative port style:– (input a, b, sel, output y);
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Jim Duckworth, WPI Verilog Module Rev A6
Add assign statement
• Similar to VHDL conditional signal assignment – continuous assignment
• Same hardware produced as with VHDL
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Jim Duckworth, WPI Verilog Module Rev A7
Verilog - general comments
• VHDL is like ADA and Pascal in style
• Strongly typed – more robust than Verilog
• In Verilog it is easier to make mistakes
• Watch for signals of different widths
• No default required for case statement, etc
• Verilog is more like the ‘c’ language
• Verilog IS case sensitive
• White space is OK
• Statements terminated with semicolon (;)
• Verilog statements between
• module and endmodule
• Comments // single line and /* and */
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Jim Duckworth, WPI Verilog Module Rev A8
Verilog
• Four-value logic system
• 0 – logic zero, or false condition
• 1 – logic 1, or true condition
• x, X – unknown logic value
• z, Z - high-impedance state
• Number formats
• b, B binary
• d, D decimal (default)
• h, H hexadecimal
• o, O octal
• 16’H789A – 16-bit number in hex format
• 1’b0 – 1-bit
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Jim Duckworth, WPI Verilog Module Rev A9
Verilog types
• Constants– parameter DIME = 10;
– parameter width = 32, nickel = 5;
– parameter quarter = 8’b0010_0101;
• Nets– wire clock, reset_n;
– wire[7:0] a_bus;
• Registers– reg clock, reset_n;
– reg[7:0] a_bus;
• Integer
– only for use as general purpose variables in loops
– integer n;
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Jim Duckworth, WPI Verilog Module Rev A10
Operators
• Bitwise– ~ negation Verilog VHDL
– & and y = a & b; y = a AND b;
– | inclusive or y = a | b; y = A OR b;
– ^ exclusive or y = a ^ b; y = a XOR b;
– y = ~(a & b); y = A NAND b;
– y = ~ a; y = NOT a;
• Reduction (no direct equivalent in VHDL)
– Accept single bus and return single bit result
• & and y = & a_bus;
• ~& nand
• | or y = | a_bus;
• ^ exclusive or
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Jim Duckworth, WPI Verilog Module Rev A11
Operators (cont’d)
• Relational (return 1 for true, 0 for false)– < less than, <=
– > greater than >=
• Equality– == logical equality
– != logical inequality
• Logical Comparison Operators– ! logical negation
– && logical and
– || logical or
• Arithemetic Operators– +
– -
– *
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Jim Duckworth, WPI Verilog Module Rev A12
Operators (cont’d)
• Shift– << logical shift left, (<<< arithmetic)
– >> logical shift right (>>> arithmetic)
• Conditional
– Only in Verilog - selects one of pair expressions
– ? :
– Logical expression before ? is evaluated
– If true, the expression before : is assigned to output
– If false, expression after : is assigned to output
• Y = (A > B) ? 1 : 0
• Y = (A == B) ? A + B : A – B
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Jim Duckworth, WPI Verilog Module Rev A13
Tri-state example
• Using conditional operator in continuous assignment
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Jim Duckworth, WPI Verilog Module Rev A14
Concurrent statements
• VHDL
– Process
– Signal assignments
• Verilog
– always statement
– Continuous assignment - assign
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Jim Duckworth, WPI Verilog Module Rev A15
Sequential Statements
• VHDL
– reside in process statement
• Verilog
– reside in an always statement
– if statements
– case statements
– Note: use begin and end to block sequential statements
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Jim Duckworth, WPI Verilog Module Rev A16
Verilog wire and register data objects
• Wire – net, connects two signals together
– wire clk, en;
– wire [15:0] a_bus;
• Reg – register, holds its value from one procedural
assignment statement to the next
– Does not imply a physical register – depends on use
– reg [7:0] b_bus;
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Jim Duckworth, WPI Verilog Module Rev A17
Index and Slice
• VHDL
– Use to and downto to specify slice
– Concatenation &• c_bus(3 downto 0) <= b_bus(7 downto 4);
• c_bus(5 downto 0) <= b_bus(7) & a_bus(6 downto 3) & ‘0’;
• Verilog
– Use colon :
– Concatenation {,}• assign c_bus[3:0] = b_bus[7:4];
• assign c_bus[5:0] = {b_bus[7], a_bus[6:3], 1’b0};
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Jim Duckworth, WPI Verilog Module Rev A18
Internal wires
• Declare internal wires:
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Jim Duckworth, WPI Verilog Module Rev A19
Decoder
• 2 to 4 decoder with enable
• Combinational logic using always statement with sensitivity list
– similar to VHDL process – for cyclic behavior
– (@) event control operator
– begin .. end block statement
– note reg for y
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Jim Duckworth, WPI Verilog Module Rev A20
Decoder (cont’d)
• Combinational logic using always statement with
sensitivity list
– similar to VHDL process – for cyclic behavior
– (@) event control operator
– begin .. end block statement
• Statements execute sequentially
– if statement
– case statement
• Note: case expression can concatenate signals ({,})
– Sensitivity list
• (a or b or c)
• Verilog 2001 allows comma-separated list (a, b, c)
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Jim Duckworth, WPI Verilog Module Rev A21
Flip-flops in Verilog
• Always inferred using edge-triggered always statement
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Jim Duckworth, WPI Verilog Module Rev A22
Flip-flops in Verilog (with async)
• Add async signals to sensitivity list
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Jim Duckworth, WPI Verilog Module Rev A23
Counters in Verilog
• Just extension of D type
• This example has async clear
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Jim Duckworth, WPI Verilog Module Rev A24
Counters in Verilog (cont’d)
• With terminal count
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Jim Duckworth, WPI Verilog Module Rev A25
State Machine
• SM1 – 4 states
• Two always statements
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Jim Duckworth, WPI Verilog Module Rev A26
State Machine hardware
• four flip-flops (can be changed through synthesis options)
• Combinational logic for next state and outputs
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Jim Duckworth, WPI Verilog Module Rev A27
Blocking and non-blocking assignment
• To ensure correct synthesis and simulation results:
• Combinational logic
– Use blocking assignment = statements in always block
• Sequential logic
– Use non blocking assignment <= statements in always block
– Can only be used on reg types
• Can only be used in an initial or always procedural blocks
– Can not be used in continuous assignments
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Jim Duckworth, WPI Verilog Module Rev A28
Top-Down Design Hierarchy
• Instantiate module (counter example with decoder)module decoder(count,seven_seg);
input [3:0] count;
output [6:0] seven_seg;
// instantiate decoder module in counter
// using position of ports
decoder d1 (count_val, seven_seg_val);
// or using formal and actual names
decoder d1 (.count(count_val), .seven_seg(seven_seg_val));
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Jim Duckworth, WPI Verilog Module Rev A29
Decoder Test Fixture Example
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Jim Duckworth, WPI Verilog Module Rev A30
Create Verilog Test Fixture
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Jim Duckworth, WPI Verilog Module Rev A31
Test Fixture Created
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Jim Duckworth, WPI Verilog Module Rev A32
Add Stimulus
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Jim Duckworth, WPI Verilog Module Rev A33
Simulation Results
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Jim Duckworth, WPI Verilog Module Rev A34
Simulation Notes
• Initial block declares a single-pass behavior
– Executes once when simulator is activated
• Delay control operator (#) and delay value - #10
• Timescale compiler directive
– timescale <reference_time_unit>/<time_precision>
– `timescale 10ns/1ns
• Inputs are declared as reg values – retains value until
updated
• Outputs are just monitored as wires
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Jim Duckworth, WPI Verilog Module Rev A35
Generating clocks
• Generating repetitive signalsinitial
begin
clk = 0;
end
always
begin
#5 clk = ~clk;
end
• Oralways
begin
#5 clk = 0;
#5 clk = 1;
end