Verilog HDL (Behavioral Modeling) Bilal Saqib. Behavioral Modeling.
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Transcript of Verilog HDL (Behavioral Modeling) Bilal Saqib. Behavioral Modeling.
Verilog HDLVerilog HDL(Behavioral Modeling)(Behavioral Modeling)
Bilal Saqib
Behavioral ModelingBehavioral Modeling
Structured ProceduresStructured Procedures
Procedural BlocksProcedural Blocks
Procedural Blocks are constructed from the following components.◦Procedural Assignment Statements◦High-Level Constructs
Procedural AssignmentsProcedural Assignments
Procedural Execution ControlProcedural Execution Control
Execution of Procedural Blocks can be specified in different ways◦Simple Delays: #<delay>
Specify delay before and after execution for a number of time steps.
◦Edge-Sensitive Controls: always @ (<edge><signal>) Execution occurs only at a signal edge. Optional
keywords “posedge” or “negedge” can be used to specify signal edge for execution.
NonBlocking v Blocking NonBlocking v Blocking AssignmentsAssignments
NonBlocking v Blocking NonBlocking v Blocking AssignmentsAssignments
Conditional Statements: if elseConditional Statements: if else
Conditional Statements: caseConditional Statements: case
casex and casezcasex and casez
Looping Statements: repeat
Looping Statements: while
Looping Statements: forever
Looping Statements: for