Veljko Milutinović [email protected] Saša Stojanović [email protected] University of Belgrade 1.

19
Veljko Milutinović [email protected] Saša Stojanović [email protected] University of Belgrade 1

Transcript of Veljko Milutinović [email protected] Saša Stojanović [email protected] University of Belgrade 1.

Page 1: Veljko Milutinović vm@etf.rs Saša Stojanović stojsasa@etf.rs University of Belgrade 1.

Veljko Milutinović[email protected]

Saša Stojanović[email protected]

University of Belgrade1

Page 2: Veljko Milutinović vm@etf.rs Saša Stojanović stojsasa@etf.rs University of Belgrade 1.

DualCore?

Where are the horses going?

2

Page 3: Veljko Milutinović vm@etf.rs Saša Stojanović stojsasa@etf.rs University of Belgrade 1.

Is it possibleto use 2000 chicken instead of two horses?

?==

3

Page 4: Veljko Milutinović vm@etf.rs Saša Stojanović stojsasa@etf.rs University of Belgrade 1.

2 x 1000 chickens 4

Page 5: Veljko Milutinović vm@etf.rs Saša Stojanović stojsasa@etf.rs University of Belgrade 1.

How about 2 000 000 ants?

5

Dat

a

Page 6: Veljko Milutinović vm@etf.rs Saša Stojanović stojsasa@etf.rs University of Belgrade 1.

Marmalade

Big Data Input Results

6

Page 7: Veljko Milutinović vm@etf.rs Saša Stojanović stojsasa@etf.rs University of Belgrade 1.

Factor: 20 to 200

MultiCore/ManyCore

DataFlow

Machine Level Code

Gate Transfer Level

7

Page 8: Veljko Milutinović vm@etf.rs Saša Stojanović stojsasa@etf.rs University of Belgrade 1.

Factor: 20

MultiCore/ManyCore

DataFlow

8

P = C*U2*f

Page 9: Veljko Milutinović vm@etf.rs Saša Stojanović stojsasa@etf.rs University of Belgrade 1.

Factor: 20

Data Processing

Process ControlData Processing

Process Control

MultiCore/ManyCore

DataFlow

9

20

1

20

1

Page 10: Veljko Milutinović vm@etf.rs Saša Stojanović stojsasa@etf.rs University of Belgrade 1.

MultiCore:Explain what to do, to the driverCaches, instruction buffers, and predictors needed

ManyCore:Explain what to do, to many sub-driversReduced caches and instruction buffers needed

DataFlow:No caches, instruction buffers, or predictors

needed: Cmin

Make a field of processing gates: +5 Java programs10

Page 11: Veljko Milutinović vm@etf.rs Saša Stojanović stojsasa@etf.rs University of Belgrade 1.

MultiCore:Business as usual

ManyCore:More difficult

DataFlow:Much more difficultDebugging both, application and configuration

code: 5 Java + Cmin

11

Page 12: Veljko Milutinović vm@etf.rs Saša Stojanović stojsasa@etf.rs University of Belgrade 1.

MultiCore/ManyCore:Several minutes

DataFlow:Several hours (to configure the FPGA

structures)Future: Xilinx, Altera,

Achronix (UCB 1GHz), Tabula (MIT, 1.6GHz)

12

Page 13: Veljko Milutinović vm@etf.rs Saša Stojanović stojsasa@etf.rs University of Belgrade 1.

13

Page 14: Veljko Milutinović vm@etf.rs Saša Stojanović stojsasa@etf.rs University of Belgrade 1.

MultiCore:Horse stable

ManyCore:Chicken house

DataFlow:Ant hole

14

Page 15: Veljko Milutinović vm@etf.rs Saša Stojanović stojsasa@etf.rs University of Belgrade 1.

MultiCore:Haystack

ManyCore:Cornbits

DataFlow:Crumbs

15

Page 16: Veljko Milutinović vm@etf.rs Saša Stojanović stojsasa@etf.rs University of Belgrade 1.

16

Small Data

Page 17: Veljko Milutinović vm@etf.rs Saša Stojanović stojsasa@etf.rs University of Belgrade 1.

17

Medium Data

Page 18: Veljko Milutinović vm@etf.rs Saša Stojanović stojsasa@etf.rs University of Belgrade 1.

18

Big Data

Page 19: Veljko Milutinović vm@etf.rs Saša Stojanović stojsasa@etf.rs University of Belgrade 1.

19