Vedic Algorithms to develop green chips for future

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Abstract The speed of ALU depends greatly on the multiplier,

Vedic Mathematics is the ancient system of mathematics which

has a unique technique of calculations based on 16 Sutras. Em-

ploying these techniques in the computation algorithms of the

coprocessor will reduce the complexity, execution time, area,

power.

Keywords-Vedic Multiplier, Urdhva Tiryambakam, ALU

I. INTRODUCTION

In any processor the major units are Control Unit, ALUand Memory read write. Among these units the perfor-

mance of any processor majorly depends on the time

taken by the ALU to perform the specified operation.

Multiplication is an important fundamental function in

arithmetic operations. Multiplication-based operations

such as Multiply and Accumulate (MAC) and inner

product are among some of the frequently used Com-

putation Intensive Arithmetic Functions (CIAF) cur-

rently implemented in many Digital Signal Pro-

cessing (DSP) applications such as convolution, Fast

Fourier Transform (FFT), filtering and in microproces-sors in its arithmetic and logic unit. Since multiplica-

tion dominates the execution time of most DSP algo-

rithms, so there is a need of high speed multiplier.

The demand for high speed processing has been in-

creasing as a result of expanding computer and signal

processing applications. Higher throughput arithmetic

operations are important to achieve the desired perfor-

mance in many real-time signal and image processing

application. One of the key arithmetic operations in

such applications is multiplication and the development

of fast multiplier circuit has been a subject of interestover decades. Reducing the time delay and power con-

sumption are very essential requirements for many ap-

plications. This work presents different multiplier ar-

chitectures. Multiplier based on Vedic Mathematics is

one of the fast and low power multiplier.

Digital multipliers are the most commonly used com-

ponents in any digital circuit design. They are fast, reli-

able and efficient components that are utilized to im-

plement any operation. Depending upon the ar-

rangement of the components, there are different

types of multipliers available. Particular multiplier ar-chitecture is chosen based on the application.

In many DSP algorithms, the multiplier lies in the criti-

cal delay path and ultimately determines the perfor-

mance of algorithm. The speed of multiplication opera-

tion is of great importance in DSP as well as in general

processor. In the past multiplication was implemented

generally with a sequence of addition, subtraction

and shift operations. There have been many algorithms

proposals in literature to perform multiplication, each

offering different advantages and having tradeoff interms of speed, circuit complexity, area and power con-

sumption.

The multiplier is a fairly large block of a computing

system. The amount of circuitry involved is directly

proportional to the square of its resolution i.e. A multi-

plier of size n bits has n2 gates. For multiplication al-

gorithms performed in DSP applications latency and

throughput are the two major concerns from delay per-

spective. Latency is the real delay of computing a func-

tion, a measure of how long the inputs to a device are

stable is the final result available on outputs. Multiplieris not only a high delay block but also a major source

of power dissipation. Thats why if one also aims to

minimize power consumption, it is of great interest to

reduce the delay by using various delay optimizations.

In this thesis work, Urdhva tiryakbhyam Sutra is first

applied to the binary number system and is used to de-

velop digital multiplier architecture. This is shown to

be very similar to the popular array multiplier ar-

chitecture. This Sutra also shows the effectiveness

of to reduce the NxN multiplier structure into an effi-

cient 2x2 multiplier structures. Nikhilam Sutra is then

discussed and is shown to be much more efficient in

the multiplication of large numbers as it reduces the

multiplication of two large numbers to that of two

smaller ones. The proposed multiplication algorithm is

then illustrated to show its computational efficiency by

taking an example of reducing a 4x4-bit multiplication

to a single 2x2-bit multiplication operation. This work

presents a systematic design methodology for fast and

area efficient digit multiplier based on Vedic mathe-

matics. The Multiplier Architecture is based on the

Vertical and Crosswise algorithm of ancient IndianVedic Mathematics.

Vedic Algorithms to develop green chips for future

Soma BhanuTej

International Institute of Information Technology

(MT-MVD,SOST dept)

Pune,India

email: [email protected]

International Journal ofSystems , Algorithms &

ApplicationsIIIIJJJJSSSSAAAA AAAA

Volume 2, Issue ICAEM12, February 2012, ISSN Online: 2277-2677 1

ICAEM12|Jan20,2012|Hyderabad|India


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II. OBJECTIVE

The main objective of this thesis is to design and synthe-

sis of a ALU, which can be used in any processor appli-

cation. This thesis deals with the study, design and syn-

thesis of ALU using Vedic multiplier. In this thesis

work, study of Vedic multiplication algorithms has

been explored. Synthesis and Static timing analysis

(STA) of this ALU has been done on RC compiler.

III.VEDIC MULTIPLICATION

The proposed Vedic multiplier is based on the Vedic

multiplication formulae (Sutras). These Sutras have been

traditionally used for the multiplication of two numbers

in the decimal number system. In this work, we apply

the same ideas to the binary number system to make the

proposed algorithm compatible with the digital hard-

ware. Vedic multiplication based on some algorithms, is

discussed below

A. Urdhva Tiryakbhyam Sutra

The multiplier is based on an algorithm Urdhva Tiryak-

bhyam (Vertical & Crosswise) of ancient Indian Vedic

Mathematics. Urdhva Tiryakbhyam Sutra is a gen-

eral multiplication formula applicable to all cases of

multiplication. It literally means Vertically and cross-

wise. It is based on a novel concept through which

the generation of all partial products can be done and

then, concurrent addition of these partial products can be

done. Thus parallelism in generation of partial products

and their summation is obtained using Urdhava Tiryak-

bhyam. The algorithm can be generalized for n x n bitnumber. Since the partial products and their sums are

calculated in parallel, the multiplier is independent of

the clock frequency of the processor. Thus the multiplier

will require the same amount of time to calculate the

product and hence is independent of the clock frequen-

cy. The net advantage is that it reduces the need of mi-

croprocessors to operate at increasingly high clock fre-

quencies. While a higher clock frequency generally re-

sults in increased processing power, its disadvantage is

that it also increases power dissipation which results in

higher device operating temperatures. By adopting the

Vedic multiplier, microprocessors designers can easilycircumvent these problems to avoid catastrophic device

failures. The processing power of multiplier can easily

be increased by increasing the input and output data bus

widths since it has a quite a regular structure. Due to its

regular structure, it can be easily layout in a silicon chip.

The Multiplier has the advantage that as the number of

bits increases, gate delay and area increases very slowly

as compared to other multipliers. Therefore it is time,

space and power efficient. It will enhance the ALU unit

also. As a result the mathematical operations which

employs multiplication is demonstrated that this archi-

tecture is quite efficient in terms of silicon area/speed.

IV. ALU

The ALU is built with Vedic Multiplier Hence the ad-

vantages of Vedic multiplier

like

1. Increase in speed

2. Decrease in delay

3. Decrease in area

4. Decrease in power consumption

unit, will have efficient computing in terms of speed,

delay and complexity.

A. Equations

The equations for a 4x4 Vedic multiplier are

TABLE 1 VEDICAND CONVECTIONAL MULTIPLIER

TABLE II CONVENTIONALAND VEDIC ALU

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VI. SIMULATION RESULTS

Fig 1. Simulation Result of 8-bit ALU using Vedic Multiplication

V. CONCLUSION

Udrhva Tiryakbhayam Sutra is highly efficient algo-

rithm for multiplication.

ACKNOWLEDGEMENTI thank my guide Prof. Bhushan Patil for his guidance

throughout the project and Prof. Rabinder Henry Head ofSOST, I2IT, Pune for encouragement and invaluable supportthroughout the work.

REFERENCES[1] Jagadguru Swami Sri Bharati Krishna Tirthji Maharaja,Vedic

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[4] Shamim Akhter, VHDL Implementation of Fast X Multiplier

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