VDK and HAPS

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SNUG 2014 1 VDK and HAPS Synopsys Hybrid platform Decreasing your T2M by enabling early software design Uri Shkolnik Zoro Solutions Ltd. June 2014 SNUG Israel

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VDK and HAPS. Synopsys Hybrid platform Decreasing your T2M by enabling early software design. Uri Shkolnik Zoro Solutions Ltd. June 2014 SNUG Israel. Agenda. About Zoro E xperience using Virtualizer VDK for ROM development DW_USB3 driver virtualization and emulation - PowerPoint PPT Presentation

Transcript of VDK and HAPS

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VDK and HAPSSynopsys Hybrid platform

Decreasing your T2M by enabling early software design

Uri ShkolnikZoro Solutions Ltd.

June 2014SNUG Israel

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Agenda

About Zoro

Experience using Virtualizer VDK for ROM development

DW_USB3 driver virtualization and emulation

Experience deploying Hybrid prototyping VDK↔HAPS

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About Zoro

Pre-Silicon Software development– Software development using simulation (using tools by

Synopsys, and additional EDA companies).– Emulation, virtual and hybrid platforms (HAPS, Virtualizer

VDK, others)– Software ASIC verification – Proven experience with ARC, ARM, CEVA, MIPS, Tensilica– ROM development, including RTOS, USB, SDIO, Security

(boot, authentication) and additional ROM stacks• Zoro offers turnkey projects, outsourcing and

consulting• Synopsys Partner (Virtual Prototyping, ARC, DW IP)

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SoC Design Efforts – Past and Present

1998 2005 20120

2

4

6

8

10

12

Embedded Software : VLSI VLSI Embedded SW

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Design Launch RTL FreezeMain cores ready

Traditional SoC Design Approach

FPGA Emulation ready

SoC Arrival

VLSI

SW

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Design Launch RTL FreezeMain cores ready

T2M SoC Design Approach

VLSI

SW

VDK Ready HAPS Ready

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Based on a True Story…..

• Israeli Fabless Company– SoC Design Start, ARM Cortex w/USB3.0 – Dec 12– Hardware prototype (FPGA which contains ARM, USB3, memories,

UART), to be ready by Mar. 13 (halted, NC)– Emulation, took long time and many efforts, single resource for both

VLSI & SW, unsuitable for many software tasks – Summer 13– Decision to deploy Virtualizer VDK, bare metal – Sep 13 (SW

engineers only)– Decision to deploy Virtualizer VDK & HAPS USB3, bare metal and

Linux – Dec 13 (done by SW engineers only). Platform runs Linux with good speed

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VDK

Memory 1(DDR3)

AXI

Memory 0(SRAM)

USB Controller

ARM CortexINTC

UART

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Software Developer’s View

Virtualizer Developer Kit (VDK)Simulation of a hardware device/SoC*

Lauterbach GDB/DDD ARM DS-5/RVDS

Virtualizer Multi-core Debugger Server

ARM Cortex A

USB

MMC

I2C/SPI

GMAC

LCD

*Simulation using industry standard based Transaction Level Models (TLM)

ARM Cortex R

ARM Cortex M

Host USB

Host MMC

Sensors, etc.

Ethernet

Touch panel

Virtual IO

Synopsys System SW Debug

Instant, OS-aware, non-intrusive, stop mode debugging

Unmodified binary SW stack imagesE.g. bootROM + Linux kernel + Linux filesystem

Simulation & Debug Scripting

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Synopsys Tools for VDKsVisibility beyond traditional software debugging

Explore platform

Inspect registers & signals

Break on signals, registers, SW,

screen contents

Script everything

Extend through scripting

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Vertical HW/SW integration: Middleware & DriversMulti-layer, multi-core, multi-tool SW debugging

Stopmode

Stopmode

GDB:Sensor middleware – Cortex A

GDB:Sensor driver – Cortex A

VP Linux awareness plugin

Kernel Symbols - vmlinuxSymbols libsensors.so

Statically loadedDynamically loaded

Virtualizer Multi-core Debugger Server

Firmware symbols

Lauterbach:Sensor firmware– Cortex M

Statically loaded

Stopmode

See article: Android hardware/software design using virtual prototypeshttp://www.embedded.com/design/prototyping-and-development/4399520

One click connection of a debugger to any thread, on any core, in any SW layer, in non-intrusive stop-mode !

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From VDK to Hybrid VDK-HAPSARM Cortex A5 w/ DW-USB3 SoCOS-less ROM and Embedded Linux Firmware

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VDK

Memory 1(DDR3)

AXI

Memory 0(SRAM)

USB Controller

ARM CortexINTC

UART

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Hybrid (VDK + HAPS)

AXIAXI

USB Controller

ARM CortexINTC

Memory 1(DDR3)

Memory 0(SRAM) UART

UMRBus

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Popular ASIC Prototyping Methods

Certify Synplify Premier Identify

SynopsysHAPS

Systems

FPGA-Based (RTL)Virtual (Pre RTL)

ASICRTL

SystemC/TLM

Project Timeline

Synopsys Virtual Prototype

Software Stack

SynopsysVirtualizer

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Integrated Hybrid Prototyping SolutionBest of Both Worlds

Synopsys Hybrid Prototype Solution

VirtualizerSystemC/TLM–based

virtual prototype

Start software development before hardware is available

HAPS SystemsFPGA-based ASIC prototype

Validate HW/SW operation at near real-time speed

Interconnect

GPIOs

UARTs

Keyboard /

Mouse Interfac

e

Color LCD

ControllerEmbedde

d memories

Timers

Generic Interrupt Controller

Generic Battery

Cortex-A7 MPCore

L2 cache controller

RTC

Watchdog Interface

Cortex-A15 MPCore

DesignWareEthernet

DesignWareUSB 3.0

UMRBus

AMBA

Data Exchange

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The Hybrid prototyping:Solution Strengths 1. Virtualization enables rapid setup, simple development

and debugging2. FPGA enables high confidentiality with RTL/IP.3. The Hybrid setup eases software design comparing to

simulation and/or full emulation solution (FPGA, Veloce).4. The Hybrid solution provides simple environments (and

transactions between) bare metal, RTOS and eLinux.5. HAPS provides solution for specific IP/RTL verification

and software integration (which cannot be done by purely virtual platform like the VDK/Xplorer, such as PHY)

6. The Hybrid setup results with longer validation time for both VLSI and SW teams

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Additional Validation Time

Validation with Hybrid SetupDesign Launch RTL FreezeMain cores ready

VLSI

SW

VDK Ready HAPS Ready

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Software Environments

AXIAXI

USB Controller

ARM CortexINTC

Memory 1(DDR3)

Memory 0(SRAM) UART

UMRBus

Bare Metal Embedded Linux FreeRTOS

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USB3/ARM VDK & HAPS DEMO

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Q & A