V2Ic Control: A Novel Control Technique with Very Fast ......3 IV Annual Meeting 2011 March...

ce

i@u

pm

.es

Universidad Politécnica de Madrid

V2Ic Control: A Novel Control Technique

with Very Fast Response under Load and Voltage Step

Pedro Alou

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Introduction

VoutVin

LOA

D

Cout

L

VoutVin

LOA

D

Cout

L

Integrated DC/DC converter

Starting point Aim


Output capacitor+

Component size reduction

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Bandwidth requirementsModulator Reference

PWM

Load

Sawtooth

Voltage mode control

Frequency

1.0KHz 3.0KHz 10KHz 30KHz 100KHz 300KHz 1.0MHz 3.0MHz 10MHzVp(VOUT)

-200d

-100d

0d

SEL>>

V(VOUT)

1.0V

1.0mV

1.0KV

Parasitic ESLFres = 1.8 MHz

Maximum BW1MHz

Maximum BW limited by parasiticsFs=5MHz

Typical BW up to 300kHz

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Contents

Fast transient response techniques V2Ic Control

Design Examples: 5 MHz sync buck converter

Experimental results

Conclusions

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Fast transient response techniques: V2

Non-linear control techniques:V2 control

1

Modulator Reference

PWM

Load

AdvantagesFast dynamic response

Simplicity

DisadvantagesTriangular output voltage ripple is

needed (ESR dominant)

PWM

Vout

Reference

V2 control

Instability due to non-

dominant ESR

Vout

PWM

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Fast transient response techniques

Linear and non-linear:Hysteretic IC

A. Soto, P. Alou and J.A. Cobos, “Non-Linear Digital control Breaks Bandwidth Limitations”, in Proceedings of 2006 Applied Power Electronics Conference APEC ’06.

LOAD

-Vref

+

Vout

R(s)

Linear loop

+-

ICout

Non-linear loop

2

PWM

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Advantages

Disadvantages

Fast dynamic response

Variable switching frequency

High sensitivity to parasitic effects


LOAD

-Vref

+

Vout

R(s)

Linear loop

+-

ICout

Non-linear control

2

PWM

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2

Non-invasive output capacitor current sensor

Same phase

Proportional impedance

S.C. Huerta, P. Alou, J.A. Oliver, O. Garcia, J. A. Cobos, A. Abou-Alfotouh, “Design methodology of a non-invasive sensor to measure the current of the output capacitor for a very fast nonlinear control”, IEEE Applied Power Electronics Conference APEC’09.

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Fast transient response techniques: VIc

Compensating slope is needed to avoid sub-harmonic oscillation over 50% duty cycles

Helps to desensitize to current sensor mismatches and parasitic effects.

The higher the compensating slope, the worse the dynamic response.

Trade-offIt is necessary a compromise!

VIc ControlECCE’10 Fast control technique based on peak current mode control of the output capacitor current del Viejo, M.; Alou, P.; Oliver, J.A.; Garcia, O.; Cobos, J.A.;

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The evolution from VIc to V2Ic

VIC Control V2IC Control

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V2Ic operation: load step

V2IC Control

Load Step

Fast reaction 200ns/div

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V2Ic operation: reference step

V2IC Control

Fast reaction

200ns/div

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Contents


V2Ic Control

Design Examples:

5 MHz sync buck converter Experimental results

Conclusions

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5MHz Design example

Vin=3VVout=1V, fsw=5MHz, L=100nH Cout=4µF. Compensating ramp 600mV KVerror = 1 current loop gain (Ksensor) is 0.2V/A.

V2IC Control

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5MHz Design example: Output Impedance

V2IC Control

Zout

Equivalent to 1.5MHz BW

Open Loop Output Impedance

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Comparison at 5MHz: VMC, VIc and V2Ic

Output voltage response under load step (4A)

Output voltage response under voltage reference step (1V)

Comparison of the proposed techniques with 1MHz bandwidth voltage mode control

Specifications:fsw=5MHz

Vin=3VVout=1VCout=4µFL=100nH

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Contents


V2Ic Control

Design Examples: 5 MHz sync buck converter

Experimental results (1 MHz) Conclusions

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V2Ic 1MHz Design: Experimental Results

Voltage reference step



2μs2μs

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ConclusionsV2Ic Control

Advantages


Fast dynamic response (feedforward of the load current)

Constant switching frequency

Low sensitivity to parasitics (compensating slope

Non-invasive output capacitor current sensor

Cout reduction

Fast ref tracking

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1MHz Design: Comparison V2Ic vs V2V2IC Control vs V2

Oscillation due to non dominant ESR(100mV/div)

10µs/div

load step of 4A (40A/µs)

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Design example IIV2IC Control vs V2

Oscillation due to non dominant ESR(100mV/div)

10µs/div

ref step 1V (2.5V/µs).

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V2Ic 1MHz Design: Experimental Results

Load step

Positive load step of 1A and 40A/µs Negative load step of 1A and 40A/µs



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5MHz Design example: Load Step responseV2IC Control

di/dt=40A/µs (2µs/div)

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VIc vs high bandwidth voltage mode control

VIc→ ∆B=50kHzVoltage mode control→ ∆B=1MHz

fsw=5MHz

Output voltage response under load step (2A)

Inductance current response under load step (2A)

Same voltage drop.20 times less bandwidth in the proposed control making

easier the implementation and integration of the system.


Vin=3VVout=1V

Cout=10µFL=100nH

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5MHz Design example: Output Impedance

Fast Loop Effect

V2IC Control

Slow Loop Effect

V2Ic Control: A Novel Control Technique with Very Fast ......3 IV Annual Meeting 2011 March...

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