Utilizing Avalanche Breakdown for Stress

Measurements on Micro-structures

by

Abbin Perunnilathil Joy

MSc., National University of Singapore, 2014

B.E., Anna University, 2012

Thesis Submitted in Partial Fulfillment of the

Requirements for the Degree of

Master of Applied Sciences

in the

School of Mechatronic Systems Engineering

Faculty of Applied Sciences

© Abbin Perunnilathil Joy 2019

SIMON FRASER UNIVERSITY

Summer 2019

Copyright in this work rests with the author. Please ensure that any reproduction or re-use is done in accordance with the relevant national copyright legislation.

ii

Approval

Name: Abbin Perunnilathil Joy

Degree: Master of Applied Science

Title: Utilizing Avalanche Breakdown for Stress Measurements on Micro-structures

Examining Committee: Chair: Siamak Arzanpour Associate Professor

Behraad Bahreyni Senior Supervisor Associate Professor

Mehrdad Moallem Supervisor Professor

Michael Adachi Internal Examiner Assistant Professor

School of Engineering Science

Date Defended/Approved: 15th May 2019

iii

Abstract

This thesis reports on the usage of the breakdown voltage of a p-n junction diode to

measure the mechanical stress/strain in micro-resonators. The working principle relies on

the dependence of silicon band gap to the mechanical stress which then affects the

current-voltage characteristics of the p-n junction. To explore the effects of mechanical

stress/strain on breakdown voltage, a flexural-mode micro-resonator is designed by

defining a p-n junction at the anchoring region to experience maximum stress during

mechanical excitations. An analytical model has been developed for the study and

numerical analysis of this phenomenon. The Synopsys Sentaurus TCAD simulations were

employed for the investigation of the breakdown voltage dependence to various

mechanical stress magnitudes as well as orientations. A micromechanical device with

integrated junctions was designed and fabricated for the validation of postulate.

Mechanical stress was applied onto the substrate by subjecting it to mechanical vibrations.

It is estimated that the breakdown voltage of the device exhibited a high-stress sensitivity

of about 240µ𝑉/𝑀𝑃𝑎. The mechanical stress can also be measured by monitoring the

device current while biased at a constant voltage. In this mode, the steep changes of the

junction current in breakdown region led to nearly tenfold higher stress sensitivity

compared to a piezoresistive sensor. The high sensitivity, simple measurement, and

potential for miniaturization for breakdown voltage sensing make it a promising technique

for measurement of stress in micro- and nano-mechanical devices.

Keywords: Micro-resonators, p-n junction, piezoresistive sensor, high sensitivity,

breakdown voltage.

iv

Dedication

To my Pappa, P. K. Joy, and Mummy, Mary Joy

To the scientific community

v

Acknowledgments

This thesis would not have been possible without the support and efforts of many

people. First of all, I would like to express the deepest gratitude to my advisor, Dr. Behraad

Bahreyni, for the opportunity to work under his mentorship throughout my graduate

studies. He has been patient and very generous with his knowledge and assisted me in

each step of my research towards the completion of this dissertation. This thesis would

not have been completed without his continuous support and supervision.

I would like to thank my committee members, Profs. Mehrdad Moallem, Michael

Adachi and Siamak Arzanpour for agreeing to be members of the committee, and read

this dissertation and give me their invaluable feedback to improve the quality of work.

Many thanks to each and every staff and technicians of Nanofabrication and

Nanoimaging facilities at the 4D LABS for granting me access to use their state-of-the-art

equipment. The training and technical support has greatly helped in the expedition of

process development and improved my hands-on skills in micro-fabrication.

Finally, I would like to express my great appreciation for the previous and current

members of Intelligent Sensing Laboratory (ISL) with whom I cherished some wonderful

moments during the graduate student life. Thanks to Dong Hao Zhuo, for the friendship

and companionship. His unconditional support helped me to strive and overcome some of

the difficult phases during my graduate student life. Thanks to Dr. Soheil Azimi, Dr. Abdul

Qader Ahsan, and Dr. Mikhail Kanygin for the invaluable time and effort in training me on

the lab equipment and their helpful technical discussions.

Last but not least, I am deeply thankful to my dear parents, Joy and Mary, and my

sisters, Assiya and Anitha, for their unconditional love and unwavering support in my life.

vi

Table of Contents

Approval .......................................................................................................................... ii

Abstract .......................................................................................................................... iii

Dedication ...................................................................................................................... iv

Acknowledgments ........................................................................................................... v

Table of Contents ........................................................................................................... vi

List of Tables ................................................................................................................. viii

List of Figures................................................................................................................. ix

List of Acronyms ............................................................................................................ xii

List of Symbols ............................................................................................................. xiv

Chapter 1. Introduction .............................................................................................. 1

1.1. Background ........................................................................................................... 1

1.2. Motivation .............................................................................................................. 2

1.3. Objectives.............................................................................................................. 3

1.4. Thesis outline ........................................................................................................ 4

Chapter 2. Mechanical sensing at small-scales ....................................................... 6

2.1. Electrostatic sensing .............................................................................................. 6

2.2. Piezoresistive sensing ........................................................................................... 9

2.3. Piezoelectric sensing ........................................................................................... 13

2.4. Piezojunction sensing .......................................................................................... 16

Chapter 3. Breakdown voltage sensing mechanism.............................................. 19

3.1. The P-N junction diode ........................................................................................ 19

3.2. Breakdown mechanisms ...................................................................................... 20

3.2.1. Avalanche breakdown ................................................................................. 20

3.2.2. Zener breakdown ......................................................................................... 22

3.3. Mechanical stress effects on the breakdown voltage ........................................... 23

Chapter 4. Device simulation ................................................................................... 27

4.1. Sentaurus structure editor ................................................................................... 29

4.2. Sentaurus device ................................................................................................. 30

4.3. Electrical breakdown simulation ........................................................................... 32

4.4. Simulation of mechanical stress effects on the breakdown voltage ...................... 34

Chapter 5. Device Fabrication ................................................................................. 39

5.1. Starting substrate ................................................................................................ 40

5.2. Blanket doping ..................................................................................................... 41

5.2.1. Doping ......................................................................................................... 41

5.2.2. Annealing/Oxidation .................................................................................... 42

5.3. Selective doping .................................................................................................. 43

5.3.1. Photolithography optimization ...................................................................... 44

5.3.2. N-region doping ........................................................................................... 46

vii

5.4. Passivation .......................................................................................................... 49

5.5. Metallization ........................................................................................................ 50

5.5.1. Via formation ............................................................................................... 50

5.5.2. Metal deposition .......................................................................................... 51

5.6. Silicon patterning ................................................................................................. 53

5.7. Release ............................................................................................................... 55

5.7.1. Backside metal deposition ........................................................................... 55

5.7.2. Vapor HF ..................................................................................................... 55

5.8. Packaging............................................................................................................ 58

Chapter 6. Device design and characterization ...................................................... 60

6.1. Device design ...................................................................................................... 60

6.2. Device analysis ................................................................................................... 62

6.2.1. Mechanical domain ...................................................................................... 63

6.2.2. Electrical domain ......................................................................................... 65

6.3. Device testing and characterization ..................................................................... 66

6.3.1. Metrology inspection .................................................................................... 66

6.3.2. Diode characteristics ................................................................................... 68

6.3.3. Resonant frequency detection ..................................................................... 70

6.3.4. Effects of electrostatic actuation on the breakdown voltage ......................... 72

6.3.5. Mechanical shaker testing of the breakdown voltage sensor ....................... 75

Chapter 7. Conclusions and future work ................................................................ 81

7.1. Conclusions ......................................................................................................... 81

7.2. Thesis Contributions ............................................................................................ 83

7.3. Future work ......................................................................................................... 84

References ................................................................................................................... 85

Appendix A Fabrication details .................................................................................. 90

Appendix B Synopsys Sentaurus TCAD pseudo code ........................................... 101

viii

List of Tables

Table 2-1: Summary of gauge factor for different materials ........................................... 11

Table 5-1: Summary of SOI wafer parameters .............................................................. 41

Table 5-2: Summary of blanket ion implantation process parameters ............................ 42

Table 5-3: Summary of RIE and BOE etch process parameters .................................... 46

Table 5-4: Summary of n-type ion implantation process parameters ............................. 47

Table 5-5: LPCVD silicon nitride process parameters .................................................... 49

Table 5-6: RIE parameters of LPCVD Si3N4 etch ......................................................... 51

Table 5-7: VHF parameters of silicon release ................................................................ 57

Table 5-8: Wire bonding parameters ............................................................................. 58

Table 6-1: Summary of maximum stress, σyy ................................................................. 64

ix

List of Figures

Figure 2-1: Schematic view of an electrostatic transducer with charge distribution ..... 7

Figure 2-2: (a) MEMS capacitive strain sensor (b) SEM image of fabricated MEMS capacitive strain sensor system [13] © 2006 IEEE ................................... 8

Figure 2-3: Conceptual schematic view and Wheatstone bridge circuit of a piezoresistive sensor .............................................................................. 10

Figure 2-4: (a) Layout of a PZR sensing chip (b) MEMS sensor and PCB setup (c) Sensor output signal for different doping concentration (d) Sensitivity measurement of PZR at room temperature when input voltage = 5 V [23] © 2011 IEEE .......................................................................................... 12

Figure 2-5: Schematic view of a piezoelectric transducer and equivalent circuit model ............................................................................................................... 14

Figure 2-6: (a) SEM image of 380 x 380 µm ZnO strain sensor (b) Experimental data from piezoelectric sensor in reference to laser-doppler-vibrometer [28] © 2008 IEEE .............................................................................................. 16

Figure 2-7: (a) Band structure of silicon under zero stress (b) Modification of band structure under stress [41] © 1955 IEEE ................................................ 18

Figure 3-1: Schematic view of a p-n junction diode .................................................. 19

Figure 3-2: Plot for the critical electric field over different values of doping concentration ......................................................................................... 21

Figure 3-3: Temperature dependence plot of energy bandgap and breakdown voltage ............................................................................................................... 24

Figure 3-4: Temperature dependence of device sensitivity ....................................... 25

Figure 3-5: (a) Variations of energy bandgap and (b) Variations of breakdown voltage with applied mechanical stress ............................................................... 26

Figure 4-1: (a) Top view of the device structure with boron/phosphorus doping defining an embedded p-n junction (b) Schematic view of the structure 27

Figure 4-2: Overall process flow of Sentaurus TCAD simulation .............................. 28

Figure 4-3: (a) 2D schematic view of the generated structure with active doping concentration (b) Generated structure in the 3D domain (c) Doping concentration profile along the silicon thickness ..................................... 29

Figure 4-4: (a) Active doping concentration distribution of device structure in 2D (b) Effective bandgap plot across silicon depth through p-n junction (c) & (d) Hole and electron mobility vs silicon depth ............................................. 31

Figure 4-5: (a) Sentaurus device simulation plot of p-n junction under reverse biased (b) Sentaurus device simulation plot of p-n junction under forward biased ............................................................................................................... 33

Figure 4-6: Mechanical stress simulation results of breakdown voltage changes when applied input stress is parallel to the p-n junction ................................... 35

Figure 4-7: Mechanical stress simulation results of breakdown voltage changes when applied input stress is perpendicular to the p-n junction ......................... 36

Figure 4-8: Non-linear breakdown voltage response for higher applied stress from -250 MPa to 250 MPa ............................................................................. 37

x

Figure 4-9: Comparison of simulated breakdown voltage changes with theoretical model ..................................................................................................... 38

Figure 5-1: Major steps in the device fabrication process flow .................................. 39

Figure 5-2: (a) Initial SOI substrate doping with Boron ions (b) Diffusion of implanted ions to a junction depth of 1.2 µm by thermal growth of SiO2 (c) Synopsys Sentaurus TCAD simulation of blanket ion implantation (d) Post-annealing plot of surface concentration .................................................................. 43

Figure 5-3: Summary of photolithography process flow and associated process conditions. .............................................................................................. 45

Figure 5-4: (a) EDX analysis on silicon confirms the completion of oxide etch (b) EDX analysis on silicon dioxide shows the presence of oxide. ....................... 46

Figure 5-5: (a) SOI wafer before phosphorus ion implantation (b) SOI wafer after phosphorus ion implantation .................................................................. 47

Figure 5-6: (a) Ion-implanted contrast difference on alignment pattern (b) Ion implanted contrast difference on breakdown voltage sensor region........ 48

Figure 5-7: Synopsys Sentaurus TCAD simulation plot of p-n junction doping profile ............................................................................................................... 48

Figure 5-8: (a) SOI wafers before LPCVD silicon nitride deposition (b) SOI wafers after LPCVD silicon nitride deposition .................................................... 50

Figure 5-9: (a) Graphical representation of via formation (b) Microscopic inspection after patterning vias. ............................................................................... 51

Figure 5-10: Graphical representation of metal deposition ......................................... 52

Figure 5-11: IV characteristics of N-contact ................................................................ 53

Figure 5-12: (a) RIE of Si3N4 and SiO2 (b) DRIE of device silicon ............................. 54

Figure 5-13: SEM image of 2 µm pitch pattern (left) SEM image of 3 x 3 µm etch hole (right) ..................................................................................................... 54

Figure 5-14: Process schematic of SOI wafer after backside metal deposition ........... 55

Figure 5-15: Optical image of the sample after VHF at 40 ºC for 20 minutes .............. 56

Figure 5-16: Optical image of the sample before and after VHF ................................. 57

Figure 5-17: SEM image of the final released sample ................................................ 58

Figure 5-18: Final released and packaged device ...................................................... 59

Figure 6-1: Top view of designed breakdown voltage sensor (left) and p-n junction actuator (right) ........................................................................................ 61

Figure 6-2: 3D model of final device design with geometric details ........................... 62

Figure 6-3: Modal analysis result of the out-of-plane resonance frequency .............. 63

Figure 6-4: Breakdown voltage and critical electrical field plot for different background dopant concentration .............................................................................. 66

Figure 6-5: (a) SEM of the final device where the annotation ‘N’ and ‘P’ indicates metal contacts to the n-doped region and p-type device layer respectively (b) Zoomed-in views of breakdown voltage sensor (c) Piezoresistor (d) Low magnification optical image of device.............................................. 67

Figure 6-6: Optical image of damaged p-n junction due to a spike in diode current .. 68

Figure 6-7: Measured Current-Voltage characteristics curve of p-n junction diode ... 69

xi

Figure 6-8: Gummel plot of p-n junction diode in the forward bias region ...................... 69

Figure 6-9: Test setup for resonant frequency estimation using vibrometer .............. 71

Figure 6-10: Resonant peaks and 3D scan results from vibrometer ........................... 72

Figure 6-11: Test setup for breakdown voltage changes by electrostatic actuation .... 73

Figure 6-12: Changes in breakdown voltage for different AC amplitudes ................... 74

Figure 6-13: Measured frequency dependence of breakdown voltage sensor output . 75

Figure 6-14: Mechanical shaker test setup for breakdown voltage sensor testing ...... 76

Figure 6-15: Box plot for breakdown voltage changes to mechanical vibrations (1g to 10g acceleration) at 500 Hz ................................................................... 77

Figure 6-16: Comparison of current changes between PZR and BV sensor ............... 78

Figure 6-17: Sensitivity of breakdown voltage changes and noise measurements to the different diode current ............................................................................ 79

xii

List of Acronyms

AC Alternating current

AlN Aluminum nitride

BC Boundary condition

BJT Bipolar junction transistor

BOE Buffer oxide etchant

BOX Buried oxide

BV Breakdown voltage

CD Critical dimension

CMOS Complementary metal-oxide-semiconductor

CVD Chemical vapor deposition

DC Direct current

DRIE Deep reactive-ion etching

EDX Energy dispersive X-ray

FEA Finite element analysis

GF Gauge factor

HF Hydrofluoric acid

IC Integrated circuit

ICP Integrated Circuit-Piezoelectric

IPA Isopropyl alcohol

JFET Junction field effect transistor

LDV Laser Doppler vibrometer

LED Light emitting diode

LPCVD Low-pressure chemical vapor deposition

MEMS Micro-electro-mechanical system

MOSFET Metal-oxide-semiconductor field-effect transistor

PCB Printed circuit board

PVDF Polyvinylidene fluoride

PZR Piezoresistor

TCAD Technology computer-aided design

PZT Lead Zirconate Titanate

RC Resistor-capacitor

RIE Reactive-ion etch

xiii

SEM Scanning electron microscopy

SMU Source measure unit

SOI Silicon-on-Insulator

UV Ultraviolet

ZnO Zinc oxide

xiv

List of Symbols

𝐶 Capacitance

𝑑 Distance between electrodes

𝑄 Charge

𝐿 Length

𝐴 Area

𝑡 Thickness

𝑘 Spring constant

𝑉𝐷 Diode voltage

𝑉𝑇 Thermal voltage

𝐼𝐷 Diode current

𝐼𝑆 Reverse saturation current

𝐸𝑟𝑒𝑣 Reverse bias electric field

𝐸𝑚 Critical electric field

𝐸𝑃𝐸 Potential energy

𝐸𝑐 Conduction band energy

𝐸𝑔 Bandgap

𝑘𝐵 Boltzmann constant

𝑇 Temperature

𝑁𝐵 Background doping concentration

𝑥𝑗 Junction depth

𝑅𝑃 Projection range

𝑘𝑒𝑓𝑓 Effective spring constant

𝑚𝑒𝑓𝑓 Effective mass

𝑓0 Resonant frequency

𝑤𝑏 Rectangular beam width

𝑙𝑏 Rectangular beam length

ℎ Rectangular beam thickness

𝐼 Moment of inertia

𝑦 Distance from the neutral axis

𝐹 Force

𝑞 Electron charge

𝜌 Resistivity

xv

𝜀 Strain

𝜋𝐿 Longitudinal piezoresistive coefficient

𝜋𝑇 Transverse piezoresistive coefficient

𝜎𝐿 Longitudinal mechanical stress

𝜎𝑇 Transverse mechanical stress

𝑒31 31 piezoelectric coefficient

∈33𝑆 Material permittivity

𝛼 Material constant

𝛾 Stress sensitivity constant

∈𝑠 Permittivity of silicon

∈0 Permittivity of free space

𝑑33 33 piezoelectric coefficient

ћ Planck’s constant

1

Chapter 1. Introduction

1.1. Background

Micro-electromechanical systems (MEMS) refers to the technology as well as the

micro-scale devices that are microfabricated and combine mechanical and electrical

elements for their operation [1]. Devices developed through MEMS technologies have had

a great impact on various applications. The advancement in silicon-based

microelectronics process and integration with the micromachining process are some of

the major reasons behind the popularity of MEMS devices [1]. MEMS technology has

become an indispensable contributor to our day-to-day lives, greatly improving the quality

of life for consumers. Surface and bulk micro-machining are the two fabrication techniques

for such systems. Surface micro-machining is the process of developing miniaturized

devices by the successive deposition and etching of thin films, whereas bulk micro-

machining selectively etches the silicon substrate to carve a structure [2]. Recent

advancements in micro-fabrication technology have made it possible to scale down the

device size from micro-scale to nano-scale [3].

MEMS devices have the functionality to sense, actuate and control the physical

quantities at micro-scale and translate the acquired data from one domain to another [4].

Much of this has been made possible by exploiting the electrical and mechanical

properties of silicon, as opposed to the integrated circuit technology that focuses on the

electrical properties only. By combining the transduction capabilities of MEMS technology

and signal processing functionalities of integrated circuits, the system performance is

enhanced and adapted for a wide range of applications [5]. The multi-disciplinary nature

of MEMS technology can be effectively used for the integration of diverse domains such

as biology and electronics [1]. In addition, MEMS devices are manufactured by a batch

process in which large quantities of devices are produced together, lowering the cost-per-

device. Due to the nature of certain physical quantities, it is favorable to do sensing at

micro-scale by achieving specific results with great accuracy and repeatability [6]. Due to

their small dimensions, some quantities can only be measured by MEMS technology,

making it unique and distinct from other technology platforms [7]. The challenges and

technological obstacles such as device scalability and new processing methods for novel

2

functional materials are still in the progressive phase to unveil the full potential of MEMS

technology.

Much of the utility of MEMS devices stems from having devices that can transduce

energy between different physical, chemical, and biological domains. Different

transduction mechanisms are employed to develop MEMS-based sensors and actuators

as the two fundamental building blocks in the field. Sensors are the devices responsible

for the measurement of physical, chemical, or biological quantities such as force,

pressure, gas concentration, temperature, etc. and often convert this information into an

electrical signal proportional to the measured parameters. In contrast, MEMS actuators

are the devices that convert an electrical signal to mechanical excitation by generating

force/strain.

The technological advancements and customer requirements are the major driving

forces behind the research and development of sensors and actuators market [8]. Due to

the advancements in MEMS technology, it finds numerous applications in diverse

industries such as Automotive, Consumer electronics, Bio-medical systems,

Communications and Defence [1]. Majority of the MEMS devices involve mechanical

movements a structure that leads to the changes in internal mechanical stress. Therefore,

the demand for high precision and high sensitive mechanical stress sensor is superior in

high-performance MEMS applications.

1.2. Motivation

The motivation behind this research is to find an alternative method for the sensing

of mechanical stress in micro-electromechanical systems that offers high sensitivity with

simple interfacing requirements. There are numerous transducers that have been

employed for the detection of mechanical stress/strain at the micro/nanoscale. The effects

of mechanical stress on the p-n junction, which manifests itself through the piezojunction

effect, has been studied over the years [9].

Although prior studies validate the effects of mechanical stress on p-n junctions,

the focus has remained on analyzing and modeling the variations in diode characteristics

under zero or forward-bias conditions. This research investigates the effects of mechanical

stress in a p-n junction diode under junction breakdown conditions. Throughout this work,

3

we studied the phenomena, developed analytic and numerical models, fabricated

prototypes, and finally validated the models. The lower power consumption, high-

sensitivity, simplicity in micro-fabrication and potential for miniaturization enable this

sensing mechanism to play a role in the field of future micro- and nano-device

manufacturing.

1.3. Objectives

The major objectives of this MASc thesis are:

Analysis and modeling of the dependence of p-n junction breakdown voltage

on mechanical stress

The effects of mechanical stress/strain over breakdown parameters in a silicon-

based p-n junction diode are understudied. The literature on this phenomenon is limited

to hydrostatic pressure effects based on crude structures [10]. This work focuses on the

development of models for the phenomenon to be confirmed with physical

implementations of micro-scale prototypes. We study the effects of mechanical stress on

p-n junction breakdown parameters. Analytical modeling facilitates the prediction of device

performance and further optimization for sensitivity improvements. The 2D and 3D device

simulations are employed to analyze the effects of mechanical stress on energy bandgap

and carrier transport properties within a p-n junction. Numerical simulations allow for the

study of different effects under near real-world conditions.

Fabrication of device prototypes

To study the effects of mechanical stress on breakdown voltage, an embedded p-

n junction is designed on a mechanical moving structure. The upward and downward

movements of the mechanical structure exert maximum stress at the anchoring regions,

where the p-n junctions are defined. Micro-resonators with moving mechanical plates are

designed with different shapes and geometries at the desired frequency of resonance in

the range of kHz. In addition to the breakdown voltage sensors, conventional piezoresistor

(PZR) sensors are also designed at the anchor points for the baseline sensitivity

comparison to mechanical stress. The design prototypes are developed by a Silicon-On-

Insulator bulk-micromachining process with doping and deep etching steps, for the

definition of embedded p-n junctions as well as mechanical structures, respectively. All

4

processing steps were carried out in class 100 cleanroom facility by following the

environmental, health, safety and security requirements.

Testing and characterization of the breakdown voltage sensor

The breakdown voltage sensor prototypes were tested for performance analysis

and sensitivity comparison. The measurements were performed with a stable test setup

to minimize the influence of external interferences. Initially, current-voltage characteristics

of the device were analyzed for the measurement of p-n junction diode parameters.

Followed by the dynamic measurements in the electrical and mechanical domain for the

device performance estimation. The repeatability test demonstrates the stability and

reproducibility of the measured signal over time. In addition, the influence of diode bias

current to device sensitivity and to signal noise level was analyzed and discussed in detail.

All the experiments associated with breakdown voltage sensors were repeated by the

piezoresistive sensor to have a baseline comparison.

1.4. Thesis outline

The dissertation is divided into six chapters as follows:

Chapter 1 provides the general background and motivation behind this work,

followed by a detailed description of objectives and methodology.

Chapter 2 discusses different MEMS-based stress/strain sensors available in the

market. Each of these transducers is analyzed from the perspective of working physics to

its merits and demerits.

Chapter 3 explains the physics behind the breakdown phenomenon in silicon-

based p-n junction diodes. Its effects on mechanical stress are mathematically modeled

and verified by simulations. The step-by-step procedure for simulations and its results are

discussed in detail.

Chapter 4 describes the micro-fabrication process flow from substrate selection to

device packaging with associated process recipes as well as metrology inspections.

5

Chapter 5 proves the effects of mechanical stress/strain on breakdown voltage by

experimental results. The noise analysis and frequency response of the device is

discussed for future enhancements.

Chapter 6 concludes the dissertation with observations and challenges in

employing the breakdown voltage sensor for high-frequency systems with contributions,

major achievements, and future works.

6

Chapter 2. Mechanical sensing at small-scales

A transducer can be defined as the device that converts input energy from one

domain to output energy in the other [11]. There are several types of transducers available

for different sensing and actuation applications. However, the transducer selection criteria

vary by the desired performance specifications such as sensitivity, fabrication complexity,

noise performance, manufacturing yield, and material compatibility.

Measurement of mechanical deformations at micro-scales is based on two

fundamental physical methods: (1) a change in distance; (2) a change in material

properties under stress [12]. The electrostatic transduction mechanism is an example for

the distance-based sensing whereas the sensing mechanism by the piezoresistive and

the piezoelectric transducers are based on the change in material properties. An overview

of the mechanical stress/strain sensing at micro-scale by different transducers has been

discussed in the following sections.

2.1. Electrostatic sensing

The working principle behind electrostatic sensing is identical to the standard

electrical capacitor with one plate fixed and another plate movable. The mechanical

quantities such as pressure, force and accelerations are the typical sensed parameters in

MEMS devices [13]. The electrostatic transduction works based on the principle that the

mechanical input quantities cause the capacitor assembly to move, therefore changing

the capacitance, producing a detectable change in the output voltage on a charged

capacitor, for instance [6]. The amount of charge Q accumulated on the parallel plates can

be expressed as a function of applied voltage (𝑉𝑖𝑛) by:

𝑄 = 𝐶𝑉𝑖𝑛 2.1.

where 𝐶 is the capacitance between parallel plates. If a capacitor is biased with an input

voltage (𝑉𝑖𝑛) the stored energy (𝐸) is given by:

𝐸 =1

2𝐶𝑉𝑖𝑛

2 2.2.

7

A common method of implementing the electrostatic sensing is by designing a

movable electrode between two fixed electrodes as shown in figure 2-1. A constant

voltage bias is supplied to the fixed electrodes as the inputs and the output signal is drawn

from the movable electrode for signal conditioning. The input mechanical quantities result

in the displacement of the movable electrode in one direction, by changing the gap

between electrodes in opposite directions. Therefore, the effective capacitance between

the fixed and movable electrodes increases and decreases simultaneously and can be

expressed as per the following equations.

∆𝐶1 =∈0 𝐴

𝑑 − 𝑥−

∈0 𝐴

𝑑 2.3.

∆𝐶2 =

∈0 𝐴

𝑑 + 𝑥+

∈0 𝐴

𝑑

2.4.

The output current flowing through the movable electrode is given by the rate of flow of

charge accumulated across the capacitor and can be expressed by the equation (2.5) [6].

𝑖𝑜𝑢𝑡 =

𝑑𝑄

𝑑𝑡=

𝑑

𝑑𝑡[(𝐶1(𝑉𝑖𝑛1 − 𝑉𝑜𝑢𝑡)] +

𝑑

𝑑𝑡[(𝐶2(𝑉𝑖𝑛2 − 𝑉𝑜𝑢𝑡)]

2.5.

Figure 2-1: Schematic view of an electrostatic transducer with charge distribution

Figure 2-2: Schematic view of an electrostatic transducer with charge distribution

8

where 𝑉𝑖𝑛1 and 𝑉𝑖𝑛2 are the input voltages applied to fixed electrodes, 𝑉𝑜𝑢𝑡 is the output

voltage drawn from the movable electrode. Typically, the user sets 𝑉𝑖𝑛1 = −𝑉𝑖𝑛2 while

holding 𝑉𝑜𝑢𝑡 near ground potential.

The electrostatic transduction mechanism can be used for the strain sensing based

on the changes in displacement or capacitance. Prior work done in 2006 [14]

demonstrates the usage of the electrostatic transducer for the design and implementation

of high-performance MEMS capacitive strain sensing. The sensing system consists of

three interdigitated comb fingers positioned at the structural center that changes the initial

Figure 2-2: (a) MEMS capacitive strain sensor (b) SEM image of fabricated MEMS capacitive strain sensor system [13] © 2006 IEEE

9

capacitance as a function of applied strain. The architecture of the electrostatic strain

sensor is shown in figure 2-2 (a).

An externally applied strain is introduced by the cantilever beam bending test setup

where the MEMS sensor is positioned near the anchoring region. The vertical

displacement of the cantilever beam generates the x-axis strain across the MEMS sensor.

The applied strain causes small lateral displacement which results in the deflection of the

top and bottom electrodes in the upward direction, changing the associated capacitance.

On the other hand, the center beam move downwards serving as a common reference

electrode. The mechanical gain of the strain sensing system is adjusted by the bending

angle of the interdigitated comb fingers. Lowering the bending angle enhances the

mechanical gain. Therefore the beam is designed with bending angle as low as 5.7º. The

SEM image of a MEMS capacitive strain sensor system is shown in figure 2-2 (b). The

MEMS differential capacitive strain sensors can yield high sensitivity with the capability of

measuring a strain as low as 0.9 𝑛𝜀 [14].

Electrostatic transduction has been widely used in the micro-device applications

due to its advantages such as larger dynamic range, low power consumption and ease of

micro-fabrication [15]. However, due to the nonlinear nature of electrostatic transduction

mechanism, the strain sensing system is prone to large signal-dependent nonlinearity at

higher applied strain values. The overall device dimension requirements raise challenges

in its miniaturization and usage in nano-scale applications.

2.2. Piezoresistive sensing

A piezoresistive sensor works based on the basic principle of the change in

electrical resistivity under the influence of mechanical stress as shown in figure 2-3. At

micro-scales, the most commonly used piezoresistive material is silicon (either crystalline

or poly-crystalline) due to its capability of electronics interfacing and ease in the

manufacturing process. The underlying physics behind piezoresistive effects in silicon is

due to the change in energy-bandgap under the external stress/strain. The changes in

energy-levels within the silicon lattice depends on the direction and nature of the applied

force. This leads to the lowering of electron mobility in n-Si thereby increasing material

resistivity [16].

10

The piezoresistive (PZR) sensor is one of the most widely used transduction

mechanism used for the detection of physical parameters such as mechanical

stress/strain. These sensors proved to have a better sensitivity performance compared to

other transducers [17]. However, its dependence on temperature variations has limited its

usage in several potential applications. At micro-scale, a typical piezoresistive sensor is

designed on a silicon substrate at which the resistor is defined by the doping process. The

increase in doping concentration is found to be an effective way to mitigate the thermal

drift in device performance [18]–[20]. On the other hand, this adversely affects the device

sensitivity. In addition to that, the discontinuity in stiffness coefficient during the strain

transfer through multiple layers is another limitation of piezoresistive transduction. These

limitations are addressed to meet the application specifications by optimizing the device

attributes to set the right trade-off between sensitivity and thermal stability.

A change in resistance (∆𝑅) due to the applied mechanical strain is produced by

the changes in any of the three quantities such as resistivity, length, and area as per

equation (2.6). The ratio of change in resistivity to the applied strain is expressed in a

dimensionless parameter known as gauge factor (GF). The gauge factor found in

semiconductor materials is found to be higher due to the change in resistivity whereas in

Figure 2-3: Conceptual schematic view and Wheatstone bridge circuit of a piezoresistive sensor

Table 2-1: Summary of gauge factor for different materials

Material Gauge Factor, F

Metals 2-5

Ceramic-metal mixture 5-50

Silicon 70-135

Figure 2-5: Conceptual schematic view of a piezoresistor

Table 2-1: Summary of gauge factor for different materials

11

metals the GF is smaller since the resistance change is primarily due to the change in

geometry. The gauge factor for an applied strain (ε) in semiconducting materials can be

calculated by the general expression as per equation (2.8).

∆𝑅

𝑅=

∆𝜌

𝜌+

∆𝐿

𝐿−

∆𝐴

𝐴 2.6.

∆𝜌

𝜌= 𝜋𝐿𝜎𝐿 + 𝜋𝑇𝜎𝑇 2.7.

𝐺𝐹 =

∆𝑅𝑅𝜀

2.8.

where 𝜌, 𝐿 and 𝐴 are the material resistivity, resistor length, and area, respectively.

𝜎𝐿 and 𝜎𝑇 are longitudinal and transverse stresses and 𝜋𝐿 and 𝜋𝑇 are piezoresistive

coefficients in the longitudinal and transverse direction. The gauge factor measured for a

few different materials is provided in table 2-1 [6].

A high-performance piezoresistive MEMS strain sensor with low thermal sensitivity

reported in [21]. The designed PZR comprised of four sensing units in which two are

oriented along 0º and 90º to measure stress components and one is oriented along 45º to

measure the shear stress component as shown in figure 2-4(a). The sensing elements are

designed in a full-bridge arrangement to minimize the thermal drift by balancing the

temperature coefficient of the resistor for different directions.

Table 2-1: Summary of gauge factor for different materials

Material Gauge Factor, F

Metals 2-5

Ceramic-metal mixture 5-50

Silicon ±70-135

Table 2-2: Summary of gauge factor for different materials

Material Gauge Factor, F

Metals 2-5

Ceramic-metal mixture 5-50

Silicon ±70-135

12

The temperature effects on the PZR is taken into account by considering the

thermal effects on PZR coefficients. The uniaxial stress along [110] orientation can be

computed from the resistor changes in full-bridge [22]:

∆𝑅

𝑅= 𝜎 (

𝜋11 + 𝜋12 + 𝜋44

2) 2.9.

where 𝜋11, 𝜋12 and 𝜋44are the piezoresistive coefficients, 𝜎 is the applied mechanical

stress and 𝑉𝑖𝑛 is the input excitation voltage.

The output voltage (𝑉𝑜𝑢𝑡) from a full-bridge configuration is obtained by multiplying with

bridge excitation voltage (𝑉𝑖𝑛) [21]:

Figure 2-4: (a) Layout of a PZR sensing chip (b) MEMS sensor and PCB setup (c) Sensor output signal for different doping concentration (d) Sensitivity measurement of PZR at room temperature when input voltage = 5 V [23] © 2011 IEEE

13

𝑉𝑜𝑢𝑡 = 𝜎 (

𝜋11 + 𝜋12 + 𝜋44

2) . 𝑉𝑖𝑛

2.10.

The PZR sensor with different doping concentration is tested and characterized to

study the variation in device sensitivity and plotted its response as shown in figure 2-4(c).

The device output voltage is a linear function regardless of doping concentration.

Although, the magnitude of changes in device output voltage is significantly higher when

the doping concentration is above 1019𝑎𝑡𝑜𝑚𝑠/𝑐𝑚3. The measured response includes the

undesirable effects by a change in resistance induced from bonding pads. The contact

pads are typically wire bonded and packaged by either aluminum or gold wire for electrical

interconnections. This introduces additional contact resistance between the metal pad and

wire tip limits the signal to noise ratio [21]. A flip-chip packaging scheme is proposed as a

solution to minimize signal loss due to the packaging [23]. Figure 2.4(d) shows the device

sensitivity plot against different doping concentration with repeatable measurements. The

result indicates that the designed PZR devices are highly repeatable and the sensitivity

drops at higher values of doping concentration. For a doping concentration of

1019𝑎𝑡𝑜𝑚𝑠/𝑐𝑚3, the measured sensitivity is 0.1 𝑚𝑉/𝜇𝜀 [23].

The MEMS-based piezoresistors are suitable for highly sensitive strain sensing

with good repeatability and reproducibility [24]. The transduction mechanism can be

employed for the static measurements by mitigating the thermal effects through optimal

design and process parameters [25]. In addition to that, the device has the capability to

measure the normal and shear components of stress. The PZR transduction has its own

limitations associated with it such as thermal effects and needs for large effective sensing

area makes it unsuitable for nanoscale applications [25].

2.3. Piezoelectric sensing

Piezoelectric transduction is a widely used transduction mechanism where the

strong electromechanical coupling is required such as in RF-MEMS applications [26]. The

piezoelectric effects are observed in certain materials where electric charges are produced

in response to applied mechanical stress. This phenomenon is a reversible process and

can be utilized for both sensing and actuation applications. Silicon is the most widely used

material in the field of microelectronics and does not exhibit the piezoelectric effect.

Therefore, the piezoelectric materials such as quartz, zinc oxide (ZnO), aluminum nitride

14

(AlN) and polyvinylidene fluoride (PVDF) are typically deposited or bonded to the silicon

substrate [6].

A typical piezoelectric material follows an ionic bonded crystalline structure with

positive and negative ions results in the formation of the dipole that cancels out each other

at rest. This creates symmetry within the crystal lattice and generates zero electric fields.

When mechanical stress is applied, the deformation of crystal happens by the generation

of a net dipole moment with an effective electric field across the crystal used for the stress

sensing parameter. However, the piezoelectric transducers are not suited for static

measurements or DC applications and only used in dynamic systems. This is due to the

internal impedance of the crystal that leads to the dissipation of charge over time [27].

Therefore, the piezoelectric transducers can be modeled as a voltage source with a series

capacitor and resistor as shown in figure 2-5.

In the majority of the applications, the piezoelectric material is sandwiched

between two metal electrodes as shown in figure 2-5. A mechanical force (𝐹) is applied

in perpendicular to the piezoelectric material generates charge (𝑄) that are collected by

the metal contacts given by:

𝑄 = 𝑑33𝐹 2.11.

where (𝑑33) is the piezoelectric constant along the z-direction. For the applied forces in

xy-plane, parallel to the metal electrodes, the piezoelectric constant value is referred to

Figure 2-5: Schematic view of a piezoelectric transducer and equivalent circuit model

Figure 2-6: Schematic view of a piezoelectric transducer and equivalent circuit

15

(𝑑31). Piezoelectric constants are material dependent, arising from their crystalline

structure.

The stress-strain relationship in a non-isotropic material is related by a tensor containing

different values of elastic modulus in different directions can be expressed as:

𝜎𝑖 = 𝐶𝑖𝑗𝜀𝑗 2.12.

where indices 𝑖 and 𝑗 varies from 1 to 6 representing different orientations. The inverse of

this relation is given by:

𝜀𝑖 = 𝑆𝑖𝑗𝜎𝑗 2.13.

where 𝑆𝑖𝑗 are the compliance coefficients which is referred to the inverse matrix of stiffness

coefficients 𝐶𝑖𝑗. When the piezoelectricity component is added, the mechanical strain can

be modified in relation to the resulting electric field as shown below [22]:

𝜀𝑖 = 𝑆𝑖𝑗𝜎𝑗 + 𝑑𝑗𝑖𝐸𝑗 2.14.

where 𝐸𝑗 is the component of electric field and 𝑑𝑗𝑖 represents the piezoelectric constants.

The piezoelectric transduction mechanism can be employed for the detection of

mechanical vibration in dynamic strain sensing. Prior work done in [28] shows the design

and fabrication of ZnO based piezoelectric sensor on silicon and steel substrates as

shown in figure 2-6(a). The experimental data indicates that the sensor is capable of high-

resolution measurements with the smallest measured strain of 40.3 nε at a sensitivity of

340 V/ε [28]. The designed piezoelectric sensor is modeled as an RC circuit for the

prediction of output voltage characteristics.

The measured signal response from the sensor is compared and validated with a laser-

doppler-vibrometer (LDV) simultaneously for the signal and noise analysis as shown in

figure 2-6(b). The sensor resolution varies largely by the frequency of operation and found

to be higher as compared to LDV. However, device manufacturing is complex due to the

incompatibility issues of piezoelectric materials with silicon. Also, the inability of using

16

piezoelectric transducers in a static system is another limiting factor to be widely used in

stress/strain sensing applications.

2.4. Piezojunction sensing

The piezojunction effect is referred to the changes in the saturation current of a p-

n junction under the influence of mechanical stress. This phenomenon was first discovered

by Hall, Bardeen, and Pearson in 1951 [29]. The characteristics of the piezojunction effect

are identical to piezoresistor in several aspects and can be useful or unwanted depending

Figure 2-6: (a) SEM image of 380 x 380 µm ZnO strain sensor (b) Experimental data from piezoelectric sensor in reference to laser-doppler-vibrometer [28] © 2008 IEEE

17

on the applications. A major advantage of the piezojunction transduction mechanism is its

minimal power consumption as compared to the conventional PZR sensors [30]. In

addition to that, the piezojunction transducers can be designed with a smaller chip area

with localized p-n junction formation and can be functional with sufficient DC

characteristics. However, the sensitivity and resolution of such transduction mechanism

are limited to higher order mechanical stress in the range of MPa to Gpa [31]. Therefore,

the application of the piezojunction effect in micro-system stress sensing is limited where

typical values of mechanical stress encountered at small scales (in the order of kPa).

The piezojunction effect was studied and modeled as a parasitic effect in the

integrated circuits. The mechanical stress generated from the micro-fabrication process

and packaging affects the long-term device stability and performance of semiconductor

devices [32]. The majority of the studies focused on the discrepancies generated in the

energy bandgap and temperature sensors due to mechanical stress [33]. This was later

used as the fundamental working principle for the development of mechanical stress

sensors. Several piezojunction based prototypes were developed such as microphones,

accelerometers, and pressure sensors [34]–[38]. These stylus-based sensing systems are

vulnerable due to the mechanical movements and by the advancement in technology later

resolved by the integration of transistors into micro-machined beams.

The physical behavior of the piezojunction effect can be explained by four different

transduction steps. Initially, the applied mechanical stress is converted into the strain. This

results in the modification of the energy band structure of silicon for the corresponding

strain. Third, the changes in energy bandgap and curvature leads to the modification in

carrier properties. Finally, the device current-voltage characteristics are shifted by the

changes in device transport properties. The numerical model and associated physics

behind the piezojunction effect are further discussed and studied in the following sections.

The exertion of mechanical stress on a structure leads to the deformation and

thereby changing resistance [39]. The electronic band structure changes in silicon for

applied strain has been studied with an assumption that the carriers are semi-classical

particles instead of waves [40]. The schematic of silicon band structure and its transitions

with and without strain is shown in figure 2-7. When no strain is applied the conduction

band minima and valence maxima are aligned at the same energy level and separated by

the forbidden energy gap, 𝐸𝐺. The mechanical strain influences the energy band structure

18

by changing the lattice constant resulting in a shift in band edges to other energy levels

as shown in figure 2-7(b) [41].

The curvature changes in band structure lead to the difference in electron effective

masses and affect the carrier mobility. These changes lead to the drift in device carrier

transport properties by creating a shift in current-voltage characteristics. The diode current

can be expressed in terms of mechanical stress by:

𝐼𝐷(𝜎) = 𝐼𝑠(𝜎) (𝑒𝑉𝐷

𝑛𝑉𝑇 − 1) 2.15.

𝐼𝑆(𝜎) = 𝐼𝑠0(1 − 𝛾1𝜎 + (𝛾12 − 𝛾2)𝜎2) 2.16.

where 𝐼𝑠0, 𝑉𝐷 , 𝑉𝑇 and 𝑛 are saturation current at rest, diode voltage, thermal voltage, and

diode ideality factor, respectively. The 𝛾1 and 𝛾2 stands for stress sensitivity constants

[42].

Figure 2-7: (a) Band structure of silicon under zero stress (b) Modification of band structure under stress [41] © 1955 IEEE

19

Chapter 3. Breakdown voltage sensing mechanism

3.1. The P-N junction diode

A p-n junction diode is the simplest two-terminal device that is created by joining

p-type and n-type semiconductor materials. It is also the fundamental building block in

electronic components like BJTs, MOSFETs, JFETs, LEDs and digital ICs [43]. Depending

on the current-voltage biasing conditions, the operating regions of the diode are

categorized as: (1) Zero bias, (2) Forward bias and (3) Reverse bias. Under zero bias

condition, the electrons from n-Si diffuse to p-region and holes from p-Si diffuse to n-

region. This results in the compensation of acceptor atoms and donor atoms at the

interface of p-Si and n-Si, respectively. An electric field is generated by the fixed ions

(positive ions on the n side due to the migration of electrons to the p side and negative

ions on the p side due to the diffusion of holes to the n side) which eventually prohibits

further diffusion of charge carriers. This region around the interface that is depleted of free

charge carriers is known as the depletion region or space charge region as shown in figure

3-1. Forward biasing means applying a positive voltage between the p-Si and n-Si sides

of the junction. This leads to the narrowing of the space charge region due to the repulsion

of holes in p-region and electrons in n-region, resulting in an exponential increase in diode

current. On the other hand, reverse bias happens when the voltage on the p-Si is less

than the n-Si side, which leads to an increase in the depletion region width. The flow of

charge carriers remains blocked by the depletion region and hence no current flows across

Figure 3-1: Schematic view of a p-n junction diode

20

junction other than the drift current produced due to the thermal generation of charge

carriers near the depletion region [43].

3.2. Breakdown mechanisms

The depletion region width of a p-n junction diode widens with an increase in the

reverse bias voltage. At higher applied voltage the junction breakdown occurs and results

in a significant increase in current due to the excessive flow of charge carriers crossing

the potential barrier. The reverse bias voltage at which the sudden increase in current is

referred to as breakdown voltage. Depending on the physics behind this phenomenon,

there are two types of breakdown mechanisms in typical p-n junction diodes which are

known as (1) Avalanche breakdown and (2) Zener breakdown [44]. The breakdown

voltage of the diode can be influenced by external factors such as electric field,

temperature, and mechanical stress [45]–[47]. Understanding the behavior of breakdown

voltage with each of these physical quantities can be effectively used as the working

principle behind numerous transduction mechanisms.

3.2.1. Avalanche breakdown

The avalanche breakdown mechanism happens under high reverse bias voltages

across relatively lightly-doped junctions due to the impact ionization. Under the reverse

bias condition, the potential barrier across the junction is increased by the applied voltage

and thus exerts high electric field across the junction. The generated electric field is given

by [44]:

𝐸𝑟𝑒𝑣 =𝑉𝑟𝑒𝑣

𝑑 3.1.

where 𝑉𝑟𝑒𝑣 and 𝑑 are reverse bias voltage and depletion width respectively. The

generated electric field attracts electron with a force enough to break a covalent bond. The

created carriers are then accelerated with high kinetic energies across the depletion

region. Some of these carriers may collide with neighboring atoms and generate more

electron-hole pairs. This phenomenon of continuous carrier generation as a chain process

is called impact ionization. Avalanche breakdown is a non-destructive phenomenon,

however, the heating caused by large breakdown current can damage the junction.

21

The electron-hole pairs generated by the impact ionization can be found from [44]:

𝑀 =

1

1 − ∫ 𝛼𝑑𝑥𝑥2

𝑥1

=1

1 − |𝑉𝑎

𝑉𝑏𝑟|𝑛

3.2.

where 𝑥1and 𝑥2 are the edge point of the depletion region, 𝛼 is the ionization coefficient,

𝑉𝑎 is the applied voltage, 𝑉𝑏𝑟 is the breakdown voltage and 𝑛 is a constant range from 2 to

6.

The p-n junction breakdown voltage due to impact ionization can be numerically calculated

from [43]:

𝑉𝑏𝑟 =∈𝑠

2𝑞𝑁𝐵𝐸𝑚

2 3.3.

where 𝑁𝐵 and 𝐸𝑚 are background doping concentration and critical electric field,

respectively. The relationship between critical electric field and background doping

concentration for different doping levels is plotted in figure 3-2 and is given by:

𝐸𝑚 ∝ 𝑁𝐵1/8

3.4.

Figure 3-2: Plot for the critical electric field over different values of doping concentration

22

3.2.2. Zener breakdown

Zener breakdown mechanism is exhibited in highly doped p-n junctions with thin

depletion region. The high doping concentration and thin depletion width lead to a large

electric field under a reverse bias voltage. Electrons in the valence band gain sufficient

energy from the high electric field and jump to the conduction band by becoming free

electron through a phenomenon known as quantum mechanical tunneling. Tunneling

mechanism can be classified into two: (1) Direct tunneling and (2) Indirect tunneling, based

on the carrier transport method. Direct tunneling is referred to the flow of electrons from

valence band maximum to conduction band minimum without changing the momentum.

On the other hand, indirect tunneling is exhibited in indirect semiconductors where

conduction band and valence band momentums are not aligned. Hence, the transport

mechanism takes place only by scattering agents such as phonon or impurities.

Under the influence of large junction electric field, the probability for quantum

mechanical tunneling is higher, i.e., the more direct transition of electrons from the

conduction band to valence band or vice versa. The tunneling probability is calculated by

Wentzek-Kraners-Brillouin approximation and is expressed as [43]:

𝑇𝑡 ≈ 𝑒𝑥𝑝 [−2 ∫ |𝑘(𝑥)|𝑑𝑥𝑥2

0

] 3.5.

where |𝑘(𝑥)| is the absolute value of carrier wave vector inside barrier and 0 to 𝑥2 indicates

the classical boundaries.

The general expression for the E-k relationship is:

𝑘(𝑥) = √2𝑚∗

ћ2(𝐸𝑃𝐸 − 𝐸𝑐) = √

2𝑚∗

ћ2(−𝑞𝐸𝑥) 3.6.

where 𝐸𝑃𝐸 , 𝐸𝑐 and 𝐸𝑥 indicate potential energy, conduction band energy and electric field,

respectively. By substituting equation (3.6) in (3.5) the tunneling probability can be

expressed in terms of energy-bandgap as follows:

23

𝑇𝑡 ≈ 𝑒𝑥𝑝 [−4√2𝑚∗

3𝑞ћ𝐹𝐸𝑔

3/2] 3.7.

where 𝐸𝑔 stands for the energy-bandgap.

3.3. Mechanical stress effects on the breakdown voltage

A suitable model to describe the interaction between the electronic and mechanical

domains is essential for the design and development of breakdown voltage mechanical

stress sensors. This analytical model facilitates the study of the major associated

parameters dependencies.

The mechanical stress affects the electrical characteristics of a p-n junction with

reversible effects [48], [49]. Although this stress-dependence can result in the undesirable

performance and affects the long-term stability in microelectronic circuits, it can be

employed for the development of new sensing mechanisms as well as for the

enhancement of electronic properties of semiconductors. Material properties such as

effective mass, mobility, and carrier lifetime are also influenced by mechanical

stress/strain [50]. The prior studies conducted by various research teams modeled,

experimentally verified and proved that the bulk electron mobility is higher in strained

silicon [51], [52]. The narrowing effects of energy bandgap is another pre-dominant effects

of mechanical stress [53]. Under the influence of mechanical stress, the stress is

converted into strain within the silicon crystal lattice. The resultant strain affects the band

structure by shifting the valence band edges and splitting into two energy levels [54]–[57].

The edge of the conduction band, on the other hand, also shifts in response to the strain.

The deformation potential theory co-relates the dependency between the energy

bandgap, (𝐸𝑔) and applied mechanical stress, (𝜎) is given by:

𝐸𝑔(𝜎) = 𝐸𝑔0 + 𝛼 𝜎 3.8.

where 𝐸𝑔0 is the material bandgap at rest and 𝛼 is a property of the semiconductor material

(𝛼 = −1.5 𝑋 10−11 𝑒𝑉/𝑃𝑎 for Silicon) [18]. The material energy bandgap tends to

decrease under the influence of temperature. This is due to the increase in lattice constant

24

when the amplitude of atomic vibrations increases at higher thermal energy. The

temperature dependence of energy bandgap can be expressed as:

𝐸𝑔(𝑇) = 𝐸𝑔0(0) +𝑎𝑇2

𝑇 + 𝑏 3.9.

where 𝐸𝑔0(0) is the energy bandgap under room temperature, 𝑎 and 𝑏 are the fitting

parameters. These changes in energy bandgap lead to the variations in the maximum

electric field within the depletion region at the event of a breakdown. Therefore, the

breakdown voltage changes due to the temperature variations are calculated as per

equation (3.3) and plotted as shown in figure 3-3.

The carrier concentration can be defined as a function of energy bandgap. Therefore, by

substituting the equation (3.8) into the general expression of carrier concentration and by

further simplification it can be expressed as:

∆𝑁𝐵 = 𝑁𝐵0 (1 − 𝑒−

𝛼 𝜎2𝐾𝐵𝑇) 3.10.

where 𝐾𝐵 is the Boltzmann constant, 𝑇 is the temperature, and 𝑁𝐵0 is the carrier

concentration at rest.

The main junction breakdown mechanism in lightly-doped silicon p-n junction is

avalanche breakdown which occurs due to the impact ionization of atoms within the

Figure 3-3: Temperature dependence plot of energy bandgap and breakdown voltage

25

depletion region under high electric fields [43]. The breakdown voltage for an abrupt

junction can be estimated by equation (3.3).

Most theories assume that the ionization field is equal to the band gap energy.

However, it was found that better fit of theory to experimental data could be achieved, if

the energy of ionization considered to be slightly larger as given by [58]:

𝐸𝑚 =9.068 × 1013

√∈𝑠

𝑁𝐵1/8

𝐸𝑔3/4

3.11.

Finally, the dependence of changes in p-n junction breakdown voltage on applied stress

can be found from:

∆𝑉𝑏𝑟

𝑉𝑏𝑟0=

𝑉𝑏𝑟0 − 𝑉𝑏𝑟(𝜎)

𝑉𝑏𝑟0= 1 − (1 +

𝛼 𝜎

𝐸𝑔0)

32

𝑒−3𝐾𝐵𝑇8 𝛼 𝜎

≈ −𝛼 (3

2𝐸𝑔0+

3

8𝐾𝐵𝑇) 𝜎

3.12.

where 𝑉𝑏𝑟0 is the breakdown voltage of the unstressed structure. The normalized

expression for breakdown voltage changes varies as a function of applied stress and

temperature changes. The temperature effects on the device sensitivity is plotted for a

defined stress value of 100 kPa is shown in figure 3-4.

Figure 3-4: Temperature dependence of device sensitivity

26

The difference between the nonlinear and linearized models in equation (3.12) is

small for typical values of mechanical stress encountered at small scales (e.g., about 1%

for a 100MPa stress). The changes in breakdown voltage and energy bandgap over small

scale mechanical stress are plotted as per the theoretical model is shown in figure 3-5.

The applied mechanical stress changes the energy bandgap and breakdown voltage as a

linear function. Under different input stress values, the lowering of energy bandgap leads

to a rise in breakdown voltage due to the changes in the junction electric field and doping

concentration.

Figure 3-5: (a) Variations of energy bandgap and (b) Variations of breakdown voltage with applied mechanical stress

27

Chapter 4. Device simulation

This chapter presents the details of the simulation of a breakdown voltage sensor

and its effects on mechanical stress by Synopsys Sentaurus TCAD software. A

rectangular silicon beam with an embedded p-n junction is used as the fundamental

structure in all simulations for the simplification of analysis. The TCAD modules and its

functionalities used in the simulations are discussed in detail.

Initially, an SOI wafer with device layer and buried oxide thickness of 2𝜇𝑚 is

defined with a base material as silicon oriented along <100> direction. The wafer

specifications were chosen based on the finite element analysis and its availability.

Followed by the initialization of starting substrate, a p-n junction is embedded on the SOI

wafer by specifying the dopant profile and junction depth. Out of two breakdown voltage

mechanisms, this work focus on the effects of mechanical stress in avalanche breakdown.

Therefore, the desired breakdown voltage is set to be around -10 V, to avoid any

interference caused by the zener breakdown mechanism.

A p-n junction breakdown voltage can be controlled by the appropriate selection of

doping concentration or resistivity. The breakdown voltage of the device layer with the

boron doping concentration of 1017 𝑎𝑡𝑜𝑚𝑠/𝑐𝑚3 is estimated to be around -10 V. However,

due to the unavailability of SOI substrate as per the requirement, a blanket ion implantation

Figure 4-1: (a) Top view of the device structure with boron/phosphorus doping defining an embedded p-n junction (b) Schematic view of the structure

28

process was employed for altering the surface concentration to 1017 𝑎𝑡𝑜𝑚𝑠/𝑐𝑚3. The

depth of the blanket ion implantation profile was extended to the neutral axis of the device

layer (~1.2 𝜇𝑚). A Gaussian profile with a surface doping concentration of

1019 𝑎𝑡𝑜𝑚𝑠/𝑐𝑚3 by phosphorus dopant is specified in, the simulator for the formation of

p-n junction at a depth of 730 nm. The aluminum metal contacts with a thickness of 500

nm are designed to obtain the diode DC characteristics. The top view and schematic view

of the final device structure are shown in figure 4-1.

Synopsys Sentaurus TCAD (Technology Computer-Aided Design) tool is used for

the model and simulation of mechanical stress effects on p-n junction diode. The TCAD

simulator emulates the semiconductor processes and its characterization by solving a

partial differential equation with Newtown’s iterative method [59]. Thermal, electrical,

mechanical and optical properties of silicon material are effectively defined for the

accurate prediction of output. TCAD simulations are broadly classified into two categories:

(1) Process Simulation and (2) Device Simulation. Process simulations are performed to

simulate various semiconductors processing such as oxidation, etching, annealing, ion

implantation, and deposition by solving corresponding physical equations.

On the other hand, device simulations are used for the extraction of electrical

characteristics of different semiconductor devices such as diodes, transistors, etc., by co-

solving the Poisson’s and the continuity equations [59]. Therefore, the TCAD simulations

are effective in device performance analysis and performance optimization. The TCAD

simulation modules and its associated sections are shown in figure 4-2. The three

essential modules used in the simulations are: (1) Sentaurus structure editor (2) Sentaurus

device and (3) Sentaurus inspect.

Figure 4-2: Overall process flow of Sentaurus TCAD simulation

29

4.1. Sentaurus structure editor

The Sentaurus structure editor is a structure editing module for 2D and 3D device

geometry. The device structures can be generated and edited either by command line or

by using the user interface. A simple beam with an embedded p-n junction is designed to

model and simulate the effects of mechanical stress on breakdown voltage. Initially, a 2D

beam geometry was defined with a length of 20 µm and a thickness of 2 µm. Followed by

the geometry definition, the contact sets are defined for enabling the simulation of

electrical characteristics by current-voltage sweep. Among the two defined contacts, one

is assigned to p-silicon and the other to n-silicon. The lateral distance between the p-Si

and n-Si are defined identically to the actual design to maximize the simulation accuracy

with respect to experimental results. After the successful assignment of electrical contacts,

the dopant profile generated by the ion implantation process is set to be Gaussian. The

profile is replicated identically to the ion implantation process simulation with a background

concentration of 1017 𝑎𝑡𝑜𝑚𝑠/𝑐𝑚3 and a junction depth of 1.2 µm for p-Si whereas n-Si is

defined by a surface concentration of 1019 𝑎𝑡𝑜𝑚𝑠/𝑐𝑚3 and a junction depth of 730 nm as

shown in figure 4-3 (these values are based on the experimental parameters to be

discussed in the following chapters). The silicon crystallographic orientation was set to

[100] direction as the device responsivity is a function of crystal axis. The stress is defined

Figure 4-3: (a) 2D schematic view of the generated structure with active doping concentration (b) Generated structure in the 3D domain (c) Doping concentration profile along the silicon thickness

30

as a variable with the Gaussian distribution that has the functionality to choose the

direction and nature (tensile or compressive stress). Finally, the device geometry meshes

with an appropriate element size for better accuracy and convergence of iterations. A

global meshing is distributed across the whole structure with a maximum to minimum

element size of 5 µm to 10 nm. However, a refined mesh is defined across the doped

region essential for the device simulations with a maximum to minimum element size of

500 nm to 5 nm. The device structure was generated in both 2D and 3D domain for

analysis as shown in figure 4-3.

4.2. Sentaurus device

The Sentaurus device is a numerical semiconductor device simulator capable of

analyzing the electrical, thermal and optical characteristics of semiconductor devices. The

simulator has the functionality of analyzing the device behavior in 2D and 3D domains. A

typical Sentaurus device simulation module consists of 6 sections such as (1) Input/Output

file sections, (2) Electrode section, (3) Physics section, (4) Plot section, (5) Math section

and (6) Solve section. In addition to that, the material parameter file needs to be selected

and modified accordingly depends on the nature of the analysis. To simulate the

mechanical stress effects on the p-n junction breakdown, the silicon parameter file is

modified with additional details such as crystal system, elasticity matrix, and deformation

potential under lattice parameters [59].

The Sentaurus structure editor module generates the grid file (TDR format) that

contains the device geometry, contact and mesh definitions. This file is called into the

Sentaurus device module as an input file along with the parameter files for the listed

materials. The piezo file within file section is explicitly specified to read the stress values

by the structure editor. Followed by the completion of device simulation, the generated

output file containing resulting voltages, currents, charges, temperature, etc are pre-

defined by the keyword current. The electrode section is to specify the list of electrical

device contacts with initial boundary conditions such as initial bias voltage or contact

resistance. The device contacts for p-Si and n-Si are designed under this section with an

initial voltage bias equals 0V. The physical models to be used in the simulation can be

activated by the physics section.

31

A proper definition of device physics is inevitable for the accurate prediction of

device electrical characteristics. In this simulation, three major types of generation-

recombination physics are activated such as Shockley-Read-Hall recombination, band-to-

band tunneling, and avalanche generation to accurately simulate the carrier movement

from valence band to conduction band or vice-versa. The mechanical stress effects on the

silicon band structure and carrier density by the deformation potential models. This model

activates the strain-induced shifts in the conduction band and valence band edges as well

as band-curvature changes. The mechanical stress values pre-defined in the structure

editor module are used for the analysis and computation of energy-band shifts and

curvature changes.

The plot section is to specify the list of variables to be plotted for further

visualization. In the simulation, parameters such as energy-bandgap, mobility, active

doping concentration, and electron/hole effective mass are plotted against the different

Figure 4-4: (a) Active doping concentration distribution of device structure in 2D (b) Effective bandgap plot across silicon depth through p-n junction (c) & (d) Hole and electron mobility vs silicon depth

32

depth of silicon layer to investigate its effects across device surface and p-n junction as

shown in figure 4-4. The math section controls the simulator numeric by the definition of

iterations number and error control values. The default setting is used for better accuracy

and minimizing computational power. Finally, the solve section specifies the input voltage

or current sweep settings with step size and iteration count. A quasi-stationary voltage

sweep is performed from 0V to -10V for the reverse bias characteristics of the p-n junction

diode. The same step is repeated with a voltage sweep from 0V to 3V to estimate the

diode forward bias characteristics. All the electrical device simulations were performed by

defining thermal nodes across the device boundary and setting the temperature to 300K

by minimizing the temperature effects on electrical characteristics.

4.3. Electrical breakdown simulation

The electrical breakdown simulations are more challenging to perform due to the

sudden increase in current for small changes in voltage and results in convergence issues.

This can be resolved with good mesh strategy as well as choosing the proper breakdown

simulation analysis. There are several methods available for the electrical breakdown

simulation such as (1) Approximate breakdown analysis, (2) Ionization integrals with

carrier analysis, (3) External resistor method, (4) Voltage-to-current boundary condition

(BC) switching method, (5) Continuation method and (6) Transient method [59]. Each of

these methods has its own merits and demerits. The voltage-to-current boundary

switching method has used in this study due to its flexibility and capability in analyzing

complicated curve shapes.

The voltage-to-current boundary condition switching method works by applying

boundary condition (BC) switch from the voltage BC to current BC. A switching point is

defined in the simulation beyond which the current increases monotonically. It is likely to

encounter iteration convergence issue if the switch point is defined non-monotonic. The

reverse and forward bias characteristics of the p-n diode are performed by two individual

voltage sweep at which the switching points are defined as -9V and 0.7V respectively. The

obtained reverse characteristics curve indicates a sudden rise in current at -9.2V and

estimated to be the breakdown point as shown in figure 4-5(a). The device forward bias

simulation result shown an ideal diode characteristic with a turn-on voltage at 0.7V as

shown in figure 4-5(b).

33

The estimated breakdown voltage from simulation converges with the theory for a

background doping concentration of 1017𝑎𝑡𝑜𝑚𝑠/𝑐𝑚3.

(a)

(b)

Figure 4-5: (a) Sentaurus device simulation plot of p-n junction under reverse biased (b) Sentaurus device simulation plot of p-n junction under forward biased

34

4.4. Simulation of mechanical stress effects on the breakdown voltage

Mechanical stress can influence work-function, bandgap, effective mass, carrier

mobility and leakage current in microelectronic devices [53], [60], [61]. The mechanical

distortion in semiconductor structures can result in changes in energy-band structure and

carrier mobility. This phenomenon has been studied in the past and modeled for the

computation of changes in band structure by deformation potential theory [62]. The

existing model for the deformation potential theory consider the changes in energy level

caused by the deformation of the lattice as a linear function of strain [63]. For silicon

material, the energy-band structure is defined with three sub-valleys for electrons (in

conduction band) and two sub-valleys for holes (in valence band) under the material

parameter file [64]. The non-linear effects of the carrier energy levels to shear strain are

also taken into account for the accurate computation of model [40]. The energy band

changes for each conduction band and valence band sub-valleys are computed based on

the input stress tensor.

Deformation potential model is activated by the keyword DeformationPotential

specified under the piezo section of the Sentaurus device module. Initially, the device

simulation coordinate system needs to be specified with respect to crystallographic

directions using the X and Y vectors [59]. Followed by the modification of silicon parameter

file by defining the number of sub-valleys for conduction band and valence band to be 3

and 2 respectively. The deformation potential values for carriers at each sub-valleys are

entered in the fields DC[i], DV[i], DC2[i] and DV2[i] [65]. Elasticity modulus is also defined

under the same file by its default unit in 𝑐𝑚2/𝑑𝑦𝑛. Similar to the deformation potential

model, the strain-induced mobility model is also activated by using a keyword Subband

under the piezo section. The mobility model can be activated separately using the prefix

‘e’ and ‘h’ for electrons and holes respectively.

Followed by the modification of silicon parameter file, the Sentaurus device

simulation is performed for different values of mechanical stress applied parallel and

perpendicular to the p-n junction. The applied stress can be defined as either tensile or

compressive, assigned by the sign convention. The positive sign indicates tensile stress

and the negative sign indicates compressive stress. Initially, the device structure editor is

modified by defining the stress ranges from -2 MPa to 2 MPa oriented parallel to the p-n

35

junction (x-axis) with a step size of 0.2 MPa. A quasi-stationary voltage sweep is

performed for each stress value to analyze the effects of stress on breakdown voltage.

The changes in breakdown voltage are obtained in reference to the current-voltage

characteristics when the device is applied with zero stress at the same current value as

shown in figure 4-6.

The primary analysis from the stress simulation is that the breakdown voltage

increases for compressive stress and decreases for tensile stress when the input stress

orientation is parallel to the p-n junction. The changes in breakdown voltage response are

linear with different slope indicates the difference in sensitivity according to the nature of

applied stress. The sensitivity of breakdown voltage changes to tensile stress (-

106 µ𝑉/𝑀𝑃𝑎) is estimated to be higher as compared to compressive stress

(40.5 µ𝑉/𝑀𝑃𝑎). All the simulations are carried out by defining the silicon channel crystal

orientation along [100] direction.

Figure 4-6: Mechanical stress simulation results of breakdown voltage changes when applied input stress is parallel to the p-n junction

36

Similarly, the simulation is repeated with the same device design, stress magnitude

but with a different orientation. The applied mechanical stress is defined to be oriented

perpendicular to the p-n junction and the simulated changes in breakdown voltage are

plotted as shown in figure 4-7. The simulated response is linear for the same stress values

as before and the overall changes in breakdown voltage are observed to be higher

compared to when the stress is applied parallel to the junction. The breakdown voltage

sensitivity is estimated to be higher for compressive stress (-180 µ𝑉/𝑀𝑃𝑎) and slightly

lower for applied tensile stress (118 µ𝑉/𝑀𝑃𝑎). The sensitivity is appeared to be higher for

tensile stress when exerted input stress is parallel to the p-n junction. However, the

sensitivity goes higher for compressive stress when the applied stress is perpendicular to

the junction. In addition to that, the breakdown voltage tends to decrease with

perpendicular compressive stress whereas increases with the parallel compressive stress.

Figure 4-7: Mechanical stress simulation results of breakdown voltage changes when applied input stress is perpendicular to the p-n junction

37

The changes in simulated breakdown voltage are found to be linear for the applied

mechanical stress ranges from -2 MPa to 2 MPa. An additional simulation was performed

to analyze the device response at higher magnitudes of stress. Therefore, the simulation

is repeated with input stress ranging from -250 MPa to 250 MPa applied perpendicular to

the p-n junction and the changes in breakdown voltage are plotted as shown in figure 4-

8. A non-linear device response is observed at higher values of applied stress. The device

is appeared to be linear for smaller stress ranging from -20 MPa to 20 MPa regardless of

tensile or compressive stress. As the applied stress enters in the range of 100 MPa the

device responsivity changes by the nature of input stress. Higher compressive stress

results in a further increase in the device sensitivity whereas higher tensile stress

maintains the breakdown voltage changes constantly and then decreases.

Figure 4-8: Non-linear breakdown voltage response for higher applied stress from -250 MPa to 250 MPa

38

In order to perform the actual device sensitivity estimation and performance

analysis, the mechanical stress values for different input accelerations are used in the

device simulation. The theoretically estimated stress values, verified by finite element

analysis for different input accelerations are used for the comparison between theoretical

and simulation models. This is used for analyzing the changes in breakdown voltage and

project the device sensitivity and performance analysis. The simulated response is then

compared with the physical model as per equation (3.11) and plotted the response as

shown in figure 4-9.

The deviation between theory and simulation is ~15% and can be explained by the

assumptions made in the physical model. The theoretical model was developed by

assuming the p-n junction temperature to be constant, whereas the actual junction

temperature varies during the current-voltage sweep in the simulation. In addition to that,

the background doping concentration of the device layer follows a Gaussian profile and it

is assumed to be constant in the numerical model for the simplicity of calculation. These

factors contribute to the discrepancies in comparison plot.

Figure 4-9: Comparison of simulated breakdown voltage changes with theoretical model

39

Chapter 5. Device Fabrication

The breakdown voltage sensor prototypes were fabricated by bulk micro-

machining process at the 4D labs and SFU Engineering Science Cleanroom Facility

(ENSF). Some of the major processes such as ion implantations, deep reactive ion etch

(DRIE) and low-pressure chemical vapor deposition (LPCVD) were carried out at external

facilities. A 5 mask process flow was designed and developed with a photolithography

resolution (contact printing) of 1𝜇𝑚. Each process step was optimized by altering

equipment parameters as well as process conditions to minimize the process deviations

and enhance mask-to-wafer critical dimensions. The major phases of process flow

include: 1) boron blanket doping of SOI substrate to alter device resistivity, 2) selective

phosphorus doping for the p-n junction formation at the desired depth, 3) vias and metal

interconnections for the electrical isolation and electrical routing, 4) patterning device layer

Figure 5-1: Major steps in the device fabrication process flow

40

for the definition of resonator body, release holes and transduction gaps, and 5) final

releasing of mechanical structure by removing the sacrificial oxide. The summary of the

fabrication process flow is shown in figure 5-1.

The process requirements and specifications were set by the equipment limitations

to ensure maximum yield with minimum particle contamination. This approach facilitated

to incorporate multiple design variations with high repeatability. The process details will

be elaborated by the following sections of this chapter.

5.1. Starting substrate

A 4” Silicon-on-insulator (SOI) wafer with suitable parameters was chosen for the

bulk micromachining process. A typical SOI wafer consists of three layers such as 1)

device silicon, 2) buried oxide (BOX), and 3) handle layer. The device silicon is made out

of high quality single crystalline polished silicon with an appropriate doping concentration

that translates to electrical resistivity. The buried oxide (BOX) is a thermally grown silicon

dioxide (SiO2) layer sandwiched between device silicon and handle layer, serves the

purpose of electrical isolation and the sacrificial layer. The SOI substrate is manufactured

by the direct wafer bonding of above mentioned three layers. A major reason for the wide

usage of SOI wafers in the MEMS industry is due to its capability for the design of high-

aspect-ratio structures by the development in deep reactive ion etching (DRIE)

techniques.

A finite element simulation was performed in COMSOL for the extraction of basic

device parameters such as resonant frequencies, electrostatic pull-in voltage, and p-n

diode breakdown voltage attributes to the selection of substrate. The device silicon

thickness and electrical resistivity were selected optimally for the desired resonance

modes, junction depth, and series resistance. Therefore, the selected device layer was

prime quality silicon at (100) orientation with a thickness of 2±0.5 µm and device resistivity

of 1-20 Ohm-cm. The silicon orientation was chosen based on the device simulations

using Synopsys Sentaurus TCAD to yield higher sensitivity. Another important

consideration in the selection of substrate was buried oxide thickness. This determines

the device electrostatic coupling performance and release condition. A thermally grown

silicon dioxide (SiO2) of 2 µm±10% was used as the sacrificial layer for the final releasing

41

of the structure. Table 5-1 summarises the specifications of the substrate used in the

process flow.

5.2. Blanket doping

5.2.1. Doping

The device silicon resistivity is one of the crucial parameters that determine the

performance of a breakdown voltage sensor. As per the finite element analysis and device

simulations, the estimated device resistivity was in the range of 0.1-0.2 Ω-cm which

translates to a surface concentration of 1017𝑎𝑡𝑜𝑚𝑠/𝑐𝑚3. Due to the unavailability of the

substrate with required device resistivity, wafers were purchased and altered the electrical

resistivity by blanket doping using the ion implantation process. There are several

methods available for doping such as 1) diffusion, 2) ion implantation, and 3) doped

polysilicon deposition. Among all the available methods, ion implantation was chosen due

to its capability in the precise control of junction depth formation and surface

concentrations. The ion implantation was carried out at INNOViON Corporation, San Jose,

California [66].

The major process parameters associated with the ion implantation process are 1)

ion energy, 2) ion dose, and 3) tilt angle. The process attributes to determine the doping

profile and was estimated through process simulations as well as theoretical calculations.

The initial SOI substrate with corresponding specifications was emulated in the simulator

and adjusted the ion implantation energy, dose, and tilt angle to obtain a background

concentration of 1017𝑎𝑡𝑜𝑚𝑠/𝑐𝑚3 at 1.2 µm deep from the surface. A trivalent impurity such

as Boron was used as the ion species to create an electron deficiency thereby lowering

Table 5-1: Summary of SOI wafer parameters

Diameter Orientation Device

thickness

(µm)

Device

resistivity

(Ω-cm)

BOX

thickness

(µm)

Handle

thickness

(µm)

Handle

resistivity

(Ω-cm)

100 mm P/B (100) 2±0.5 1-20 2±10% 400±15 1-20

Table 5-2: Summary of blanket ion implantation process parametersTable 5-3: Summary of

SOI wafer parameters

Diameter Orientation Device

thickness

(µm)

Device

resistivity

(Ω-cm)

BOX

thickness

(µm)

Handle

thickness

(µm)

Handle

resistivity

(Ω-cm)

100 mm P/B (100) 2±0.5 1-20 2±10% 400±15 1-20

42

the resistivity of p-type device silicon layer [67]. The table 5-2 summarizes the ion

implantation process parameters obtained from the simulator.

5.2.2. Annealing/Oxidation

In the ion implantation process, high energy boron ions are bombarded with silicon

atoms at the lattice of device layers, and therefore damaging the crystalline structure. The

primary crystalline damage can be restored back to pre-implant condition with high thermal

treatment process known as annealing. There are several annealing techniques available

such as 1) furnace annealing, 2) rapid thermal annealing, 3) laser annealing, 4) flash

annealing, and 5) spike annealing depends on the applications. Furnace annealing was

used in this process for the dopant drive-in and thermal growth of oxide.

The two major attributes of annealing are temperature and time. With the help of

process simulations, the optimal temperature and time were able to determine for the

desired junction depth, surface concentrations, and oxide thickness. Based on the process

simulations, a thermal treatment of ion implanted SOI substrate at 1000 °C for 35 mins

leads to a junction depth of 1.2 µm and grow 250 nm thick silicon dioxide as shown in

figure 5-2. The doping profile of device silicon followed by the drive-in process is

graphically plotted in figure 5-2. The dopant junction depth was theoretically calculated to

validate the simulation results using the general expression given by:

𝐶(𝑥𝑗) = 𝐶𝑝𝑒𝑥𝑝 (−(𝑥𝑗 − 𝑅𝑝)2

2𝛥𝑅𝑝2 ) 5.1.

Table 5-2: Summary of blanket ion implantation process parameters

Implanter type Specie Dose

(atoms/cm2)

Energy (keV) Tilt

6200 Boron (11) 5.0E+13 150 0°

Table 5-4: Summary of blanket ion implantation process parameters

Implanter type Specie Dose

(atoms/cm2)

Energy (keV) Tilt

6200 Boron (11) 5.0E+13 150 0°

43

where 𝐶(𝑥𝑗) is the dopant concentration at junction depth 𝑥𝑗; 𝐶𝑝 is the peak surface

concentration; 𝑅𝑝 is the mean of Gaussian distribution and 𝛥𝑅𝑝 is the standard deviation

of Gaussian distribution [68].

The four-point probe measurement of the device silicon layer has been measured

and verified on the change in device resistivity from 1-20 Ohm-cm to 0.1-0.2 Ohm-cm.

5.3. Selective doping

The selective doping is the crucial process step as it is responsible for the creation

of a p-n junction and thereby setting baseline device performance. The thermally grown

oxide from the blanket dopant annealing was patterned to create an opening and used as

a mask for selective annealing. The n-doped region was formed by phosphorus doping

Figure 5-2: (a) Initial SOI substrate doping with Boron ions (b) Diffusion of implanted ions to a junction depth of 1.2 µm by thermal growth of SiO2 (c) Synopsys Sentaurus TCAD simulation of blanket ion implantation (d) Post-annealing plot of surface concentration

44

using an ion implantation technique followed by a thermal diffusion process. The p-n

junction depth and the surface concentration of the n-doped region are controlled by the

thermal drive-in parameters such as temperature and time. The process simulations and

theoretical models are used for the estimation of drive-in conditions.

5.3.1. Photolithography optimization

The quality and robustness of the photolithography process attribute to the

accuracy of critical dimension transfer from the mask to wafer. The contact printing method

was used for pattern transfer due to its ability to achieve higher resolution, less expensive

nature and resource availability [69]. The proposed MEMS resonators were designed with

a minimum critical dimension (CD) of 1µm; whereas a typical contact printing resolution is

limited to 2 µm. This raised the challenge in the development of 1µm line or space and

patterns it.

An ABM manual aligner system [70] with split-field dual CCD camera alignment is

used for the process optimization. All the process runs are performed using blanket silicon

wafer by changing the exposure time and fixing UV dosage as well as energy. Initially, the

pilot wafers are cleaned by standard RCA process and thermally grown a thin oxide layer

of 250 nm thickness. The wafers are then coated with HMDS and pre-baked at 150 °C to

improve the photoresist adhesion and prevent resist lift-off issues. Followed by the HMDS

coating, a positive tone photoresist (AZ703) [71] is spin coated over the wafer at 4500 rpm

for 60 seconds and measured with a thickness of 950 nm. Subsequently, wafers are baked

on a hotplate at 90 °C for 60 seconds for the partial evaporation of solvents and promote

adhesion. The pre-exposure baking is also done on a hotplate at 110 °C for 60 seconds

as per recommendation by the photoresist vendors for the enhancement of photoresist

stability. The next is to expose the photoresist using a patterned mask on the mask aligner.

The exposed photoresist is then baked on a hotplate at 110 °C for 60 seconds prior to

development. Afterward, a photoresist developer (AZ300 [72]) is used with slight agitation

to dissolve the photoresist from the UV exposed region. The wafers are now hard-baked

at 120 °C for 2 mins for the final evaporation of solvents and make the resist more durable.

The masking steps have now completed and proceed with the microscopic inspection and

CD measurements. The summarized process flow and associated process conditions

have been listed in figure 5-3.

45

The optimization of etching parameters is as important as photolithography to

minimize the undercut and achieving 1 µm critical dimension. The buried oxide etchant

(BOE) are commonly used isotropic etchant for the removal of silicon dioxide. The usage

of the isotropic etchant is not ideal for the definition of smaller features. Hence, a

combination of reactive ion etching (RIE) and wet etching are adapted by minimal undercut

and smoother silicon surface. The Sentech Etchlab 200 RIE [73] equipment was used for

the removal of SiO2 with vertical side walls by high energy plasma and the etch rate is

controlled by the gas composition. The RF power, chamber pressure and gas composition

(CHF3/O2) used in the process optimization are summarized as shown in table 5-3.

Followed by RIE, a hard bake at 120 °C for 60 seconds is inevitable to improve the

photoresist chemical resistance to wet etchants. The wafers are then wet etched using

BOE for 90 seconds to confirm the removal of SiO2. The hydrophobic nature of silicon

towards de-ionized water confirms the completion of oxide etching. An elemental analysis

(EDX) along with scanning electron microscopy (SEM) is done for the surface evaluation

as shown in figure 5-4. After the completion of etching, the remaining photoresist is then

Figure 5-3: Summary of photolithography process flow and associated process conditions.

Table 5-5: Summary of RIE and BOE etch process parameters

46

stripped away using acetone soak for 5 minutes and isopropyl alcohol (IPA) rinse for 60

seconds.

5.3.2. N-region doping

The photolithography and etch parameters are optimized for 1 µm feature size with

pilot wafers and proceed with main SOI wafers. Firstly, the thermally grown oxide during

blanket implantation annealing is patterned as per optimized masking and etching

process. The metrology inspections are done after every single process to ensure the

process specifications are met. The wafers are then packaged and shipped to INNOViON

corporation facility for the ion implantation process.

Table 5-3: Summary of RIE and BOE etch process parameters

Reactive ion etch (RIE) Buffer oxide etch (BOE)

Power

(watts)

Pressure

(mTorr)

CHF3/O2

(sccm)

Etch rate

(nm/min)

Temperature

(°C)

Time

(seconds)

Etch rate

(nm/min)

100 50 50/5 17.5 25 90 42

Figure 5-4: (a) EDX analysis on silicon confirms the completion of oxide etch (b) EDX analysis on silicon dioxide shows the presence of oxide.

Table 5-6: Summary of n-type ion implantation process parametersTable 5-7:

Summary of RIE and BOE etch process parameters

Reactive ion etch (RIE) Buffer oxide etch (BOE)

Power

(watts)

Pressure

(mTorr)

CHF3/O2

(sccm)

Etch rate

(nm/min)

Temperature

(°C)

Time

(seconds)

Etch rate

(nm/min)

47

The n-doped regions are formed by the doping of pentavalent impurities such as

phosphorus by creating electron sufficiency. Similar to blanket doping, the main process

parameters such as ion energy, dosage, and tilt are estimated by the process simulations

as well as theoretical models. These parameters are then adjusted to obtain a target

specification of 1019𝑎𝑡𝑜𝑚𝑠/𝑐𝑚3 as shown in table 5-4. The implantation is done in two

steps for the deeper penetration of ions and to achieve higher surface concentration as

shown in figure 5-5.

The ion implanted SOI wafers are then processed in buffer oxide etchant (BOE) to

strip the masking oxide and performed a microscopic inspection to inspect for any surface

abnormality. A contrast difference is observed across the doped region as shown in figure

Table 5-4: Summary of n-type ion implantation process parameters

Implanter

type

Specie Dose

(atoms/cm2)

Energy (keV) Tilt

6200B Phosphorus

(31)+

1.0E+12 40 0°

6200B Phosphorus

(31)+

5.0E+14 20 7°

Figure 5-5: (a) SOI wafer before phosphorus ion implantation (b) SOI wafer after phosphorus ion implantation

Table 5-8: Summary of n-type ion implantation process parameters

48

5-6. Followed by the metrology inspections, the wafers are then processed by thermal

annealing for the diffusion of dopants to desired junction depth and for the electrical

activation of ions.

The annealing temperature and time are adjusted by the process simulations for a

target junction depth of 730 nm and to grow a 30 nm silicon dioxide prior to the deposition

of the passivation layer. The final estimated doping profile of p-n junction is plotted as

shown in figure 5-7.

Figure 5-6: (a) Ion-implanted contrast difference on alignment pattern (b) Ion implanted contrast difference on breakdown voltage sensor region

Figure 5-7: (a) Ion-implanted contrast difference on alignment pattern (b) Ion implanted contrast difference on breakdown voltage sensor region

Figure 5-7: Synopsys Sentaurus TCAD simulation plot of p-n junction doping profile

49

5.4. Passivation

The current-voltage characteristics of p-n junction diode are important for the

breakdown voltage sensing mechanism. The device sensitivity performance is influenced

by the reverse leakage current and stability of electrical characteristics. The exposed p-n

junction can be affected by the surface-recombination phenomenon and results in an

increase in leakage current. To minimize the effects of recombination, a passivation layer

is coated across the surface and improved the diode characteristics. The thermally grown

silicon dioxide is commonly used passivation layer in microelectronic devices, whereas

this is not suitable for the proposed process flow. The passivation layer should be able to

withstand the final releasing step. The vapor releasing is done by the exposure of the

surface to hydrofluoric acid and hence silicon nitride is selected as the passivation film.

The silicon nitride films are deposited by the chemical vapor deposition (CVD) from

dichlorosilane (SiH2Cl2) and ammonia (NH3) with excellent conformality and composition.

However, the higher internal stress of film affects the device reliability and long-term

usage. This issue can be resolved by the decrease in NH3/SiH2Cl2 gas ratio and by the

deposition of silicon-rich silicon nitride SiNx. The ion implanted wafers are deposited with

low-stress silicon nitride at the nanoFAB facility at the University of Alberta. A thin film of

200 nm is deposited by regulating the deposition process in a gas flow ratio of 60:10

(SiH2Cl2: NH3) at a temperature of 835 °C and a chamber pressure of 200 mTorr as shown

in figure 5-8. The film inspection followed by the LPCVD process confirms the deposition

of 190 nm thick silicon nitride with an average tensile stress of 110 MPa. The summarized

LPCVD process parameters are consolidated in table 5-5.

Table 5-5: LPCVD silicon nitride process parameters

SiH2Cl2: NH3 Temperature

(°C)

Pressure

(mTorr)

Time (mins) Deposition

rate (nm/min)

60:10 835 200 60 3.1

Table 5-10: LPCVD silicon nitride process parameters

SiH2Cl2: NH3 Temperature Pressure Time (mins) Deposition

50

5.5. Metallization

Metallization is the next step in the process flow, followed by the deposition of the

passivation film. The overall process is broadly divided into two steps: 1) via formation and

2) metal deposition. The via formation is essential for the electrical isolation between the

metal pads as well as to improve the adhesion between the metal and silicon surface.

Metal film facilitates access to the different device region used for electrical testing and

characterization.

5.5.1. Via formation

The vias are patterned by the masking step followed by the etching of passivation

silicon nitride and silicon dioxide underneath to access silicon layer. Initially, silicon nitride

is etched by reactive ion etching (RIE) for vertical side walls by minimizing the variations

in critical dimension. The RIE is performed at the 4D labs facility using the standard etch

recipe with parameters as shown in table 5-6 [74]. After the removal of silicon nitride, SOI

wafers are hard baked at 120 °C for 60 seconds prior to silicon dioxide etching to improve

the photoresist adhesion. The wafers are then dipped in BOE for 60 seconds for the

Figure 5-8: (a) SOI wafers before LPCVD silicon nitride deposition (b) SOI wafers after LPCVD silicon nitride deposition

Table 5-11: RIE parameters of LPCVD Si3N4 etch

Figure 5-9: (a) SOI wafers before LPCVD silicon nitride deposition (b) SOI wafers after LPCVD silicon nitride deposition

51

removal of SiO2 as shown in figure 5-8. Followed by the inspections, the photoresist is

stripped by using acetone rinse for 5 mins and IPA dip for 60 seconds.

5.5.2. Metal deposition

The metals used in SOI wafers are carefully selected to ensure good electrical

performance. The major factors taken into consideration for the choice of materials are:

1) vapor HF compatibility 2) sheet resistivity 3) contact resistance and 4) ease of wire

bonding. The Aluminum was the first choice of preference due to its wide usage in

microfabrication and good conductivity. However, there are few challenges associated

with its usages such as reliability problems and spiking. In addition to that, there are many

reported cases in which it is attacked by vapor HF. To address these issues, an alloy of

aluminum with 1% of silicon is used with an additional hard metal layer using nickel. The

Table 5-6: RIE parameters of LPCVD Si3N4 etch

CF4/O2

(sccm)

Power (W) Pressure

(mTorr)

Time (mins) Etch rate

(nm/min)

30/2 80 30 5.25 42

Figure 5-9: (a) Graphical representation of via formation (b) Microscopic inspection after patterning vias.

Table 5-12: RIE parameters of LPCVD Si3N4 etch

CF4/O2

(sccm)

Power (W) Pressure

(mTorr)

Time (mins) Etch rate

(nm/min)

30/2 80 30 5.25 42

52

Al alloy is known best for the improved silicon interface and enhancing metal-silicon

electrical contact. The nickel is used due to its masking ability to vapor HF and hence used

as a protective film for the aluminum pads.

The surface quality of the metal-silicon interface is directly translated to the diode

performance and hence a standard RCA clean is performed on SOI substrate prior to the

metal deposition. The lift-off process is used for the metal deposition due to its advantages

on slower turn-around time and cheaper process. The RCA cleaned SOI wafers are then

spin-coated with AZ703 photoresist and patterned using a metal mask to define the

bonding pads. The developed wafers are then processed with plasma stripper at 50 Watts

power and 280 mTorr pressure under O2 ambient to clean exposed region by the removal

of photoresist residue. Afterward, the SOI wafers proceed for the metal deposition using

thermal evaporation technique. The evaporation was chosen over sputtering due to its

ability for depositing metal at highest purity at lower pressure. The process initiated by the

deposition of Al using Al0.99Si0.1 pallets at 5 µTorr pressure. The deposition rate was

monitored in real-time using an integrated crystal oscillator to obtain a thickness of 110

nm. Upon the completion of Al deposition, Ni pallets are heated by passing current to the

filament and deposited to a target thickness of 220 nm. Both metal depositions are carried

out in the same chamber to minimize the formation of native oxide between metal stacks.

The wafers are then soaked in acetone for 10 mins to remove the deposited metal over

photoresist with ultrasonic agitation followed by IPA rinse to wash off the residue as shown

in figure 5-10.

The processed SOI wafers are now patterned with metal pads and accessible for

electrical testing. The basic testing such as current-voltage sweep is performed across the

wafer for the analysis of metal-silicon contact and p-n junction characteristics. The metal

to the n-doped region is found to be non-ohmic from the IV sweep as shown in the figure

5-11. Sintering is one of the techniques to improve the non-ohmic nature between metal-

Figure 5-10: Graphical representation of metal deposition

53

silicon interfaces. This was not performed as the measured p-n diode characteristics meet

the target specifications with reverse leakage current in the range of nanoampere.

5.6. Silicon patterning

A Deep Reactive-Ion Etching (DRIE) process was used for the pattern transfer of

the resonant body, the definition of etch holes as well as geometry and to create isolation

from device-to-device. The process was done in two phases: 1) reactive-ion etching (RIE)

of the top passivation silicon nitride and silicon dioxide to access the device silicon 2) DRIE

of device silicon with a buried oxide (BOX) as stopping layer as shown in figure 5-12. The

DRIE process is highly selective to the masking photoresist with high aspect ratio. This

enables the definition of vertical sidewalls minimizing the undercut.

Higher aspect ratio and anisotropic profile can be obtained by fine-tuning the DRIE

process parameters such as plasma source power, chamber pressure and controlling the

gas flow rate per cycle. The high power and low-pressure conditions are ideal for the better

anisotropic profile, however smaller pressure slower the etch rate. The Bosch process is

a high-aspect ratio DRIE plasma etching process used for the vertical sidewall. This

process works based on the cyclic isotropic etching with a fluorocarbon-based protective

film coated on the side wall. The process executes in two cycles: a) silicon etching by SF6

Figure 5-11: IV characteristics of N-contact

Figure 5-12: IV characteristics of N-contact

54

gas flow and protective coating definition by C4F8. The thickness of the protective coating

is optimized by controlling the gas flow to prevent breaking the film during the process.

Followed by the completion of silicon DRIE with additional 10% over-etching the

masking photoresist was stripped off and inspected under SEM as shown in figure 5-13.

The images confirm the completion of the silicon etches with excellent sidewall profile.

Figure 5-12: (a) RIE of Si3N4 and SiO2 (b) DRIE of device silicon

Figure 5-13: (a) RIE of Si3N4 and SiO2 (b) DRIE of device silicon

Figure 5-13: SEM image of 2 µm pitch pattern (left) SEM image of 3 x 3 µm etch hole (right)

55

5.7. Release

Followed by the silicon DRIE and inspection the SOI wafers are processed for the

final releasing step. The release step is to remove the buried oxide (BOX) layer

underneath the main structure. Prior to the final release, a metal contact to the substrate

needs to be established for the device testing and characterization.

5.7.1. Backside metal deposition

The main purpose of backside metal deposition is to make a contact to the bottom

handle layer for electrostatic testing. The SOI wafers followed by the DRIE process were

coated with photoresist on the front-side as a protective layer by spin coating. A

combination of dry etching and wet etching were performed on the backside for the

removal of passivation silicon nitride layer and oxide respectively. The SOI wafers were

rinsed in DI water and the hydrophobic nature confirms the completion of etching. Wafers

were then deposited with 200 nm of Aluminum by thermal evaporation process by

establishing a backside contact as shown in figure 5-14.

5.7.2. Vapor HF

The final processed SOI wafers were diced into dies of 5 x 5 mm using a saw

cutter. Each sample was soaked in microposit remover 1165 for 10 minutes with low power

ultrasonic agitation for the removal of photoresist. It was then followed by oxygen plasma

to remove any organic residue from the prior processes and proceeded to vapor HF.

Figure 5-14: Process schematic of SOI wafer after backside metal deposition

Figure 5-15: Process schematic of SOI wafer after backside metal deposition

56

The major challenges associated with micro-structure releasing are sticking to the

sacrificial layer and damage to metal pads. The vapor HF method is been widely used in

the MEMS industry due to its capability in minimizing the stiction and end-point detection

of the released structure. The basic working mechanism behind the process is based on

the evaporation of HF 48% solution by generating a saturated HF environment. The idonus

vapor HF etcher [75] was used for the releasing process consist of a heating sample holder

at which the samples were mounted using electrostatic force. The oxide etches rate can

be controlled by the sample temperature and the gap between the sample and the HF

solution [76]. The optimum temperature of the process was estimated to be 35 ºC by

experimental analysis. Lower process temperature results in the water condensation

generated as the by-products of the chemical reaction whereas higher temperature (above

40 ºC) create pin-holes in silicon nitride film and metal peeling issue as shown in figure 5-

15.

The LPCVD silicon nitride was found to be swollen up as it was exposed longer to

vapor HF and falls back to baseline by further heat treatment above 250 ºC. This was

identified as one of the key reason to affect the metal to silicon contact quality. The bulging

of silicon nitride lift-up the metal pads beneath it and disconnects the metal

Figure 5-15: Optical image of the sample after VHF at 40 ºC for 20 minutes

Table 5-13: VHF parameters of silicon release

57

interconnections through vias. The issue was resolved by limiting the VHF cycle to every

3 minutes followed by thermal treatment at 180 ºC to prevent the formation of water

condensation. A lateral dimension of 15 µm BOX was removed by VHF in 30 minutes and

confirmed the releasing by optical inspection as shown in figure 5-16. The consolidated

vapor HF parameters for releasing step is summarized in table 5-7.

SEM inspection of the fully released samples was carried out for high-resolution

imaging and observe any possible bending of the structure due to internal stress as shown

in figure 5-17.

Table 5-7: VHF parameters of silicon release

Etch

temperature

(ºC)

Time per

cycle (mins)

# of cycles Heat

treatment

temperature

(ºC)

Heat

treatment

time (min)

35 3 10 180 1

Figure 5-16: Optical image of the sample before and after VHF

Table 5-14: VHF parameters of silicon release

Etch

temperature

(ºC)

Time per

cycle (mins)

# of cycles Heat

treatment

temperature

(ºC)

Heat

treatment

time (min)

58

5.8. Packaging

The 44 pins ceramic quad flat non-leaded package was used for packaging, in

which the released sample was mounted using conductive double-sided carbon tape. The

wedge to wedge wire bonder (K&S 4500 series) was used to establish interconnections

using a thin gold wire (diameter = 50 µm). The major challenge associated with gold to

nickel wire bonding is the stiction to metal pads due to the hardness of metal pads. The

wire bonding process parameters such as force and power were adjusted for the reliable

and repeatable bonding process. The optimized wire bonding process parameters are

summarized as per table 5-8.

Figure 5-17: SEM image of the final released sample

Table 5-15: VHF parameters of silicon release

Figure 5-18: SEM image of the final released sample

Table 5-8: Wire bonding parameters

Bond Temperature (ºC) Time Power Force

1st bond (Nickel) 120 8 3.5 9

2nd bond (Gold) 120 8 3.5 5

Table 5-16: VHF parameters of silicon release

Bond Temperature (ºC) Time Power Force

59

The final released device is mounted on top of conductive carbon tape and wire

bonded to a ceramic package as shown in figure 5-18. Followed by the completion of the

packaging process, the device proceeds for testing and characterization.

Figure 5-18: Final released and packaged device

Figure 5-19: Final released and packaged device

60

Chapter 6. Device design and characterization

This chapter discusses the design and analysis of the fundamental structure that

was designed and fabricated to establish the proof-of-concept. The designed breakdown

voltage senor was tested and characterized under electrical and mechanical excitation to

investigate the nature of the phenomenon, device sensitivity and performance analysis.

The repeatability and reproducibility of the measurements were studied for a better

understanding of device reliability.

6.1. Device design

The breakdown voltage based micro-resonator is designed and modeled with a

clamped-clamped beam to resonate under the flexural mode. The main beam is anchored

at two endpoints with two rectangular plates attached to it as a central mass, generating

maximum displacement by lowering the beam stiffness. The stress generated around the

anchor points are directly correlated to the magnitude of the produced displacement and

therefore the proposed sensor is designed near the anchoring region. Higher stress can

results in a larger signal output from the sensor by minimizing the parasitic effects as well

as noise. An electrostatic actuator is also designed in parallel to the designed beam as an

alternative actuation mechanism. This enables the device to be tested under electrical and

mechanical forces for the confirmation of the proposed breakdown voltage sensing

mechanism.

The designed micro-resonator prototype has two major design components: a)

actuation and b) sensing mechanism. The actuator is responsible for the resonator body

to vibrate at its modal frequencies whereas the sensor translates the detection of

mechanical vibrations into a detectable electrical signal. The p-n junction is designed to

test its functionality to work as a sensor and actuator in a micro-resonator as shown in

figure 6-1. All the devices are designed with a conventional piezoresistive (PZR) sensor

as an alternative sensing element. This work focus on the study of integrating p-n junction

diode as a breakdown voltage sensor whereas the actuation mechanism requires

dedicated testing and in-depth study, to be done as the future work. The micro-resonators

were also designed with several other commonly used structures such as cantilever beam,

61

tuning fork, rectangular and square plate to investigate the device performance such as

sensitivity, stability, and repeatability.

The mechanical and electrical domain device parameters were computed and

analyzed for the design geometry. The associated mechanical attributes such as resonant

frequency, maximum stress, maximum displacement, and quality factor were extracted by

the finite element analysis method and verified by the theoretical calculations. The

Coventorware simulator was used for the parametric study to estimate the optimum

geometry for the desired mechanical performance. The magnitude and position of the

maximum stress at the event of excitation were analyzed for the optimal placement of

sensors. In addition to that, the electrostatic force and pull-in voltage were estimated by

the co-solve analysis of Coventorware simulator. The characteristic nature of the sensing

element was studied by analyzing the current-voltage response, breakdown voltage and

stress dependence of p-n diode using Sentaurus TCAD process simulations.

Figure 6-1: Top view of designed breakdown voltage sensor (left) and p-n junction actuator (right)

62

6.2. Device analysis

The design goal was to create an out-of-plane flexural micro-resonator with an

embedded p-n junction at the anchor point for sensing mechanical stress/strain. The

desired resonance mode is the upward and downward movement of the attached

rectangular mass plate along with the main beam, exerting a maximum stress/strain near

the anchor region. Structural geometry of the designed clamped-clamped beam resonator

prototype is shown in figure 6-2.

Figure 6-2: 3D model of final device design with geometric details

63

6.2.1. Mechanical domain

The natural resonant frequency is estimated by the calculation of effective spring

constant as well as mass and determined by the following expression:

𝑓𝑜 =𝜔𝑜

2𝜋=

1

2𝜋√

𝑘𝑒𝑓𝑓

𝑚𝑒𝑓𝑓 6.1.

𝑘𝑒𝑓𝑓 =

192𝐸𝐼

𝑙𝑏3

6.2.

𝐼 =

𝑤𝑏ℎ3

12

6.3.

where 𝑘𝑒𝑓𝑓, 𝑚𝑒𝑓𝑓, 𝐼𝑏 , 𝑤𝑏 and ℎ are the effective spring constant, mass, beam length, width,

and thickness respectively. The effective mass is assumed to be the equivalent mass of

two rectangular side plates. The modal analysis simulation was performed for the

estimation of resonant frequency simulated to be 20.31 kHz compared to the theoretical

value of 20.1 kHz. The resonance mode shape of the designed beam is as shown in figure

6-3.

Figure 6-3: Modal analysis result of the out-of-plane resonance frequency

64

The maximum stress along the beam length was computed by the Euler Beam

theory. The beam deflection for different input accelerations was calculated and estimated

the stress by second-order derivative as per the following expression:

𝜎𝑦𝑦 = 𝑦𝐸𝑑2𝜓(𝑥)

𝑑𝑥2 6.4.

𝜓(𝑥) =

𝐹𝑥2

24𝐸𝐼𝑙𝑏(𝑥 − 𝑙𝑏)2

6.5.

where 𝑦, 𝐸, 𝐹, 𝑥 and 𝐼𝑏 are the distance from the neutral axis, Young’s modulus, force,

distance from the anchor point and beam length respectively. The maximum bending

stress for different input accelerations ranging from 1g to 10g was theoretically estimated

and verified by the finite element analysis. A volume boundary condition was defined as

input acceleration along the z-axis by anchoring the two end points. The summary of

maximum stress numerically calculated using equation (6.4) and FEA simulation is

consolidated as per the following table.

Table 6-1: Summary of maximum stress, σyy

Input acceleration (g) σyy_theory (MPa) σyy_simulation (MPa)

1 -0.014 -0.016

2 -0.028 -0.031

3 -0.043 -0.047

4 -0.057 -0.063

5 -0.071 -0.079

6 -0.085 -0.094

7 -0.1 -0.11

8 -0.113 -0.13

9 -0.128 -0.14

10 -0.144 -0.16

Table 6-2: Summary of maximum stress, σyy

65

6.2.2. Electrical domain

The reverse bias voltage of a p-n junction diode is limited by the breakdown

mechanism. The breakdown phenomenon is characterized by the exponential increase in

the reverse leakage current. The two major mechanisms that can cause breakdown are

avalanche multiplication and quantum mechanical tunneling of carriers. Both mechanisms

can be destructive by overheating due to a large current flow across the junction [44].

Avalanche breakdown occurs in p-n junction with large depletion width at higher

breakdown voltage. At higher reverse bias voltage, the increase in junction electric field

results in the acceleration and bombardment of minority carriers generating more electron-

hole pairs. This phenomenon is called impact ionization.

The general expression for the breakdown voltage of an abrupt p-n junction is

given by equation (3.3). The breakdown in silicon can be predicted by the empirical

expression for the electric field at the breakdown is given by:

|𝐸𝑚| =

4 × 105

1 −13

log (𝑁𝐵

1016)

6.6.

where 𝑁𝐵 stands for background doping concentration. The corresponding depletion layer

width at the event of a breakdown is given by:

𝑤𝑏𝑟 =

|𝐸𝑚| ∈𝑠

𝑞𝑁𝐵

6.7.

The device was designed to operate at a breakdown voltage of around 10V by the

selection of appropriate background dopant concentration. As per the figure 6-4, it can be

seen that the desired breakdown voltage is obtained by choosing the background dopant

concentration to be 1017𝑎𝑡𝑜𝑚𝑠/𝑐𝑚3. The smaller background dopant concentration

results in a larger depletion region, thereby higher breakdown voltage. This can potentially

degrade the device performance by increasing internal series resistance across the p-n

junction. The series resistance is a parasitic effect that blocks the small signal changes

coming from the device by generating an undesirable feedback loop in the electronics.

66

6.3. Device testing and characterization

The designed breakdown voltage sensor was tested by electrical and mechanical

methods to evaluate the DC and AC performance analysis. The test results were then

compared with analytical models and discussed in the following sections.

6.3.1. Metrology inspection

The diced device sample was initially inspected under the scanning electron microscopy

(SEM) for surface non-uniformities and residue from the micro-fabrication process prior to

testing and characterization. The Nova Nano SEM was used under the immersion mode

for the high-resolution image acquisition as shown in figure 6-5. The designed micro-

resonator device was fabricated on an SOI wafer using bulk micro-machining process with

a device layer thickness of 2 µm and resistivity of 0.1-0.2 Ω-cm. The design consists of

one main beam with two rectangular proof mass attached to either side of the main beam.

Figure 6-4: Breakdown voltage and critical electrical field plot for different background dopant concentration

Figure 6-5: Breakdown voltage and critical electrical field plot for different background dopant concentration

67

Figure 6-5: (a) SEM of the final device where the annotation ‘N’ and ‘P’ indicates metal contacts to the n-doped region and p-type device layer respectively (b) Zoomed-in views of breakdown voltage sensor (c) Piezoresistor (d) Low

magnification optical image of device

68

A p-n junction diode and a piezoresisitor are embedded at either end of the main

beam accessed by metal pads for electrical testing. The metal contacts annotated by the

letter ‘P’ and ‘N’ indicates metal contacts to p-Si (boron doped) and n-Si (phosphorus

doped) respectively, which are electrically isolated by the passivation nitride layer.

Similarly, the PZR is designed with two metal pads named PZR1 and PZR2 as shown in

figure 6-5(a), connects to either endpoint of the phosphorus-doped region. The bottom

handle layer is accessed by the backside metal that is mounted on to the package using

conductive tape.

6.3.2. Diode characteristics

The device testing and characterization are initiated by verifying the electrical

characteristics of the embedded p-n junction. The critical diode parameters such as

breakdown voltage, leakage current, and series resistance are measured by the current-

voltage sweep and discussed in the following section.

The quality of p-n diode is the most important attribute, translates into the device

performance. The electrical characteristic curve is obtained by voltage sweep and current

measurement is done by using a Keithley 2400 source-measure unit. The input voltage

range was set to be from -11 V to 3 V by limiting the current to be 3 mA. A sudden spike

in measured current can damage the p-n junction due to overheating as shown in figure

Figure 6-6: Optical image of damaged p-n junction due to a spike in diode current

69

6-6. At higher current, the power generated becomes significant and tries to dissipate it

quickly by rising the temperature causing damage to the device. One method to resolve

this issue is by designing an appropriate heat sink to control the variations in junction

temperature. All the measurements are performed at room temperature in the ambient

condition by eliminating the effects of photovoltaic response.

Figure 6-7: Measured Current-Voltage characteristics curve of p-n junction diode

Figure 6-8: Gummel plot of p-n junction diode in the forward bias region

70

The forward bias response of diode is analyzed for the measurement of

parameters such as turn-on voltage and series resistance. An ideal silicon-based diode

turns on at 0.7 V and IV measurement indicates the designed p-n junction follows the ideal

diode characteristics as shown in figure 6-7. At higher input voltages p-n junction diode

can be resistive due to the metal-silicon contact resistance and bulk resistance of silicon

itself depending on doping concentration. This can be estimated from the slope of Gummel

plot at which the current is plotted in logarithmic scale and calculated to be 1.1 kΩ as

shown in figure 6-8.

The reverse bias characteristics are analyzed for the estimation of device

breakdown voltage as well as junction leakage current. The p-n junction doping process

is designed to breakdown at -10 V by theoretical models and simulation process. A sudden

spike in the reverse bias current occurs at -9.2 V and measured as the breakdown point

as shown in figure 6-7. The leakage current under the reverse bias voltage is estimated

to be as small as ~2 nA.

6.3.3. Resonant frequency detection

The device geometry is designed to operate at a resonant frequency of 20.1 kHz

in the flexural mode. The different resonant mode shapes were simulated by the finite

element analysis and converge with the theoretical value. In order to measure the

resonance frequency, the device is actuated electrostatically by applying a voltage (DC

and AC combined) to the substrate and top device silicon layer is grounded. The output

signal is analyzed over a frequency spectrum by a vibrometer. The change in amplitude

and phase confirms the frequency of vibration.

The MSA VIB-A-510 vibrometer is used for the precise measurement of device

dynamic response such as resonance frequency and 3D deflection scan. The scanning

vibrometer consists of a laser interferometer with fiber optics coupled to the measurement

microscope [77]. The output signal from the interferometer is captured by high-

performance data acquisition hardware and processed by the signal analysis software.

The built-in camera is used for the alignment of the laser spot to the desired region of

scanning [78]. The vibrations induced by the resonant frequency creates a shift in the

backscattered light is then analyzed by the precision interferometer by dividing the

incoming light into two parts as a reference beam and measurement beam. The final

71

results are generated by the superposition of these two beams. The vibrometer has been

setup on a vibration table to eliminate any sort of incoming interference from the

atmosphere. The device under test is mounted on the stage and the laser spot is aligned

to the center of the clamped-clamped beam. The in-built vibrometer controller is capable

of supplying a voltage up to 3V maximum. Hence, a combination of 1 V AC and 2 V DC

periodic chirp signal is applied to the substrate whereas the top device silicon layer is

grounded by creating an electrostatic force between the parallel plates. All tests very

carried out under vacuum to eliminate the effects of gas damping as per test setup is

shown in figure 6-9.

The vibrometer controller analyses and plotted the device response over a pre-

defined frequency range by processing the backscattered laser. The initial resonance

peak appeared at 24.5 kHz with a displacement magnitude of 1.4 nm. By extending the

scanning frequency range, another peak appears with an even higher amplitude at 32.8

kHz with 4.9 nm in displacement. The correlation between the magnitude of vibrations and

amplitude of the input signal is verified and found to be quadratic, confirming the appeared

response to be resonance peak but not interference.

Figure 6-9: Test setup for resonant frequency estimation using vibrometer

72

The MSA VIB-A-510 system is also capable of scanning the device vibrations on

real-time for the applied input signal. This mode enables to further analyze and emulate

the device vibration modes in 3D. A measurement grid is primarily defined to cover the

resonator body with an appropriate number of points. A higher number of scan points

result in an increase in scanning resolution. The input signal is applied with the same

amplitude values as 1 V AC and 2 V DC. The final scan modes are obtained for

frequencies at 24.5 kHz and 32.8 kHz as shown in figure 6-10. The scanning result at 24.5

kHz results in a vibration mode shape at which the rectangular plate on the left side goes

downwards when the plate on the right side goes upwards. The expected mode shape is

obtained at 32.8 kHz in which the entire resonator body goes upwards and downwards.

The measured mode shapes by the 3D scan are verified by the finite element simulations.

6.3.4. Effects of electrostatic actuation on the breakdown voltage

The electrostatic actuator works based on the force generated between two

conducting electrodes when a voltage is applied. The generated force is attractive in

nature and can be controlled by the amplitude of input voltage. The effects of the input

voltage are exaggerated in the device by increasing the effective overlap area by higher

capacitance value, thereby consuming less power. The applied AC signal puts the

resonator body into vibration by the electrostatic force and exerts mechanical stress at the

anchor points where the p-n junction is designed. The changes in breakdown voltage are

amplified and analyzed using a lock-in amplifier. At higher input voltage the larger

Figure 6-10: Resonant peaks and 3D scan results from vibrometer

Figure 6-10: Resonant peaks and 3D scan results from vibrometer

73

electrostatic force can vary restoring force significantly and results in pull-in effect. This

can potentially damage the device by leading to a short circuit. Therefore, the input voltage

is restricted lower than the calculated pull-in voltage.

The test setup for the device testing under electrostatic actuation is shown in figure

6-11. The device is actuated by applying an AC voltage to the bottom silicon handle layer

using the internal function generator of the lock-in amplifier. Due to the quadratic nature

between the input drive voltage and the generated electrostatic force, the device under

test oscillates at the second harmonics (2f) for an input frequency, f. Therefore, the stress-

induced changes in breakdown voltage are analyzed at twice the frequency (2f) of the

input signal. The p-n junction is pushed into breakdown region by biasing a voltage of 9.4

V to the n-Si. The p-Si is feed into the transimpedance amplifier with a feedback resistance

of 100 kΩ, were the changes in breakdown current (ΔIbr) due to electrostatic force is

amplified and converted into a voltage domain. This signal is analyzed in reference to the

internal AC signal and the final response is plotted by the lock-in amplifier.

Figure 6-11: Test setup for breakdown voltage changes by electrostatic actuation

74

The breakdown voltage changes to electrostatic force are analyzed for different

input AC voltage amplitude ranges from 0.5 V to 5 V and plotted its response as shown in

figure 6-12. The test was conducted at a lower frequency range of 500 Hz, thereby

minizing its influence from the resonant frequency. The obtained breakdown voltage

changes are analyzed at the second harmonic frequency of 1 kHz. The applied AC signal

changes the electrostatic force and the resultant breakdown voltage by quadratic nature.

The experiment is repeated for different input diode biasing current to study the breakdown

voltage sensitivity at different regions of breakdown. It is found that the breakdown voltage

changes is unchanged for bias current higher than 300 µA. For lower bias current, the

device response becomes unstable and the effect of noise becomes dominant. The

amplified signal from the transimpedance amplifier is also verified using an oscilloscope

to study the characteristics of the generated signal. Non-Linear signal response is

identified at lower bias current (Ibias = 10 µA) and needs to further investigate the effects

of breakdown voltage at the starting point of breakdown.

The same experiment was repeated for different input signal frequencies to

estimate the device frequency response. An AC signal was applied with an amplitude of

3V with its second harmonic frequency ranging from 20 Hz to 4000 Hz (i.e., the first

Figure 6-12: Changes in breakdown voltage for different AC amplitudes

75

harmonic is between 10Hz and 2000Hz). The data is plotted against different input

frequencies as shown in figure 6-13.

At frequencies below 500Hz, the signal has a fairly stable amplitude. While it is

expected that the breakdown voltage response will change with frequency, at this stage

we are unsure of the reasons for signal drop at frequencies above 500Hz, where in

addition to the transduction, the damping can cause signal drop. This effect needs to be

better studied in future devices.

6.3.5. Mechanical shaker testing of the breakdown voltage sensor

The electrostatic actuation method of device testing can affect the test results by

electrical interference. The electrostatic signal applied to the handle silicon layer could

potentially affect the signal changes generated by the p-n junction. This issue is addressed

by testing the device under mechanical vibrations. A mechanical shaker is used for the

excitation of vibrations by applying an input AC signal with an integrated power amplifier.

The mechanical vibration attributes such as displacement, velocity or acceleration and

frequency of vibration are defined by the mechanical shaker controller. The device

response is analyzed and recorded using a lock-in amplifier.

Figure 6-13: Measured frequency dependence of breakdown voltage sensor output

76

A schematic for the experimental setup of the breakdown voltage sensor using

mechanical shaker is shown in figure 6-14. Initially, the p-n junction is pushed into the

breakdown region by biasing at a constant current of Ibias = 500 µA using a Keithley 2400

source measure unit. The device under test is soldered to a PCB and mechanically

mounted to the vibration stage of shaker using a stud. This is to eliminate the damping

effects at lower frequencies and to deliver accurate vibrations as pre-defined by input

settings. A TMS K2004E01 model mechanical shaker is used and the test is carried out

under a closed loop with an Integrated Circuit-Piezoelectric (ICP) sensor for real-time

monitoring of the input accelerations. The vibration frequency is set to be 500 Hz and at

off resonance. The amplitude of the vibrations was controlled with a mechanical shaker

controller under different input accelerations ranging from 1g (9.8 m/sec2) to 10g (98

m/sec2). These accelerations exert maximum stress at the anchor points of the clamped-

Figure 6-14: Mechanical shaker test setup for breakdown voltage sensor testing

77

clamped beam where the p-n junction is defined, resulting in a shift in the breakdown

voltage.

The changes in breakdown voltage from the device under test are amplified by a voltage

amplification circuit with a gain of 100 and feedback into Zurich Instruments HF2 lock-in

amplifier under AC coupling mode to monitor the electrical response. The input vibration

signals from the mechanical shaker controller are then supplied as an external reference

input to the lock-in amplifier to synchronize the amplitude and phase of the waveform. The

drive signal from the controller is passed through a two-stage RC filter to remove the noise

and voltage amplified (gain = 10) before supplying as an external reference signal to the

lock-in amplifier. All the experiments are carried out under atmospheric pressure by

blocking the ambient light to eliminate the photovoltaic effects.

The changes in breakdown voltage are measured and plotted it against the exerted

mechanical stress as shown in figure 6-15. The device response is found to be linear and

a direct function of the input accelerations. The device sensitivity is estimated from the

measurement values with respect to the input stress and calculated to be around 175

Figure 6-15: Box plot for breakdown voltage changes to mechanical vibrations (1g to 10g acceleration) at 500 Hz

78

μV/MPa. The p-n junction is located 730 nm deep from the surface and lateral depletion

region is spread around the active doping region. The magnitude of stress is almost

negligible at 730 nm depth, due to its close proximity to the neutral axis located at 1 μm.

Therefore, the lateral depletion region closer to the surface where the maximum stress is

experienced assumed to be responsible for the changes in silicon energy-band curvature

as well as effective band-gap resulting in an early breakdown. The experiment is repeated

over several days to study the stability and repeatability of the measurement. The standard

deviation from the measurements is estimated to be smaller than 10% as per the box plot

is shown in figure 6-15.

The current in the junction increases exponentially for reverse voltages higher than

the breakdown voltage of the device due to the avalanche effect. This provides an

opportunity for an alternative method for the measurement of the mechanical stresses

where the diode is biased within its breakdown region using a voltage source while

monitoring the changes in current through the device in response to the stress. To

demonstrate this approach, the diode is biased with a voltage source until a 500 µA current

flow through it at rest (Vbr = -9.345 V). The same amount of current also flows through the

piezoresistor at the opposite end of the beam (R0 = 6.9 kΩ). The device is then placed on

Figure 6-16: Comparison of current changes between PZR and BV sensor

79

the shaker and subjected to various magnitudes of inertial forces at 500 Hz. Figure 6-16

shows the measurement results for this experiment. As can be seen, the breakdown

voltage yields a significantly higher sensitivity (~8.6 X) in terms of the change in the current

through the device. This is due to the exponential increase in the current response at the

breakdown point of the p-n junction, whereas the linear characteristics of piezoresistor

limit the device sensitivity. The device sensitivity can be further enhanced by setting the

voltage biasing condition to the starting point of the breakdown event.

Figure 6-17 shows the variations in the sensitivity of breakdown voltage as a

function of bias current for the junction. As can be seen, the device exhibits higher

sensitivity at lower currents at the expense of increased noise. Both the breakdown

voltage and device sensitivity become stable for bias currents larger than ~400 µA.

The effects of mechanical stress on breakdown voltage in a silicon-based p-n

junction diode is theoretically modeled and verified by the Synopsys Sentaurus device

simulations. A micro-resonator is designed, fabricated and characterized to prove the

Figure 6-17: Sensitivity of breakdown voltage changes and noise measurements to the different diode current

80

concept. The experimental results are in good agreement with both the theoretical model

and simulation results. The measurement repeatability and device noise analysis ensures

a promising transduction mechanism in the field of micro-electro-mechanical systems

(MEMS) sensors and actuators.

81

Chapter 7. Conclusions and future work

7.1. Conclusions

In this thesis, for the first time to the best of our knowledge, the breakdown voltage

of a basic p-n junction was utilized for the mechanical stress sensing. Microstructures were

designed with embedded junctions and used to validate the hypothesis and model behind

the phenomenon. This mechanism provides an alternative stress/strain sensing method

for sensitive and low power MEMS applications. The effects of mechanical stress on

breakdown voltage within a p-n junction was studied with analytical models and verified

by device simulations. The analytic model relates the mechanical stress to material

properties such as energy bandgap, critical electric field, and background doping

concentration. The electronic response of the device was studied numerically to

investigate the effect of mechanical stress on p-n junction breakdown voltage and its

dependence on associated parameters. The changes in silicon energy band structure with

respect to the applied mechanical stress were numerically analyzed to study the

phenomenon and utilized for the enhancement of device performance. The Synopsys

Sentaurus TCAD simulations were employed for the DC analysis of p-n junction and its

effects on mechanical stress. The device behaviors were simulated for different ranges

and crystal orientations by summarizing its responsivity and validating the analytical

model.

The Finite Element Analysis (FEA) and modal analysis using Coventorware

software were used for the static and dynamic device responses. The fundamental

resonating structures such as cantilever beams, clamped-clamped beams, tuning-fork,

rectangular beams, and square plates were designed for analyzing the sensitivity of

breakdown voltage at different stress levels. In addition to the sensing mechanism, the p-

n junctions were also employed as an actuator to induce mechanical excitations within the

resonator body. Therefore, the identical p-n junctions can be used for the sensing and

actuation in a micro-resonator by minimizing the complexity of device fabrication.

The design prototype has been developed by a bulk-micromachining process

using the SOI substrate. The process flow was designed and developed based on the

TCAD process simulations to meet the device performance specifications and FEA

simulations for the required electro-mechanical performance. A photomask set was then

82

designed with numerous flexural-mode designs in which geometry was chosen for the

device to resonate within a few tens of kHz. Each processing steps was optimized by the

silicon pilot wafers to ensure the compatibility of all steps with high-quality output. The

developed process flow is identical to the standard foundry process, with major processing

steps consisting of doping and deep etching. The doping process parameters were

precisely estimated which is essential for the creation of p-n junctions and piezoresistors.

One of the major challenges was to achieve narrow transduction gaps for improved

transduction efficiency. This challenge was overcome by the dry etching process with a

high level of anisotropy by minimizing the discrepancies between design CD and physical

CD. The metallization process was carefully executed with a clean surface to achieve

ohmic contacts to both p-type and n-type regions. The final sacrificial oxide releasing step

was optimized with no sign of stiction and less impact on surface roughness.

Micro-structures with different geometries were designed with embedded p-n

junctions for the proof-of-concept experiments in such a way that the upward and

downward movements of a proof-mass exerted maximum stress across the junctions

resulting in a shift in current-voltage characteristics. In addition to the p-n junction, a

piezoresistive sensor was also designed and embedded on the structure for performance

comparison. The device characterization verifies that the breakdown voltage sensor offers

higher strain sensitivity compared to the conventional piezoresistive sensors while

consuming a smaller effective chip area. The breakdown voltage sensors were

characterized using a stable test setup for the repeatability and reproducibility of

measurements by minimizing external interferences. The static measurements were

performed to evaluate the I-V characteristics of p-n junctions measuring basic diode

parameters. On the other hand, the dynamic measurements facilitate the study of p-n

junction characteristics with mechanical excitations and electrostatic force. The

experiments were conducted in the electrical and mechanical domains to study the

differences in device behavior and for the confirmation of phenomenon. Further

experiments were performed for the in-depth understanding of device sensitivity at

different diode currents, noise levels, and device frequency response. All the experiments

were repeated for the piezoresistive sensors in parallel with breakdown voltage sensors

for baseline comparison. The low power consumption, high sensitivity, and scope for

miniaturization qualifies it as a potential transduction mechanism in the field of MEMS.

83

7.2. Thesis Contributions

The highlights of the thesis contributions can be summarized as follows:

Development of an analytical model for the study of mechanical stress

effects on avalanche breakdown

We have proposed an analytical model to study the behavior of breakdown

voltage and associated parameters for its dependence on mechanical stress.

The influence of parameters such as junction electric field and doping

concentration is taken into account to establish the model.

Developing electronic and electromechanical numerical models

We have validated the accuracy and precision of the developed model using

Synopsys Sentaurus TCAD, where we verified the changes in breakdown

voltage for different ranges of mechanical stress. A reliable way of simulating

this phenomenon by the choice of appropriate modules and activation of

physical phenomenon is demonstrated.

Development and optimization of the microfabrication process

An SOI micro-machining process has developed for the fabrication of device

prototypes. The process flow is capable to support various designs on a single

substrate. Each process steps are optimized to minimize the process induced

deviations.

Experimental characterization and verification

The device prototypes are tested under the electrical and mechanical domain

for the verification of phenomenon. The electronic circuits for the reliable way

of device testing are designed and implemented.

The studied physical phenomenon and its characterization results are submitted

to the scientific journal (Applied Physics Letters) currently under review. In

addition, further device testing is in-progress and results will be published in the

upcoming conferences.

84

7.3. Future work

This thesis has carried out extensive research and investigations into design,

development, and characterization of miniaturized mechanical stress/strain sensor by p-n

junction breakdown voltage phenomena. There are several research challenges that could

be potentially explored and addressed for future improvements. Some of them are listed

below:

Study of temperature effects on breakdown voltage for the static sensing

applications.

Studying the transient and frequency responses of breakdown voltage

sensors.

Noise analysis and modeling of breakdown voltage sensing mechanism.

Design of bulk-mode micro-resonator with embedded breakdown voltage

sensor to study the responsivity of the phenomenon at higher order

frequencies.

Development of p-n junctions with smaller breakdown voltage and series

resistance to further minimize the power consumption and enhancement of

device sensitivity.

The use of Junction Field Effect Transistors instead of p-n junctions by

providing on-chip amplification with a higher signal-to-noise ratio.

85

References

[1] R. Rao, An Introduction to MEMS (Micro-electromechanical Systems). Prime Faraday Technology Watch, 2002.

[2] P. J. French and P. M. Sarro, “Surface versus bulk micromachining: the contest for suitable applications,” J. Micromechanics Microengineering, vol. 8, no. 2, pp. 45–53, Jun. 1998.

[3] M. Li, H. X. Tang, and M. L. Roukes, “Ultra-sensitive NEMS-based cantilevers for sensing, scanned probe and very high-frequency applications,” Nat. Nanotechnol., vol. 2, no. 2, pp. 114–120, Feb. 2007.

[4] B. Bahreyni, “Chapter 1 - Introduction,” in Fabrication and Design of Resonant Microdevices, B. Bahreyni, Ed. Norwich, NY: William Andrew Publishing, 2009, pp. 1–8.

[5] A. C. Fischer et al., “Integrating MEMS and ICs,” Microsyst. Nanoeng., vol. 1, no. 1, Dec. 2015.

[6] T. M. Adams and R. A. Layton, Introductory MEMS: Fabrication and Applications. Springer US, 2010.

[7] X. Li, B. Bhushan, K. Takashima, C.-W. Baek, and Y.-K. Kim, “Mechanical characterization of micro/nanoscale structures for MEMS/NEMS applications using nanoindentation techniques,” Ultramicroscopy, vol. 97, no. 1–4, pp. 481–494, Oct. 2003.

[8] “The MEMS market is showing a 17.5% CAGR between 2018 and 2023 | Solid State Technology,” May-2018. [Online]. Available: https://electroiq.com/2018/06/the-mems-market-is-showing-a-17-5-cagr-between-2018-and-2023/. [Accessed: 25-Mar-2019].

[9] M. A. Rasouli, “Employing piezojunction effect for resonant micro-device applications,” Thesis, Applied Sciences: School of Mechatronic Systems Engineering, 2016.

[10] A. Jayaraman, M. E. Sikorski, J. C. Irvin, and G. H. Yates, “Effect of Hydrostatic Pressure on p‐n Junction Characteristics and the Pressure Variation of the Band Gap,” J. Appl. Phys., vol. 38, no. 11, pp. 4454–4459, Oct. 1967.

[11] “Transducer | electronics,” Encyclopedia Britannica. [Online]. Available: https://www.britannica.com/technology/transducer-electronics. [Accessed: 07-Apr-2019].

[12] R. H. Bishop, Mechatronic Systems, Sensors, and Actuators: Fundamentals and Modeling. CRC Press, 2017.

[13] R. Puers and D. Lapadatu, “Electrostatic forces and their effects on capacitive mechanical sensors,” Sens. Actuators Phys., vol. 56, no. 3, pp. 203–210, Sep. 1996.

[14] M. Suster, J. Guo, N. Chaimanonart, W. H. Ko, and D. J. Young, “A High-Performance MEMS Capacitive Strain Sensing System,” J. Microelectromechanical Syst., vol. 15, no. 5, pp. 1069–1077, Oct. 2006.

[15] M. Gad-el-Hak, MEMS: Applications. CRC Press, 2005. [16] M. Suh, “Wearable sensors for athletes,” in Electronic Textiles, T. Dias, Ed. Oxford:

Woodhead Publishing, 2015, pp. 257–273. [17] S. Kon, K. Oldham, and R. Horowitz, “Piezoresistive and piezoelectric MEMS strain

sensors for vibration detection,” presented at the The 14th International Symposium on: Smart Structures and Materials & Nondestructive Evaluation and Health Monitoring, San Diego, California, 2007, p. 65292V.

86

[18] Y. Kanda, “A graphical representation of the piezoresistance coefficients in silicon,” IEEE Trans. Electron Devices, vol. 29, no. 1, pp. 64–70, Jan. 1982.

[19] A. Boukabache and P. Pons, “Doping effects on thermal behaviour of silicon resistor,” Electron. Lett., vol. 38, no. 7, pp. 342–343, Mar. 2002.

[20] A. A. S. Mohammed, W. A. Moussa, and E. Lou, “High-Performance Piezoresistive MEMS Strain Sensor with Low Thermal Sensitivity,” Sensors, vol. 11, no. 2, pp. 1819–1846, Jan. 2011.

[21] A. A. S. Mohammed, W. A. Moussa, and E. Lou, “High-Performance Piezoresistive MEMS Strain Sensor with Low Thermal Sensitivity,” Sensors, vol. 11, no. 2, pp. 1819–1846, Feb. 2011.

[22] S. D. Senturia, Microsystem Design. Springer US, 2001. [23] A. A. S. Mohammed, W. A. Moussa, and E. Lou, “Development and Experimental

Evaluation of a Novel Piezoresistive MEMS Strain Sensor,” IEEE Sens. J., vol. 11, no. 10, pp. 2220–2232, Oct. 2011.

[24] D. Weinstein and S. A. Bhave, “Piezoresistive sensing of a dielectrically actuated silicon bar resonator,” presented at the Solid-State Sensors, Actuators, and Microsystems Workshop, 2018, p. 4.

[25] Y. Liu, H. Wang, W. Zhao, H. Qin, and X. Fang, “Thermal-Performance Instability in Piezoresistive Sensors: Inducement and Improvement,” Sensors, vol. 16, no. 12, Nov. 2016.

[26] H. P. Lobl et al., “Piezoelectric materials for BAW resonators and filters,” in 2001 IEEE Ultrasonics Symposium. Proceedings. An International Symposium (Cat. No.01CH37263), 2001, vol. 1, pp. 807–811 vol.1.

[27] J. Karki, “Signal Conditioning Piezoelectric Sensors,” Application report SLOA033A, Sep. 2000.

[28] S. Kon and R. Horowitz, “A High-Resolution MEMS Piezoelectric Strain Sensor for Structural Vibration Detection,” IEEE Sens. J., vol. 8, no. 12, pp. 2027–2035, Dec. 2008.

[29] H. H. Hall, J. Bardeen, and G. L. Pearson, “The Effects of Pressure and Temperature on the Resistance of p-n Junctions in Germanium,” Phys. Rev., vol. 84, no. 1, pp. 129–132, Oct. 1951.

[30] F. Fruett and G. C. M. Meijer, Eds., “Stress-sensing elements based on the piezojunction effect,” in The Piezojunction Effect in Silicon Integrated Circuits and Sensors, Boston, MA: Springer US, 2002, pp. 119–142.

[31] F. Fruett and G. C. M. Meijer, The Piezojunction Effect in Silicon Integrated Circuits and Sensors. Springer Science & Business Media, 2006.

[32] G. C. M. Meijer, “Concepts for bandgap References and voltage measurement systems,” in Analog Circuit Design: Low-Noise, Low-Power, Low-Voltage; Mixed-Mode Design with CAD Tools; Voltage, Current and Time References, J. H. Huijsing, R. J. van de Plassche, and W. M. C. Sansen, Eds. Boston, MA: Springer US, 1996, pp. 243–268.

[33] G. C. M. Meijer, P. C. Schmale, and K. V. Zalinge, “A new curvature-corrected bandgap reference,” IEEE J. Solid-State Circuits, vol. 17, no. 6, pp. 1139–1143, Dec. 1982.

[34] M. E. Sikorski, P. Andreatch, A. Grieco, and H. Christensen, “Transistor Microphone,” Rev. Sci. Instrum., vol. 33, pp. 1130–1131, Oct. 1962.

[35] F. Krieger and H.- Toussaint, “A piezo-mesh-diode pressure transducer,” Proc. IEEE, vol. 55, no. 7, pp. 1234–1235, Jul. 1967.

[36] J. J. Wortman and L. K. Monteith, “Semiconductor mechanical sensors,” IEEE Trans. Electron Devices, vol. 16, no. 10, pp. 855–860, Oct. 1969.

87

[37] D. P. Jones, S. V. Ellam, H. Riddle, and B. W. Watson, “The measurement of air flow in a forced expiration using a pressure-sensitive transistor,” Med. Biol. Eng., vol. 13, no. 1, pp. 71–77, Jan. 1975.

[38] J. Matovic, Z. Djuric, N. Simicic, and A. Vujanic, “Piezojunction effect based pressure sensor,” Electron. Lett., vol. 29, no. 6, pp. 565–566, Mar. 1993.

[39] J. F. Nye, Physical Properties of Crystals: Their Representation by Tensors and Matrices, Reprint edition. Oxford Oxfordshire : New York: Oxford University Press, 1999.

[40] G. L. Bir, Symmetry and strain-induced effects in semiconductors. New York: Wiley, 1974.

[41] C. Herring, “Transport properties of a many-valley semiconductor,” Bell Syst. Tech. J., vol. 34, no. 2, pp. 237–290, Mar. 1955.

[42] J. F. Creemer and P. J. French, “A new model of the effect of mechanical stress on the saturation current of bipolar transistors,” Sens. Actuators Phys., vol. 97–98, pp. 289–295, Apr. 2002.

[43] S. M. Sze and K. K. Ng, Physics of Semiconductor Devices, 3 edition. Hoboken, N.J: Wiley-Interscience, 2006.

[44] B. J. V. Zeghbroeck, Principles of Semiconductor Devices. Bart Van Zeghbroeck, 2011.

[45] R. L. Davies and F. E. Gentry, “Control of electric field at the surface of P-N junctions,” IEEE Trans. Electron Devices, vol. 11, no. 7, pp. 313–323, Jul. 1964.

[46] C. Y. Chang, S. S. Chiu, and L. P. Hsu, “Temperature dependence of breakdown voltage in silicon abrupt p-n junctions,” IEEE Trans. Electron Devices, vol. 18, no. 6, pp. 391–393, Jun. 1971.

[47] J. R. Hauser and J. J. Wortman, “Some Effects of Mechanical Stress on the Breakdown Voltage of p‐n Junctions,” J. Appl. Phys., vol. 37, no. 10, pp. 3884–3892, Sep. 1966.

[48] J. J. Wortman, J. R. Hauser, and R. M. Burger, “Effect of Mechanical Stress on p‐n Junction Device Characteristics,” J. Appl. Phys., vol. 35, no. 7, pp. 2122–2131, Jul. 1964.

[49] R. Edwards, “Some effects of localized stress on silicon planar transistors,” IEEE Trans. Electron Devices, vol. 11, pp. 286–294, Jun. 1964.

[50] Y. Kanda, “Effect of Stress on Germanium and Silicon p-n Junctions,” Jpn. J. Appl. Phys., vol. 6, no. 4, p. 475, Apr. 1967.

[51] S. Dhar, E. Ungersbock, H. Kosina, T. Grasser, and S. Selberherr, “Electron Mobility Model for 110 Stressed Silicon Including Strain-Dependent Mass,” IEEE Trans. Nanotechnol., vol. 6, no. 1, pp. 97–100, Jan. 2007.

[52] K. Uchida, T. Krishnamohan, K. C. Saraswat, and Y. Nishi, “Physical mechanisms of electron mobility enhancement in uniaxial stressed MOSFETs and impact of uniaxial stress engineering in ballistic regime,” in Technical Digest - International Electron Devices Meeting, IEDM, 2005, pp. 129–132.

[53] I. Goroff and L. Kleinman, “Deformation Potentials in Silicon. III. Effects of a General Strain on Conduction and Valence Levels,” Phys. Rev., vol. 132, no. 3, pp. 1080–1084, Nov. 1963.

[54] Y. Sun, S. E. Thompson, and T. Nishida, “Physics of strain effects in semiconductors and metal-oxide-semiconductor field-effect transistors,” J. Appl. Phys., vol. 101, no. 10, p. 104503, May 2007.

[55] A. Goetzberger and R. H. Finch, “Lowering the Breakdown Voltage of Silicon p‐n Junctions by Stress,” J. Appl. Phys., vol. 35, no. 6, pp. 1851–1854, Jun. 1964.

[56] W. Rindner, “Effects of Uniaxial and Inhomogeneous Stress in Germanium and

Silicon p‐n Junctions,” J. Appl. Phys., vol. 36, no. 8, pp. 2513–2518, Aug. 1965.

88

[57] W. Rindner, “BREAKDOWN VOLTAGES AND CURRENTS IN MECHANICALLY STRESSED Ge AND Si DIODES,” Appl. Phys. Lett., vol. 6, no. 11, pp. 225–226, Jun. 1965.

[58] J. L. Hudgins, G. S. Simin, E. Santi, and M. A. Khan, “An assessment of wide bandgap semiconductors for power devices,” IEEE Trans. Power Electron., vol. 18, no. 3, pp. 907–914, May 2003.

[59] “Sentaurus Device User Manual.” Synopsys, Jun-2006. [60] S. Reggiani, M. Valdinoci, L. Colalongo, and G. Baccarani, “A Unified Analytical

Model for Bulk and Surface Mobility in Si n- and p-Channel MOSFET’s,” in 29th European Solid-State Device Research Conference, 1999, vol. 1, pp. 240–243.

[61] S. Reggiani et al., “Electron and hole mobility in silicon at large operating temperatures. I. Bulk mobility,” IEEE Trans. Electron Devices, vol. 49, no. 3, pp. 490–499, Mar. 2002.

[62] G. Zhao et al., “A simulation method of Pressure-Stress affects Power Press Pack FRD Chip Forward voltage,” Appl. Mech. Mater. Trans Tech Publ., vol. 433–435, Oct. 2013.

[63] J. L. Egley and D. Chidambarrao, “Strain effects on device characteristics: Implementation in drift-diffusion simulators,” Solid-State Electron., vol. 36, no. 12, pp. 1653–1664, Dec. 1993.

[64] F. Herman, “The Electronic Energy Band Structure of Silicon and Germanium,” Proc. IRE, vol. 43, no. 12, pp. 1703–1732, Dec. 1955.

[65] J. Bardeen and W. Shockley, “Deformation Potentials and Mobilities in Non-Polar Crystals,” Phys. Rev., vol. 80, no. 1, pp. 72–80, Oct. 1950.

[66] “Foundry Ion Implantation Service | INNOVION CORPORATION.” [Online]. Available: https://www.innovioncorp.com/. [Accessed: 08-Apr-2019].

[67] S. M. Ku, “Boron-implanted silicon resistors,” Solid-State Electron., vol. 20, no. 10, pp. 803–812, Oct. 1977.

[68] F. E. Office, “Analysis of Ion Implantation Profiles for Accurate Process/Device Simulation: Analysis Based on Quasi-Crystal Extended LSS Theory,” FUJITSU Sci Tech J, vol. 46, no. 3, p. 9, 2010.

[69] P. Äyräs, J. T. Rantala, S. Honkanen, S. B. Mendes, and N. Peyghambarian, “Diffraction gratings in sol–gel films by direct contact printing using a UV-mercury lamp,” Opt. Commun., vol. 162, no. 4, pp. 215–218, Apr. 1999.

[70] “Manual mask aligner, ABM USA.” [Online]. Available: http://www.abmusainc.com/. [Accessed: 08-Apr-2019].

[71] “AZ MiR 703 Series Photoresists,” Integrated Micro Materials. [Online]. Available: http://www.imicromaterials.com/index.php/products/ig-line-photoresists/az-mir-703-series. [Accessed: 08-Apr-2019].

[72] “AZ300 MIF Specs,” Integrated Micro Materials. [Online]. Available: http://www.imicromaterials.com/index.php/Products/Developers/mif-specs. [Accessed: 08-Apr-2019].

[73] “Plasma Etcher & Plasma Deposition Tools by SENTECH.” [Online]. Available: https://www.sentech.com/en/RIE-Etchlab-200__228/. [Accessed: 08-Apr-2019].

[74] K. R. Williams, K. Gupta, and M. Wasilik, “Etch rates for micromachining processing-part II,” J. Microelectromechanical Syst., vol. 12, no. 6, pp. 761–778, Dec. 2003.

[75] “Idonus HF Vapor Phase Etcher.” [Online]. Available: https://www.idonus.com/products/mems-products/hf-vapor-phase-etcher.html. [Accessed: 08-Apr-2019].

[76] T. Bakke, J. Schmidt, M. Friedrichs, B. Völker, T. Fraunhofer Bakke@ipms, and De, Etch stop materials for release by vapor HF etching, vol. 16. 2005.

89

[77] “Polytec GmbH Optical Measurement Systems Application Note VIB-G-05, June 2006.” .

[78] A. B. Stanbridge and D. J. Ewins, “Modal testing using a scanning laser doppler vibrometer,” Mech. Syst. Signal Process., vol. 13, no. 2, pp. 255–270, Mar. 1999.

90

Appendix A Fabrication details

The following are the details of recipes and process parameters associated with micro-

fabrication for the development of breakdown voltage sensor.

Step ID Process Step Process details

1. Ion-implantation (P-type)

1-1 Blanket ion-implantation Energy: 150 keV

Dose: 5.00E+13 atoms/cm2

Tilt: 0º

Dopant: Boron

2. Alignment pattern and etch

2-1 Alignment pattern HMDS (vacuum): 10 minutes

HMDS bake: 150ºC for 2 minutes

Photoresist: AZ703

Resist spinning: 4000 rpm for 60 seconds

Soft bake: 90ºC for 60 seconds

Pre-exposure bake: 110ºC for 60 seconds

Exposure: 3.3 seconds

Post-exposure bake: 110ºC for 60 seconds

Development: AZ300 for 55 seconds

Hard bake: 110ºC for 2 minutes

91

Step ID Process Step Process details

2-2 Silicon RIE 12sccm SF6 + 7sccm O2

Power: 250 Watts

Pressure: 15 mTorr

Time: 60 seconds

Etch rate: ~220 nm/min

2-3 Photoresist removal Acetone + Sonic agitation: 3 minutes

IPA rinse: 60 seconds

3. Oxidation/Annealing

3-1 Standard RCA clean - RCA SC – 1

DI H2O : NH4OH : H2O2 – 5 : 1 : 1

Temperature: 80ºC

Time: 10 minutes

- Modified HF dip

DI H2O : HF – 50 : 1

Room temperature

Time: 30 seconds

- RCA SC – 2

DI H2O : HCl : H2O2 – 6 : 1 : 1

Temperature: 80ºC

Time: 10 minutes

3-2 DI water rinse Time: 3 minutes, 3 cycles

Step ID Process Step Process details

92

Step ID Process Step Process details

3-3 Wet thermal oxidation Temperature: 1000ºC

Time: 35 minutes

3-4 Oxide patterning HMDS (vacuum): 10 minutes

HMDS bake: 150ºC for 2 minutes

Photoresist: AZ703

Resist spinning: 4000 rpm for 60 seconds

Soft bake: 90ºC for 60 seconds

Pre-exposure bake: 110ºC for 60 seconds

Exposure: 3.3 seconds

Post-exposure bake: 110ºC for 60 seconds

Development: AZ300 for 55 seconds

Hard bake: 110ºC for 2 minutes

3-5 Oxide RIE 50sccm CHF3 + 2sccm O2

Power: 100 Watts

Pressure: 75 mTorr

Time: 7 minutes and 30 seconds

Etch rate: 17.5 nm/min

3-6 Hard bake Temperature: 120ºC

Time: 60 seconds

3-7 Oxide wet etch Buffer oxide etchant (BOE)

Time: 1 minute 30 seconds

3-8 Photoresist removal Acetone + Sonic agitation: 3 minutes

IPA rinse: 60 seconds

93

Step ID Process Step Process details

4. Ion-implantation (N-type)

4-1 Selective ion-implantation - Implant 1

Energy: 40 keV

Dose: 1.00E+12 atoms/cm2

Tilt: 0º

Dopant: Phosphorus

- Implant 2

Energy: 20 keV

Dose: 5.00E+14 atoms/cm2

Tilt: 7º

Dopant: Phosphorus

4-2 Oxide strip Buffer oxide etchant (BOE)

Time: 8 minutes

Room temperature

4-3 Standard RCA clean - RCA SC – 1

DI H2O : NH4OH : H2O2 – 5 : 1 : 1

Temperature: 80ºC

Time: 10 minutes

- Modified HF dip

DI H2O : HF – 50 : 1

Room temperature

Time: 30 seconds

Step ID Process Step Process details

94

Step ID Process Step Process details

4-4 Annealing/Oxidation Temperature: 800ºC

Time: 45 minutes

5. Nitride deposition and patterning (Vias)

5-1 LPCVD Si3N4 deposition Standard low-stress recipe developed by nanoFAB, University of Alberta.

Thickness: ~210nm

5-2 Contact vias patterning HMDS (vacuum): 10 minutes

HMDS bake: 150ºC for 2 minutes

Photoresist: AZ703

Resist spinning: 4000 rpm for 60 seconds

Soft bake: 90ºC for 60 seconds

Pre-exposure bake: 110ºC for 60 seconds

Exposure: 3.3 seconds

Post-exposure bake: 110ºC for 60 seconds

Development: AZ300 for 55 seconds

Hard bake: 110ºC for 2 minutes

5-3 Nitride RIE 30sccm CF4 + 2sccm O2

Power: 80 Watts

Pressure: 30 mTorr

Time: 5 minutes 40 seconds

Etch rate: 40.5 nm/min

5.4 Hard bake Temperature: 120ºC

Time: 60 seconds

95

Step ID Process Step Process details

5-5 Oxide wet etch Buffer oxide etchant (BOE)

Time: 1 minute 20 seconds

Room temperature

5-6 Photoresist removal Acetone + Sonic agitation: 3 minutes

IPA rinse: 60 seconds

6. Metallization

6-1 Photoresist exposure

(Mask: Metal)

HMDS (vacuum): 10 minutes

HMDS bake: 150ºC for 2 minutes

Photoresist: AZ703

Resist spinning: 4000 rpm for 60 seconds

Soft bake: 90ºC for 60 seconds

Pre-exposure bake: 110ºC for 60 seconds

Exposure: 3.3 seconds

Post-exposure bake: 110ºC for 60 seconds

Development: AZ300 for 55 seconds

6-2 Descum 45sccm O2

Power: 50 Watts

Pressure: 280 mTorr

Time: 3 minutes

6-3 Thermal evaporation

(Aluminum)

Material: Aluminum (Al99Si1)

Deposition rate: ~ 5 Aº/second

Thickness: 200nm

Step ID Process Step Process details

96

Step ID Process Step Process details

6-4 Thermal evaporation

(Nickel)

Material: Nickel

Deposition rate: ~ 5 Aº/second

Thickness: 150nm

6-5 Metal lift-off Acetone soak: 10 minutes

Acetone + Sonic agitation: 3 minutes

IPA rinse: 3 minutes

7. Device silicon pattern and etch

7-1 Device silicon pattern Standard procedure done at nanoFAB, University of Alberta.

Equipment: SUSS MA/BA6

Minimum resolution: 1µm

7-2 Nitride RIE Done at nanoFAB facility.

7-3 Oxide RIE Done at nanoFAB facility.

7-4 Silicon DRIE Standard procedure done at nanoFAB, University of Alberta.

Equipment: Oxford Estrelas

Etch depth: 2.1 µm +/-10%

7-5 Photoresist removal Acetone + Sonic agitation: 3 minutes

IPA rinse: 60 seconds

Step ID Process Step Process details

6-4 Thermal evaporation Material: Nickel

97

Step ID Process Step Process details

8. Back-side metal contact

8-1 Front-side protection Photoresist: AZ703

Resist spinning: 3000 rpm for 60 seconds (2x)

Hard bake: 120ºC for 2 minutes

8-2 Nitride RIE (back-side) 30sccm CF4 + 2sccm O2

Power: 80 Watts

Pressure: 30 mTorr

Time: 12 minutes

Etch rate: 40.5 nm/min

8-3 Oxide wet etch Buffer oxide etchant (BOE)

Time: 2 minutes

Room temperature

8-4 Thermal evaporation

(Aluminum)

Material: Aluminum (Al99Si1)

Deposition rate: ~ 5 Aº/second

Thickness: 200nm

9. Release

9-1 Photoresist removal Microposit 1165 soak: 10 minutes

IPA rinse: 60 seconds

9-2 Ashing Power: 300 Watts

Pressure: 280 mTorr

Time: 10 minutes

Step ID Process Step Process details

98

Step ID Process Step Process details

9-3 Drying Hotplate

Temperature: 150ºC

Time: 10 minutes

9-4 Vapor HF release Temperature: 35ºC

Number of steps: 10

Each step cycle:

- VHF for 3 minutes

- Hotplate 180ºC for 60 seconds

99

P-N junction based micro-resonators

A square shaped micro-resonator was designed with embedded p-n junctions at

the four anchoring locations as shown in figure A-1. The sensing and actuation are made

possible by the integrated p-n junctions as well as electrostatic transduction mechanism

with a minimum gap of 1 µm. In addition to that, a silicon-based surface acoustic wave

(SAW) resonator was designed with continuous doping lines works by the basic principle

of p-n junction based actuation is shown in figure A-2.

Figure A-1: SEM image of square plate resonator with p-n junction at four anchor

points

Figure A-1: SEM image of square plate resonator with p-n junction at four anchor

points

Figure A-2: SEM image of silicon-based surface acoustic wave (SAW) resonator

with p-n junction lines

100

Resonant peak detection

The resonant frequency for the square plate resonator (300 x 300 µm) was estimated by

the lock-in amplifier. The estimated resonant peak was detected near 205 kHz with the

amplitude and phase response as shown in figure A-3.

Figure A-3: Amplitude (top) and phase (bottom) response of the detected

resonant peak by frequency sweep in the lock-in amplifier.

101

Appendix B Synopsys Sentaurus TCAD pseudo code

Sentaurus Structure Editor

(sde:clear)

(sdegeo:create-rectangle (position -10 0.0 0.0) (position 10 2.0 0.0) "Silicon" "R.Device")

(sdegeo:create-rectangle (position -10 2.0 0.0) (position -8 4.0 0.0) "Oxide" "R.BoxL")

(sdegeo:create-rectangle (position 8 2.0 0.0) (position 10 4.0 0.0) "Oxide" "R.BoxR")

(sdegeo:create-rectangle (position -10 4 0.0) (position 10 50 0.0) "Silicon" "R.Substrate")

(sdegeo:set-default-boolean "ABA")

(sdegeo:define-contact-set "P" 4.0 (color:rgb 1.0 0.0 0.0 ) "##" )

(sdegeo:define-contact-set "N" 4.0 (color:rgb 0.0 0.0 1.0 ) "##" )

(sdegeo:define-contact-set "left_handle" 4.0 (color:rgb 0.0 1.0 1.0 ) "##" )

(sdegeo:define-contact-set "right_handle" 4.0 (color:rgb 0.0 1.0 1.0 ) "##" )

(sdegeo:define-contact-set "top_device" 4.0 (color:rgb 0.0 1.0 1.0 ) "##" )

(sdegeo:define-contact-set "bottom" 4.0 (color:rgb 0.0 1.0 1.0 ) "##" )

(sdegeo:insert-vertex (position -9.9 50 0.0))

(sdegeo:insert-vertex (position 9.9 50 0.0))

(sdegeo:set-contact (find-edge-id (position 0 0 0.0)) "N")

(sdegeo:set-contact (find-edge-id (position 0 2.0 0.0)) "P")

(sdegeo:set-contact (find-edge-id (position -10 10 0.0)) "left_handle")

(sdegeo:set-contact (find-edge-id (position 10 10 0.0)) "right_handle")

(sdegeo:set-contact (find-edge-id (position 0 50 0.0)) "bottom")

(sdedr:define-constant-profile "Const.Silicon" "BoronActiveConcentration" 1e+15)

(sdedr:define-constant-profile-material "PlaceCD.Silicon" "Const.Silicon" "Silicon")

102

(sdedr:define-refeval-window "BaseLine.Pimplant" "Line" (position -10 0.0 0.0) (position 10 0.0 0.0))

(sdedr:define-analytical-profile-placement "PlaceAP.Pimplant" "Gauss.Pimplant" "BaseLine.Pimplant" "Positive" "NoReplace" "Eval")

(sdedr:define-gaussian-profile "Gauss.Pimplant" "BoronActiveConcentration" "PeakPos" 0.0 "PeakVal" 1e18 "ValueAtDepth" 1e17 "Depth" 1.2 "Gauss" "Factor" 0.8)

(sdedr:define-refeval-window "BaseLine.Nimplant" "Line" (position -10 0.0 0.0) (position 10 0.0 0.0))

(sdedr:define-analytical-profile-placement "PlaceAP.Nimplant" "Gauss.Nimplant" "BaseLine.Nimplant" "Positive" "NoReplace" "Eval")

(sdedr:define-gaussian-profile "Gauss.Nimplant" "PhosphorusActiveConcentration" "PeakPos" 0.0 "PeakVal" 1e19 "ValueAtDepth" 1e17 "Depth" 0.7 "Gauss" "Factor" 0.8)

(sdedr:define-refeval-window "REW_strain" "Rectangle" (position -10 0 0) (position 10 2 0))

(sdedr:define-analytical-profile-placement "APP_strain" "APD_strain" "REW_strain" "Positive" "NoReplace" "Eval" "Silicon" 0 "material")

(sdedr:define-gaussian-profile "APD_strain" "StressYY" "PeakPos" 0 "PeakVal" @stress@ "StdDev" 0.1 "Gauss" "Factor" 1.0)

(sdedr:define-refeval-window "RefWin.all" "Rectangle" (position -30 -10 0) (position 30 60 0))

(sdedr:define-refinement-size "RefDef.all" 5.0 5.0 0.01 0.01)

(sdedr:define-refinement-placement "PlaceRF.all" "RefDef.all" "RefWin.all")

(sdedr:define-refinement-function "RefDef.all" "DopingConcentration" "MaxTransDiff" 1)

(sdedr:define-refinement-function "RefDef.all" "MaxLenInt" "Silicon" "Aluminum" 0.001 1.5 "DoubleSide")

(sdedr:define-refeval-window "RefWin.channel" "Rectangle" (position -4 0.0 0.0) (position 4 2 0.0))

(sdedr:define-refinement-size "RefDef.channel" 0.5 0.5 0.005 0.005)

(sdedr:define-refinement-placement "PlaceRF.channel" "RefDef.channel" "RefWin.channel")

(sde:save-model "n@node@_geo")

;Meshing the device

(sde:build-mesh "" "n@node@")

103

Sentaurus Device

File

Grid = "@tdr@"

Piezo = "@tdr@"

Plot = "@tdrdat@"

Parameter = "@parameter@"

Current = "@plot@"

Output = "@log@"

Electrode

Name="P" Voltage=0.0

Name="N" Voltage=0.0

Thermode

Name="P" Temperature=300 SurfaceResistance=0.00001

Name="N" Temperature=300 SurfaceResistance=0.00001

Name="left_handle" Temperature=300 SurfaceResistance=0.00001

Name="right_handle" Temperature=300 SurfaceResistance=0.00001

Name="bottom" Temperature=300 SurfaceResistance=0.00001

Physics

EffectiveIntrinsicDensity( OldSlotboom )

hMultivalley(MLDA kpDOS -Density)

Mobility(

PhuMob

HighFieldSaturation

104

)

Piezo(

Model(

DeformationPotential(ekp hkp minimum)

DOS( emass hmass )

Mobility( hSubband(Doping EffectiveMass Scattering(MLDA) )

hSaturationFactor= 0.0

)

)

)

Recombination(

SRH( DopingDep )

Band2Band(E2)

Avalanche( Eparallel )

)

Fermi

Math

Iterations=20

Notdamped =100

RelErrControl

AvalDerivatives

ErrRef(Electron)=1.e10

ErrRef(Hole)=1.e10

BreakCriteria Current(Contact="N" AbsVal=10e-6)

Transient=BE

105

EnormalInterface( MaterialInterface= "Oxide/Silicon" )

Solve

*- Build-up of initial solution:

Coupled(Iterations=100) Poisson

Coupled Poisson Electron Hole

Quasistationary(

InitialStep=@<1e-2/5.0>@ Increment=1.41

MinStep=@<1e-5/5.0>@ MaxStep=0.005

Goal Name="N" Voltage=10.

) Coupled Poisson Electron Hole

QuasiStationary (

InitialStep=1e-4 Maxstep=0.05 MinStep=1e-9 Increment=1.41

Goal name="N" current=10e-6

) Coupled Poisson Electron Hole

Plot

ElectrostaticPotential

eDensity hDensity

DopingConcentration BandGap EffectiveBandGap BandGapNarrowing

eMobility hMobility

SRHRecombination eSRHRecombination hSRHRecombination

ConductionBand ValenceBand

106

eQuantumPotential hQuantumPotential

* These 4 fields needed to make band diagram plots in Svisual

ConductionBandEnergy

ValenceBandEnergy

eGradQuasiFermiEnergy hGradQuasiFermiEnergy

* vector quantities

ElectricField/vector

TotalCurrentDensity/vector

eCurrentDensity/vector

hCurrentDensity/vector

eVelocity/vector

hVelocity/vector

LatticeTemperature

JouleHeat eJouleHeat hJouleHeat

lHeatFlux/vector