USING TCAD TO MINIMIZE PROCESS DISPERSIONS
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Transcript of USING TCAD TO MINIMIZE PROCESS DISPERSIONS
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ALTIS Semiconductor Device Engineering team
Essonne Nanopole
September 20, 2004
USING TCAD TO MINIMIZE
PROCESS DISPERSIONS
G. DUBOIS
D. ANDRADE
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ALTIS Semiconductor Device Engineering team
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INTRODUCTION
CALIBRATION RESULTS
DIM PC PROCESS WINDOW SIMULATION RESULTS
OTHER PROCESS CAUSES OF VARIATION
COMBINED EFFECT OF PROCESS VARIATIONS
CONCLUSION
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ALTIS Semiconductor Device Engineering team
Essonne Nanopole
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A - INTRODUCTION
The goal is to demonstrate that TCAD could be very usefulin identifying the process root causes of transistor electrical parameters dispersion, mainly Ion , Vt and Ioff.The followingstudy was done on a 0.18µm designed gate length CMOSprocess .
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ALTIS Semiconductor Device Engineering team
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CoSi
POLY P+
1.8 V P FET: 1.8 V N FET:
Substrate P- Boron : 5E15 / cm3
.18 CMOS FEOL : SUMMARY
B
As As In
CoSi
POLY N+
BBCoSi Sb
CoSi
POLY P+
AsAs BBCoSi Sb B B
CoSi
STI B
In
CoSi
POLY N+
P FET1.8 V
P FET3.3 V
N FET3.3 V
N FET1.8 V
3.3 V P FET : 3.3 V N FET:
In In CoSiCoSi
PhSTI
AsPh
CoSiPh AsPh
PhSTI
Ph
CoSiB B
STI STI
DEVICES MENU
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B - CALIBRATION
PROCESS CALIBRATION:Impurity diffusion, activation models and dislocation calibration
variables were taken from INFINEON calibration work.
ELECTRICAL CALIBRATION : Mobility model has been shared with INFINEON simulation
group.
RESULTS :I-V Characteristics end up very close to measurements
performed on product.
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ALTIS Semiconductor Device Engineering team
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C10 NFET S/D PROFILS
1,00E+12
1,00E+13
1,00E+14
1,00E+15
1,00E+16
1,00E+17
1,00E+18
1,00E+19
1,00E+20
1,00E+21
1,00E+22
0 0,1 0,2 0,3 0,4 0,5 0,6 0,7 0,8 0,9 1
Y
CO
NC
EN
TR
AT
ION
ARSENIC
PHOPHORUS
INDIUM
BORON
NET DOPING
C10 NFET PWELL UNDERGATE PROFILS
1,00E+12
1,00E+13
1,00E+14
1,00E+15
1,00E+16
1,00E+17
1,00E+18
1,00E+19
1,00E+20
1,00E+21
1,00E+22
0 0,1 0,2 0,3 0,4 0,5 0,6 0,7 0,8 0,9 1
Y
CO
NC
EN
TR
AT
ION
BORON
INDIUM
ARSENIC
PHOSPHORUS
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ALTIS Semiconductor Device Engineering team
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C10 NFET X SECTION AT SILICON SURFACE
1,00E+12
1,00E+13
1,00E+14
1,00E+15
1,00E+16
1,00E+17
1,00E+18
1,00E+19
1,00E+20
1,00E+21
1,00E+22
0 0,1 0,2 0,3 0,4 0,5 0,6 0,7 0,8 0,9 1 1,1 1,2 1,3 1,4 1,5 1,6 1,7 1,8 1,9 2
X
CO
NC
EN
TR
AT
ION
NET DOPING
BORON
ARSENIC
PHOSPHORUS
INDIUMSOURCE DRAIN
FET CHANNEL LENGTH
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C10 NFET 10 x .18
1E-11
1E-10
1E-09
1E-08
1E-07
1E-06
1E-05
0,0001
0,001
0 0,1 0,2 0,3 0,4 0,5 0,6 0,7 0,8 0,9 1 1,1 1,2 1,3 1,4 1,5 1,6 1,7 1,8 1,9 2
VGS
IDS
MEASURE
SIMUL
SIMUL VT ADJ
Simulation properly matches product measurements.
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C – PC DIM PROCESS WINDOW SIMULATION
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C – PC DIM PROCESS WINDOW SIMULATION
The simulation shows a good matching with « the real world ».
Halo implant tailoring allows to reduce the Ion (or Vt) spread,
due to PC DIM variation, within +/- 5 %.
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D - ANALYSIS OF OTHER CAUSES OF
ELECTRICAL VARIATION
1° VARIATION OF EXTENSION IMPLANT DUE TO SCREEN
OXIDE THICKNESS SPREAD.
The extension implant being low energy, it is strongly
influenced
by screen oxide thickness variation…
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POLYSPACER 0
REMAINING Gox + SPACER 0 on Si
REMAINING GOX THICK SPACER 0 THICK SCREEN OX THICK
2nm 9,3nm 5,2nm
0nm 9,3nm 6,3nm
3nm 9,3nm 5,8nm
2nm 8,5nm 4,6nm
2nm 10nm 5,7nm
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TCAD simulation shows that:
A huge variation of remaining gate oxide induces a small
variation of screen oxide.
Screen oxide thickness variation represents 50% of Spacer 0
(poly oxidation thickness) variation.
Consequently, the extension implant is not impacted
by gate oxide, nor Spacer 0 fluctuations.
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2° VARIATION OF ANNEALS TEMPERATURE
Rapid Thermal Process single wafer tools, using infra red
heating systems, may present slight temperature variations inducing
wafer to
wafer, and within wafer, spread.
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E – COMBINED EFFECTS OF PROCESS
VARIATIONS
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TCAD simulation consists in a very efficient support formanufacturing engineers. It indeed provides an accuratesizing of the different processes effect.
Only considering PC dim & T° anneal variations induces85% of the devices electrical parameters total spread. Thosetwo components are the first order root causes of the total device electrical variation.
F – CONCLUSION