Using ECC Feedback to Guide Voltage Speculation …...Process variation Circuit aging Temperature...
Transcript of Using ECC Feedback to Guide Voltage Speculation …...Process variation Circuit aging Temperature...
Using ECC Feedback to Guide Voltage Speculation in Low-Voltage Processors
Anys Bacha and Radu TeodorescuDepartment of Computer Science and Engineering
The Ohio State Universityhttp://arch.cse.ohio-state.edu
Anys Bacha
Energy efficiency is now crucial to all computing markets, especially in the growth areas: mobile and cloud computing.
Energy Efficiency
Using ECC Feedback to Guide Voltage Speculation in Low-Voltage Processors2
Anys Bacha
Process variation Circuit aging
Temperature Voltage noise
Energy inefficient
Microprocessor Challenges
safe Vdd
Vdd
High guardband(10-20%)
nominal Vdd
Using ECC Feedback to Guide Voltage Speculation in Low-Voltage Processors3
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• Razor (Ernst et al. MICRO’03)
• Shadow latches detect/correct errors
• IBM POWER7 (Lefurgy et al. MICRO’11)
• Critical path monitors help avoid errors
• Itanium 9560 (Bacha and Teodorescu ISCA’13)
• ECC conservatively help avoid errors via software speculation
Voltage Speculation
Razor
POWER7
Itanium 9560
Using ECC Feedback to Guide Voltage Speculation in Low-Voltage Processors4
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• Commercial interest in low voltage for substantial energy savings
Intel Claremont solar chip
The Case for Low Voltage Speculation
Using ECC Feedback to Guide Voltage Speculation in Low-Voltage Processors5
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0.5 V 100mV (20%)
1.0 VVdd
DVFS
• Commercial interest in low voltage for substantial energy savings
switching speed
pdf𝑓𝑓 ∝ (𝑉𝑉𝑉𝑉𝑉𝑉 − 𝑉𝑉𝑉𝑉)
High Vdd
Low Vdd
Amplified process variation effects
100mV (10%)
Prohibitive guardbands
Intel Claremont solar chip
The Case for Low Voltage Speculation
0.8 V
Using ECC Feedback to Guide Voltage Speculation in Low-Voltage Processors6
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• Motivation
• ECC-based voltage speculation
• Experimental framework
• Evaluation
Outline
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• Margin exploration of 32nm 8-core CMP at two constant frequencies
nom. Vdd
min Vdd
Vdd
?
2.53 GHz (High Vdd) 340 MHz (Low Vdd)
Margin Reduction (mV)
0 50 100 150 200
Core0Core1Core2Core3Core4Core5Core6Core7
Margin at high Vdd (120mV) Margin at low Vdd (200mV)
0 50 100 150 200
Core0Core1Core2Core3Core4Core5Core6Core7
Margin Reduction (mV)
60%More Margin
Margin Opportunity at Low Voltage
nom. Vdd
min Vdd
Vdd
?
Using ECC Feedback to Guide Voltage Speculation in Low-Voltage Processors8
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Correctable Errors at Low Voltage
0
20
40
60
80
100
120
140
0 20 40 60 80 100 120 140 160
Corr. Error
Margin Reduction (mV)
Err
or R
ate
(Err
./min
)
Using ECC Feedback to Guide Voltage Speculation in Low-Voltage Processors9
Error Free
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Correctable Errors at Low Voltage
0
20
40
60
80
100
120
140
0 20 40 60 80 100 120 140 160
Corr. Error
Margin Reduction (mV)
Err
or R
ate
(Err
./min
)
Error Free
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Correctable Errors at Low Voltage
0
20
40
60
80
100
120
140
0 20 40 60 80 100 120 140 160
Corr. Error
Margin Reduction (mV)
Err
or R
ate
(Err
./min
)
Uncor.Error
Using ECC Feedback to Guide Voltage Speculation in Low-Voltage Processors11
Error Free
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0
20
40
60
80
100
120
140
0 20 40 60 80 100 120 140 160
Corr. Error
Correctable Errors at Low Voltage
Margin Reduction (mV)
Err
or R
ate
(Err
./min
)
Speculation Feedback
Error Free Uncor.Error
• Large buffer zone for speculation
4x CorrectableRange
• Correctable error range is 4x relative to high Vdd
Using ECC Feedback to Guide Voltage Speculation in Low-Voltage Processors12
Error Free
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0
0.2
0.4
0.6
0.8
1
110 120 130 140 150 160 170 180 190 200 210
Margin Reduction (mV)
Predictability of Select Cache LinesP
roba
bilit
y of
Cor
r. E
rror
s
Select cache lines consistently react to Vdd reduction
Using ECC Feedback to Guide Voltage Speculation in Low-Voltage Processors13
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• Motivation
• ECC-based voltage speculation
• Experimental framework
• Evaluation
Outline
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• Main idea:
• Dynamically lower Vdd at constant frequency
• Treat correctable errors as “early warning system”
810mV
600mV
Vdd
ECC Guided Voltage Speculation
CautionECC Feedback
cache lineBIST
Built-In Self-Test
Using ECC Feedback to Guide Voltage Speculation in Low-Voltage Processors15
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Continuous monitoring of weakest cache line
ECC Guided Voltage Speculation
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Way 1
Set 2
VddSet 0
Set 1
Set 2
Set 3
Way 1
Discovery Phase
Way 2 Way 3Way 0
ECC Guided Voltage Speculation
Access Count
Err. CountECC Monitor
Test Pattern
Address
0x5A5A5A5A5A
X
Continuous monitoring of weakest cache line
Using ECC Feedback to Guide Voltage Speculation in Low-Voltage Processors17
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Set 0
Set 1
Set 2
Set 3
Way 1
Runtime Phase
Way 2 Way 3Way 0
ECC Guided Voltage Speculation
Set 2
Way 1
Access Count
Err. CountECC Monitor
Test Pattern
Address
0x5A5A5A5A5APWR CTL
Way 1Set 2 0x3
0x1
Continuous monitoring of weakest cache line
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ECC Guided Voltage Speculation
Access Count
Err. CountECC Monitor
Test Pattern
Address
0x5A5A5A5A5APWR CTL
Way 1Set 2 0x3
0x1
Err
or R
ate
Cor
e V
dd
Max Threshold
Min Threshold
Adjust Vdd?
Continuous monitoring of weakest cache line
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ECC Monitor
Core 0
Core 1
Core 7
Core 6
Core 2
Core 3
Core 5
Core 4
System Logic
LLC
LLC
PWR CTL
I$
D$
I$
D$
I$
D$
I$
D$
I$
D$
I$
D$
I$
D$
I$
D$
ECC Monitors and Activation
• ECC monitors to probe vulnerable cache lines
8-core CMP with ECC monitors
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ECC Monitors and Activation
• ECC monitors to probe vulnerable cache lines
• Activate single monitor across Vdd domain
Core 0
Core 1
Core 7
Core 6
Core 2
Core 3
Core 5
Core 4
System Logic
LLC
LLC
PWR CTL
I$
D$
I$
D$
I$
D$
I$
D$
I$
D$
I$
D$
I$
D$
I$
D$
ECC Monitor
8-core CMP with ECC monitors
Vdd Domain
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• Motivation
• ECC-based voltage speculation
• Experimental framework
• Evaluation
Outline
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• System:
• BL860c-i4 Integrity Server from HP
• 2x 9560 Itanium II CPUs
• Simulation (Firmware):
• HW thread to monitor weak cache line
• Dedicated “service” core for error logging and power measurements
• Benchmarks:
• CoreMark, SPEC CPU2000, SPECjbb2005, and stress test application
VRAdapt Voltage
Core ECC Event
Self-test
WorkloadHW Thread 0
Operating System
System
Firmw
are
HW Thread1Monitor
Cache
Experimental Framework
Using ECC Feedback to Guide Voltage Speculation in Low-Voltage Processors23
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• Motivation
• ECC-based voltage speculation
• Experimental framework
• Evaluation
Outline
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Vdd adapts to changing conditions and context switches using error rate as feedback
Voltage Speculation in Action
Using ECC Feedback to Guide Voltage Speculation in Low-Voltage Processors25
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Vdd adapts to changing conditions and context switches using error rate as feedback
Voltage Speculation in Action
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18% average Vdd reduction
Rel
ativ
e S
uppl
y V
olta
ge
10%
Supply Voltage Reduction
Using ECC Feedback to Guide Voltage Speculation in Low-Voltage Processors27
0.5
0.6
0.7
0.8
0.9
1
Core 0 Core 1 Core 2 Core 3 Core 4 Core 5 Core 6 Core 7
CoreMark SPECjbb SPECint SPECfp
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0
0.2
0.4
0.6
0.8
1
CoreMark Specjbb2005 SPECint SPECfp
Rel
ativ
e P
ower
Power Savings
33% power reduction across all cores
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• Exploit auxiliary core within core cluster to stress Vdd
Core 1
Core Cluster
VR
Core 0
Shared Vdd
Speculation Sensitivity to Workload
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• Exploit auxiliary core within core cluster to stress Vdd
Core 1
VR
Core 0
Shared Vdd
Linpack
Core Cluster
Speculation Sensitivity to Workload
Execute(30 seconds)
Throttle(30 seconds)
Using ECC Feedback to Guide Voltage Speculation in Low-Voltage Processors30
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• Exploit auxiliary core within core cluster to stress Vdd
Core 1
VR
Core 0
Shared Vdd
Linpack
Core Cluster
Cache
ECC weak line
ECC Event Self-test
Self-test Code
Speculation Sensitivity to Workload
Execute(30 seconds)
Throttle(30 seconds)
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• Exploit auxiliary core within core cluster to stress Vdd
Core 1
VR
Execute(30 seconds)
Throttle(30 seconds)
Core 0
Shared Vdd
Linpack
Core Cluster
Cache
ECC weak line
ECC Event Self-test
Self-test Code
Speculation Sensitivity to Workload
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• Similarly exploit auxiliary core within core cluster to induce noise
Resiliency to Voltage Noise
Core 1
VR
Core 0
Shared Vdd
Core Cluster
Cache
ECC weak line
ECC Event Self-test
Self-test Code
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• Similarly exploit auxiliary core within core cluster to induce noise Core 1
VR
High-power cycles(FP Instructions)
Low-power cycles(NOP Instructions)
Core 0
Shared Vdd
CalibratedVoltage Virus
Core Cluster
Cache
ECC weak line
ECC Event Self-test
Self-test Code
Resiliency to Voltage Noise
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• Similarly exploit auxiliary core within core cluster to induce noise Core 1
VR
High-power cycles(FP Instructions)
Low-power cycles(NOP Instructions)
Core 0
Shared Vdd
Core Cluster
Cache
ECC weak line
ECC Event Self-test
Self-test CodeCalibrated
Voltage Virus
Resiliency to Voltage Noise
CPU Cycles
Cur
rent
8
fadd f81, f28, f83
…
24
fadd f81, f28, f83
…
16
NOP
Variable period
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• Similarly exploit auxiliary core within core cluster to induce noise Core 1
VR
High-power cycles(FP Instructions)
Low-power cycles(NOP Instructions)
Core 0
Shared Vdd
Core Cluster
Cache
ECC weak line
ECC Event Self-test
Self-test Code
Rel
. Cor
rect
able
Err
ors
0
0.2
0.4
0.6
0.8
1
0 2 4 6 8 10 12 14 16 18 20
NOP/Active Cycles
CalibratedVoltage Virus
Resiliency to Voltage Noise
CPU Cycles
Cur
rent
8
fadd f81, f28, f83
…
24
fadd f81, f28, f83
…
16
NOP
Variable period
Using ECC Feedback to Guide Voltage Speculation in Low-Voltage Processors36
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• Similarly exploit auxiliary core within core cluster to induce noise
Rel
. Cor
rect
able
Err
ors
0
0.2
0.4
0.6
0.8
1
0 2 4 6 8 10 12 14 16 18 20
Core 1
VR
High-power cycles(FP Instructions)
Low-power cycles(NOP Instructions)
Core 0
Shared Vdd
Core Cluster
Cache
ECC weak line
ECC Event Self-test
Self-test CodeCalibrated
Voltage Virus
Resiliency to Voltage Noise
CPU Cycles
Cur
rent
8
fadd f81, f28, f83
…
24
fadd f81, f28, f83
…
16
NOP
Variable period
NOP/Active Cycles
Using ECC Feedback to Guide Voltage Speculation in Low-Voltage Processors37
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00.5
11.5
22.5
3
0.81 0.76 0.71 0.66 0.61
Hardware Speculation Software Speculation
Supply Voltage (V)
0
0.2
0.4
0.6
0.8
1
CoreMark Specjbb2005 SPECint SPECfp
Software Speculation Hardware Speculation
Rel
ativ
e E
nerg
y• Handling errors at low Vdd in
software is energy inefficient
• 33% in energy savings
• 11% improvement in energy efficiency over software speculation approach
Rel
ativ
e E
nerg
y
Energy Savings
(ISCA’13) (MICRO’14)
(ISCA’13)(MICRO’14)
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• Cache lines can be used for speculation in low voltage
• Demonstrate sensitivity of technique to noise
• Deliver 33% in energy savings
• Evaluate on real system
Conclusion
Using ECC Feedback to Guide Voltage Speculation in Low-Voltage Processors39
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Thank you!
Questions?
Using ECC Feedback to Guide Voltage Speculation in Low-Voltage Processors40
Using ECC Feedback to Guide Voltage Speculation in Low-Voltage Processors
Anys Bacha and Radu TeodorescuDepartment of Computer Science and Engineering
The Ohio State Universityhttp://arch.cse.ohio-state.edu