UPPAAL Introduction Chien-Liang Chen. Outline Real-Time Verification and Validation Tools Promela...

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UPPAAL Introduction Chien-Liang Chen

Transcript of UPPAAL Introduction Chien-Liang Chen. Outline Real-Time Verification and Validation Tools Promela...

Page 1: UPPAAL Introduction Chien-Liang Chen. Outline Real-Time Verification and Validation Tools  Promela and SPIN Simulation Verification  Real-Time Extensions:

UPPAAL Introduction

Chien-Liang Chen

Page 2: UPPAAL Introduction Chien-Liang Chen. Outline Real-Time Verification and Validation Tools  Promela and SPIN Simulation Verification  Real-Time Extensions:

Outline

Real-Time Verification and Validation Tools Promela and SPIN

Simulation Verification

Real-Time Extensions: RT-SPIN – Real-Time extensions to SPIN UPPAAL – Toolbox for validation and verification of

real-time systems

Page 3: UPPAAL Introduction Chien-Liang Chen. Outline Real-Time Verification and Validation Tools  Promela and SPIN Simulation Verification  Real-Time Extensions:

Modelling

Page 4: UPPAAL Introduction Chien-Liang Chen. Outline Real-Time Verification and Validation Tools  Promela and SPIN Simulation Verification  Real-Time Extensions:

UPPAAL UPPAAL is a tool box for simulation and verification of re

al-time systems based on constraint solving and other techniques.

UPPAAL was developed jointly by Uppsala University and Aalborg University.

It can be used for systems that are modeled as a collection of non-deterministic processes w/ finite control structures and real-valued clocks, communicating through channels and/or shared variables.

It is designed primarily to check both invariants and reachability properties by exploring the statespace of a system.

Page 5: UPPAAL Introduction Chien-Liang Chen. Outline Real-Time Verification and Validation Tools  Promela and SPIN Simulation Verification  Real-Time Extensions:

UPPAAL Components UPPAAL consists of three main parts:

a description language, a simulator, and a model checker.

The description language is a non-deterministic guarded command language with data types. It can be used to describe a system as a network of timed automata using either a graphical (*.atg, *.xml) or textual (*.xta) format.

The simulator enables examination of possible dynamic executions of a system during the early modeling stages.

The model checker exhaustively checks all possible states.

Page 6: UPPAAL Introduction Chien-Liang Chen. Outline Real-Time Verification and Validation Tools  Promela and SPIN Simulation Verification  Real-Time Extensions:

UPPAAL Tools (earlier version)

checkta – syntax checker simta – simulator verifyta – model checker

Page 7: UPPAAL Introduction Chien-Liang Chen. Outline Real-Time Verification and Validation Tools  Promela and SPIN Simulation Verification  Real-Time Extensions:

Example – .xta file format (from UPPAAL in a Nutshell)clock x, y;int n;chan a;

process A { state A0 { y<=6 }, A1, A2, A3; init A0; trans A0 -> A1 { guard y>=3; sync a!; assign y:=0; }, A1 -> A2 { guard y>=4; }, A2 -> A3 { guard n==5; }, A3 -> A0;}

Page 8: UPPAAL Introduction Chien-Liang Chen. Outline Real-Time Verification and Validation Tools  Promela and SPIN Simulation Verification  Real-Time Extensions:

Example (cont.) (from UPPAAL in a Nutshell)

process B { state B0 { x<=4 }, B1, B2, B3; commit B1; init B0; trans B0 -> B1 { guard x>=2; sync a?; assign n:=5,x:=0; }, B1 -> B2 { assign n:=n+1; }, B2 -> B3 { }, B3 -> B0;}

system A, B;

Page 9: UPPAAL Introduction Chien-Liang Chen. Outline Real-Time Verification and Validation Tools  Promela and SPIN Simulation Verification  Real-Time Extensions:

Example (cont.)

Page 10: UPPAAL Introduction Chien-Liang Chen. Outline Real-Time Verification and Validation Tools  Promela and SPIN Simulation Verification  Real-Time Extensions:

Linear Temporal Logic (LTL) LTL formulae are used to specify temporal

properties. LTL includes propositional logic and temporal

operators: [ ]P = always P <>P = eventually P P U Q = P is true until Q becomes true

Examples: Invariance: [ ] (p) Response: [ ] ((p) -> (<> (q))) Precedence: [ ] ((p) -> ((q) U (r))) Objective: [ ] ((p) -> <>((q) || (r)))

Page 11: UPPAAL Introduction Chien-Liang Chen. Outline Real-Time Verification and Validation Tools  Promela and SPIN Simulation Verification  Real-Time Extensions:

Labels and Transitions

The edges of the automata can be labeled with three different types of labels: a guard expressing a condition on the values of clocks

and integer variables that must be satised in order for the edge to be taken,

a synchronization action which is performed when the edge is taken, and

a number of clock resets and assignments to integer variables.

Nodes may be labeled with invariants; that is, conditions expressing constraints on the clock values in order for control to remain in a particular node.

Page 12: UPPAAL Introduction Chien-Liang Chen. Outline Real-Time Verification and Validation Tools  Promela and SPIN Simulation Verification  Real-Time Extensions:

Committed Locations

A committed location must be left immediately. A broadcast can be represented by two transitions with a committed state between sends.

Page 13: UPPAAL Introduction Chien-Liang Chen. Outline Real-Time Verification and Validation Tools  Promela and SPIN Simulation Verification  Real-Time Extensions:

• Action transitions – if two complementary edges of two different components are enabled in a state, then they can synchronize; also, if a component has an enabled internal edge, the edge can be taken without any synchronizaton; e.g., from ((A0,B0),x=3.5,y=3.5,n=0) the two components can synchronize to ((A1,B1),x=0,y=0,n=5).

Transitions Delay transitions – if none of the invariants of the

nodes in the current state are violated, time may progress without making a transition; e.g., from ((A0,B0),x=0,y=0,n=0), time may elapse 3.5 units to ((A0,B0),x=3.5,y=3.5,n=0), but time cannot elapse 5 time units because that would violate the invariant on B0.

Page 14: UPPAAL Introduction Chien-Liang Chen. Outline Real-Time Verification and Validation Tools  Promela and SPIN Simulation Verification  Real-Time Extensions:

Action transitions – if two complementary edges of two different components are enabled in a state, then they can synchronize; also, if a component has an enabled internal edge, the edge can be taken without any synchronizaton; e.g., from ((A

0,B0),x=0,y=0,n=0) the two components can synchronize to ((A1,B1),x=0,y=0,n=5).

Transitions (cont.)

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UPPAAL Transitions

Page 16: UPPAAL Introduction Chien-Liang Chen. Outline Real-Time Verification and Validation Tools  Promela and SPIN Simulation Verification  Real-Time Extensions:

Urgent Channels and Committed Locations Transitions can be overruled by the presence of

urgent channels and committed locations: When two components can synchronize on an urgent

channel, no further delay is allowed; e.g., if channel a is urgent, time could not elapse beyond 3, because in state ((A0,B0),x=3,y=3,n=0), synchronization on channel a is enabled.

Page 17: UPPAAL Introduction Chien-Liang Chen. Outline Real-Time Verification and Validation Tools  Promela and SPIN Simulation Verification  Real-Time Extensions:

Committed Nodes Transitions can be overruled by the presence of urge

nt channels and committed locations:

If one of the components is in a committed node, no delay is allowed to occur and any action transition must involve the component committed to continue; e.g., in state ((A1,B1),x=0,y=0,n=5), B1 is commited, so the next state of the network is ((A1,B2),x=0,y=0,n=6).

Page 18: UPPAAL Introduction Chien-Liang Chen. Outline Real-Time Verification and Validation Tools  Promela and SPIN Simulation Verification  Real-Time Extensions:

UPPAAL Locations

Page 19: UPPAAL Introduction Chien-Liang Chen. Outline Real-Time Verification and Validation Tools  Promela and SPIN Simulation Verification  Real-Time Extensions:

Translation to UPPAAL

P1 :: while True doT1 : wait(turn=1)C1 : turn:=0endwhile

||P2 :: while True do

T2 : wait(turn=0)C2 : turn:=1endwhile

P1 :: while True doT1 : wait(turn=1)C1 : turn:=0endwhile

||P2 :: while True do

T2 : wait(turn=0)C2 : turn:=1endwhile

Mutual Exclusion Program

Page 20: UPPAAL Introduction Chien-Liang Chen. Outline Real-Time Verification and Validation Tools  Promela and SPIN Simulation Verification  Real-Time Extensions:

Example: Mutual Exclusion

Page 21: UPPAAL Introduction Chien-Liang Chen. Outline Real-Time Verification and Validation Tools  Promela and SPIN Simulation Verification  Real-Time Extensions:

Intelligent Light Control

Off Light Brightpress? press?

press?

press?

• Requirements: If a user quickly presses the light control twice, then the light should get brighter; on the other hand, if the user slowly presses the light control twice, the light should turn off.

• Solution: Add a real-valued clock, x.

x:=0

x>3

x<=3

Page 22: UPPAAL Introduction Chien-Liang Chen. Outline Real-Time Verification and Validation Tools  Promela and SPIN Simulation Verification  Real-Time Extensions:

UPPAAL Model =Networks of Timed Automata

A timed automaton is a standard finite state automaton extended with a finite collection of real-valued clocks.

Page 23: UPPAAL Introduction Chien-Liang Chen. Outline Real-Time Verification and Validation Tools  Promela and SPIN Simulation Verification  Real-Time Extensions:

Timed Automata

n

m

a

Alur & Dill 1990Clocks: x, y

x<=5 && y>3

x := 0

Guard Boolean combination of comp withinteger bounds

ResetAction perfomed on clocks

Transitions

( n , x=2.4 , y=3.1415 ) ( n , x=3.5 , y=4.2415 )

e(1.1)

( n , x=2.4 , y=3.1415 ) ( m , x=0 , y=3.1415 )

a

State ( location , x=v , y=u ) where v,u are in R

Actionused

for synchronization

Page 24: UPPAAL Introduction Chien-Liang Chen. Outline Real-Time Verification and Validation Tools  Promela and SPIN Simulation Verification  Real-Time Extensions:

n

m

a

Clocks: x, y

x<=5 & y>3

x := 0

Transitions

( n , x=2.4 , y=3.1415 ) ( n , x=3.5 , y=4.2415 )

e(1.1)

( n , x=2.4 , y=3.1415 )

e(3.2)

x<=5

y<=10

LocationInvariants

g1g2 g3

g4

Invariants ensure progress.

Timed Automata - Invariants

Page 25: UPPAAL Introduction Chien-Liang Chen. Outline Real-Time Verification and Validation Tools  Promela and SPIN Simulation Verification  Real-Time Extensions:

A simple program

Int x

Process Pdo:: x<2000 x:=x+1od

Process Qdo:: x>0 x:=x-1od

Process Rdo:: x=2000 x:=0od

fork P; fork Q; fork R

Int x

Process Pdo:: x<2000 x:=x+1od

Process Qdo:: x>0 x:=x-1od

Process Rdo:: x=2000 x:=0od

fork P; fork Q; fork R

What are possible values for x?

Questions/Properties:

E<>(x>1000)E<>(x>2000)A[](x<=2000)E<>(x<0)A[](x>=0)Possible

Always

Page 26: UPPAAL Introduction Chien-Liang Chen. Outline Real-Time Verification and Validation Tools  Promela and SPIN Simulation Verification  Real-Time Extensions:

Verification (example.xta)int x:=0;process P{state S0;init S0;trans S0 -> S0{guard x<2000; assign x:=x+1; };}process Q{state S1;init S1;trans S1 -> S1{guard x>0; assign x:=x-1; };}process R{state S2;init S2;trans S2 -> S2{guard x==0; assign x:=0; };}p1:=P();q1:=Q();r1:=R();system p1,q1,r1;

Int x

Process Pdo:: x<2000 x:=x+1od

Process Qdo:: x>0 x:=x-1od

Process Rdo:: x=2000 x:=0od

fork P; fork Q; fork R

Int x

Process Pdo:: x<2000 x:=x+1od

Process Qdo:: x>0 x:=x-1od

Process Rdo:: x=2000 x:=0od

fork P; fork Q; fork R

Page 27: UPPAAL Introduction Chien-Liang Chen. Outline Real-Time Verification and Validation Tools  Promela and SPIN Simulation Verification  Real-Time Extensions:

BNF for q-format

Page 28: UPPAAL Introduction Chien-Liang Chen. Outline Real-Time Verification and Validation Tools  Promela and SPIN Simulation Verification  Real-Time Extensions:

Example: Mutual Exclusion

Page 29: UPPAAL Introduction Chien-Liang Chen. Outline Real-Time Verification and Validation Tools  Promela and SPIN Simulation Verification  Real-Time Extensions:

Example (mutex2.xta)

//Global declarationsint turn;int in_CS;

//Process templateprocess P(const id){clock x;state Idle, Try, Crit;init Idle;trans Idle -> Try{assign turn:=id, x:=0; },Try -> Crit{guard turn==(1-id); assign in_CS:=in_CS+1; },Try -> Try{guard turn==id; },Crit -> Idle{guard x>3; assign in_CS:=in_CS-1; };}

//Process assignmentsP1:=P(1);P2:=P(0);

//System definition.system P1, P2;

Page 30: UPPAAL Introduction Chien-Liang Chen. Outline Real-Time Verification and Validation Tools  Promela and SPIN Simulation Verification  Real-Time Extensions:

From UPPAAL-time Models to Kripke Structures

I1 I2t=0

T1 I2t=0

T1 T2t=0

I1 T2t=0

I1 C2t=0

T1 C2t=0

C1 I2t=1

T1 T2t=1

C1 T2t=1

T1 I2t=1

I1 T2t=1

I1 I2t=1

Page 31: UPPAAL Introduction Chien-Liang Chen. Outline Real-Time Verification and Validation Tools  Promela and SPIN Simulation Verification  Real-Time Extensions:

CTL Models

Page 32: UPPAAL Introduction Chien-Liang Chen. Outline Real-Time Verification and Validation Tools  Promela and SPIN Simulation Verification  Real-Time Extensions:

Computation Tree Logic, CTL(Clarke and Emerson, 1980)

Syntax

Page 33: UPPAAL Introduction Chien-Liang Chen. Outline Real-Time Verification and Validation Tools  Promela and SPIN Simulation Verification  Real-Time Extensions:

Example(from UPPAAL2k: Small Tutorial)

P1Obs

Page 34: UPPAAL Introduction Chien-Liang Chen. Outline Real-Time Verification and Validation Tools  Promela and SPIN Simulation Verification  Real-Time Extensions:

Example (cont.)

Page 35: UPPAAL Introduction Chien-Liang Chen. Outline Real-Time Verification and Validation Tools  Promela and SPIN Simulation Verification  Real-Time Extensions:

Example (cont.)

Verification: A[](Obs.taken imply x>=2) E<>(Obs.idle and x>3) E<>(Obs.idle and x>3000)

P1 Obs

Page 36: UPPAAL Introduction Chien-Liang Chen. Outline Real-Time Verification and Validation Tools  Promela and SPIN Simulation Verification  Real-Time Extensions:

Example (cont.)

Page 37: UPPAAL Introduction Chien-Liang Chen. Outline Real-Time Verification and Validation Tools  Promela and SPIN Simulation Verification  Real-Time Extensions:

Example (cont.)

Page 38: UPPAAL Introduction Chien-Liang Chen. Outline Real-Time Verification and Validation Tools  Promela and SPIN Simulation Verification  Real-Time Extensions:

Translation to UPPAAL

P1 :: while True doT1 : wait(turn=1)C1 : turn:=0endwhile

||P2 :: while True do

T2 : wait(turn=0)C2 : turn:=1endwhile

P1 :: while True doT1 : wait(turn=1)C1 : turn:=0endwhile

||P2 :: while True do

T2 : wait(turn=0)C2 : turn:=1endwhile

Mutual Exclusion Program

Page 39: UPPAAL Introduction Chien-Liang Chen. Outline Real-Time Verification and Validation Tools  Promela and SPIN Simulation Verification  Real-Time Extensions:

CTL Models

Page 40: UPPAAL Introduction Chien-Liang Chen. Outline Real-Time Verification and Validation Tools  Promela and SPIN Simulation Verification  Real-Time Extensions:

Computation Tree Logic, CTL(Clarke and Emerson, 1980)

Syntax

Page 41: UPPAAL Introduction Chien-Liang Chen. Outline Real-Time Verification and Validation Tools  Promela and SPIN Simulation Verification  Real-Time Extensions:

Path

p

p

p

s s1s2 s3...

The set of path starting in s

Page 42: UPPAAL Introduction Chien-Liang Chen. Outline Real-Time Verification and Validation Tools  Promela and SPIN Simulation Verification  Real-Time Extensions:

Formal Semantics

Page 43: UPPAAL Introduction Chien-Liang Chen. Outline Real-Time Verification and Validation Tools  Promela and SPIN Simulation Verification  Real-Time Extensions:

CTL, Derived Operators

. . .

. . .

. . .

. . .

p

p p

AF p

. . .

. . .

. . .

. . .

p

EF p

possibleinevitable

Page 44: UPPAAL Introduction Chien-Liang Chen. Outline Real-Time Verification and Validation Tools  Promela and SPIN Simulation Verification  Real-Time Extensions:

CTL, Derived Operators

p p

p

. . .

. . .

. . .

. . .

AG p

p p p p

p

p

. . .

. . .

. . .

. . .EG p

p

always

potentially always

Page 45: UPPAAL Introduction Chien-Liang Chen. Outline Real-Time Verification and Validation Tools  Promela and SPIN Simulation Verification  Real-Time Extensions:

Theorem

All operators are derivable from

• EX f • EG f • E[ f U g ]

and boolean connectives

All operators are derivable from

• EX f • EG f • E[ f U g ]

and boolean connectives

ggfggf EGUE U A

Page 46: UPPAAL Introduction Chien-Liang Chen. Outline Real-Time Verification and Validation Tools  Promela and SPIN Simulation Verification  Real-Time Extensions:

UPPAAL Specification Language A[] p (AG p)

E<> p (EF p)

p::= a.l | gd | gc | p and p |

p or p | not p | p imply p |

( p )

clock guardsdata guardsprocess location

Page 47: UPPAAL Introduction Chien-Liang Chen. Outline Real-Time Verification and Validation Tools  Promela and SPIN Simulation Verification  Real-Time Extensions:

Semantics: Example

...)9,0,()9),3(9,(

)3,3,(),0,(

),()0,(

)5.3,()0,(

)3(93

5.3

yxoffyxon

yxonyxon

yxonyxon

yxoffyxoff

click

push

push

push

pushclick9y

Page 48: UPPAAL Introduction Chien-Liang Chen. Outline Real-Time Verification and Validation Tools  Promela and SPIN Simulation Verification  Real-Time Extensions:

Light Switch (cont.)

push

pushclick

onx

onx

xoff

xoff

xoff

offon

offon

yx

U E

U A

U E

U A

U A

)AFAG(

)AFAG(

)AG(

2

2

3

3

2

9

9y

A[] (x <= y)

P.on --> P.off

Page 49: UPPAAL Introduction Chien-Liang Chen. Outline Real-Time Verification and Validation Tools  Promela and SPIN Simulation Verification  Real-Time Extensions:

Paths

Example Path:

push

pushclick9y

...)9,0,()9),3(9,(

)3,3,(),0,(

),()0,(

)5.3,()0,(

)3(93

5.3

yxoffyxon

yxonyxon

yxonyxon

yxoffyxoff

click

push

push

Page 50: UPPAAL Introduction Chien-Liang Chen. Outline Real-Time Verification and Validation Tools  Promela and SPIN Simulation Verification  Real-Time Extensions:

Elapsed Time in Path

...)9,0,()9),3(9,(

)3,3,(),0,(

),()0,(

)5.3,()0,(

)3(93

5.3

yxoffyxon

yxonyxon

yxonyxon

yxoffyxoff

click

push

push

Example:

Page 51: UPPAAL Introduction Chien-Liang Chen. Outline Real-Time Verification and Validation Tools  Promela and SPIN Simulation Verification  Real-Time Extensions:

Infinite State Space?

Page 52: UPPAAL Introduction Chien-Liang Chen. Outline Real-Time Verification and Validation Tools  Promela and SPIN Simulation Verification  Real-Time Extensions:

RegionsFinite partitioning of state space

x

y Definition

max

'

n

nxxnx

w'www

jii

where

and

form the

of conditions same exact the

satisfy and iff

An equivalence class (i.e. a region)in fact there are only a finite number of regions!

1 2 3

1

2

Page 53: UPPAAL Introduction Chien-Liang Chen. Outline Real-Time Verification and Validation Tools  Promela and SPIN Simulation Verification  Real-Time Extensions:

RegionsFinite partitioning of state space

x

y Definition

max

'

n

nxxnx

w'www

jii

where

and

form the

of conditions same exact the

satisfy and iff

An equivalence class (i.e. a region)

Successor regions, Succ(r)

r

1 2 3

1

2

Page 54: UPPAAL Introduction Chien-Liang Chen. Outline Real-Time Verification and Validation Tools  Promela and SPIN Simulation Verification  Real-Time Extensions:

RegionsFinite partitioning of state space

x

y

Definition

max

'

n

nxxnx

w'www

jii

where

and

form the

of conditions same exact the

satisfy and iff

An equivalence class (i.e. a region) r

{x}r

{y}r

r

Resetregions

sat

sat

then Whenever

','

,

''

vl,u

vl,u

vuuv

THEOREM

1 2 3

1

2

Page 55: UPPAAL Introduction Chien-Liang Chen. Outline Real-Time Verification and Validation Tools  Promela and SPIN Simulation Verification  Real-Time Extensions:

Region graph of simple timed automata

Page 56: UPPAAL Introduction Chien-Liang Chen. Outline Real-Time Verification and Validation Tools  Promela and SPIN Simulation Verification  Real-Time Extensions:

Modified light switch

Page 57: UPPAAL Introduction Chien-Liang Chen. Outline Real-Time Verification and Validation Tools  Promela and SPIN Simulation Verification  Real-Time Extensions:

)AFAG(

)AFAG(

)AG(

3offon

offon

yx

Reachable partof region graph

Properties

Page 58: UPPAAL Introduction Chien-Liang Chen. Outline Real-Time Verification and Validation Tools  Promela and SPIN Simulation Verification  Real-Time Extensions:

Roughly speaking....

Model checking a timed automata against a TCTL-formula amounts to

model checking its region graph against a CTL-formula

Model checking a timed automata against a TCTL-formula amounts to

model checking its region graph against a CTL-formula

Page 59: UPPAAL Introduction Chien-Liang Chen. Outline Real-Time Verification and Validation Tools  Promela and SPIN Simulation Verification  Real-Time Extensions:

Problem to be solved

Model Checking TCTL is PSPACE-hard

Page 60: UPPAAL Introduction Chien-Liang Chen. Outline Real-Time Verification and Validation Tools  Promela and SPIN Simulation Verification  Real-Time Extensions:

Zones: From Infinite to Finite

State(n, x=3.2, y=2.5)

x

y

x

y

Symbolic state (set)(n, )

Zone:conjunction ofx-y<=n, x<=>n

3y4,1x1

Page 61: UPPAAL Introduction Chien-Liang Chen. Outline Real-Time Verification and Validation Tools  Promela and SPIN Simulation Verification  Real-Time Extensions:

61

Symbolic Transitions

n

m

x>3

y:=0

x

ydelays to

x

y

x

y conjuncts to

x

y

projects to

1<=x<=41<=y<=3

1<=x, 1<=y-2<=x-y<=3

3<x, 1<=y-2<=x-y<=3

3<x, y=0

Thus (n,1<=x<=4,1<=y<=3) =a => (m, 3<x, y=0)

a

Page 62: UPPAAL Introduction Chien-Liang Chen. Outline Real-Time Verification and Validation Tools  Promela and SPIN Simulation Verification  Real-Time Extensions:

Forward Reachability

Passed

WaitingFinal

Init

INITIAL Passed := Ø; Waiting := {(n0,Z0)}

REPEAT - pick (n,Z) in Waiting - if for some Z’ Z (n,Z’) in Passed then STOP - else (explore) add

{ (m,U) : (n,Z) => (m,U) } to Waiting; Add (n,Z) to Passed

UNTIL Waiting = Ø or Final is in Waiting

Init -> Final ?

Page 63: UPPAAL Introduction Chien-Liang Chen. Outline Real-Time Verification and Validation Tools  Promela and SPIN Simulation Verification  Real-Time Extensions:

Forward Reachability

Passed

Waiting Final

Init

n,Z

INITIAL Passed := Ø; Waiting := {(n0,Z0)}

REPEAT - pick (n,Z) in Waiting - if for some Z’ Z (n,Z’) in Passed then STOP - else (explore) add

{ (m,U) : (n,Z) => (m,U) } to Waiting; Add (n,Z) to Passed

UNTIL Waiting = Ø or Final is in Waiting

n,Z’

Init -> Final ?

Page 64: UPPAAL Introduction Chien-Liang Chen. Outline Real-Time Verification and Validation Tools  Promela and SPIN Simulation Verification  Real-Time Extensions:

Forward Reachability

Passed

Waiting Final

Init

n,Z

INITIAL Passed := Ø; Waiting := {(n0,Z0)}

REPEAT - pick (n,Z) in Waiting - if for some Z’ Z (n,Z’) in Passed then STOP - else /explore/ add

{ (m,U) : (n,Z) => (m,U) } to Waiting; Add (n,Z) to Passed

UNTIL Waiting = Ø or Final is in Waiting

n,Z’

m,U

Init -> Final ?

Page 65: UPPAAL Introduction Chien-Liang Chen. Outline Real-Time Verification and Validation Tools  Promela and SPIN Simulation Verification  Real-Time Extensions:

Forward Reachability

Passed

Waiting Final

Init

INITIAL Passed := Ø; Waiting := {(n0,Z0)}

REPEAT - pick (n,Z) in Waiting - if for some Z’ Z (n,Z’) in Passed then STOP - else /explore/ add

{ (m,U) : (n,Z) => (m,U) } to Waiting; Add (n,Z) to Passed

UNTIL Waiting = Ø or Final is in Waiting

n,Z’

m,U

n,Z

Init -> Final ?

Page 66: UPPAAL Introduction Chien-Liang Chen. Outline Real-Time Verification and Validation Tools  Promela and SPIN Simulation Verification  Real-Time Extensions:

UPPAAL Verification Options

• Diagnostic Trace

• Breadth-First• Depth-First

• Local Reduction• Global Reduction • Active-Clock Reduction

• Re-Use State-Space

• Over-Approximation• Under-Approximation

• Diagnostic Trace

• Breadth-First• Depth-First

• Local Reduction• Global Reduction • Active-Clock Reduction

• Re-Use State-Space

• Over-Approximation• Under-Approximation

Page 67: UPPAAL Introduction Chien-Liang Chen. Outline Real-Time Verification and Validation Tools  Promela and SPIN Simulation Verification  Real-Time Extensions:

Forward Rechability

Passed

Waiting Final

Init

INITIAL Passed := Ø; Waiting := {(n0,Z0)}

REPEAT - pick (n,Z) in Waiting - if for some Z’ Z (n,Z’) in Passed then STOP - else /explore/ add

{ (m,U) : (n,Z) => (m,U) } to Waiting; Add (n,Z) to Passed

UNTIL Waiting = Ø or Final is in Waiting

n,Z’

m,U

n,Z

Init -> Final ?

location

zone

Page 68: UPPAAL Introduction Chien-Liang Chen. Outline Real-Time Verification and Validation Tools  Promela and SPIN Simulation Verification  Real-Time Extensions:

Order of ExplorationDepth-First vs Breadth-First

Passed

Waiting Final

Init

n,Z’

m,U

n,Z

Depth-FirstWaiting stored on

stack

Breadth-FirstWaiting stored in

queue

Depth-FirstWaiting stored on

stack

Breadth-FirstWaiting stored in

queue

In most cases BF is preferred becauseit allows for generation of “shortest”traces.

DF is useful in situations when reachability may be concluded without generating the full state-space.Easy computation of traces.

Page 69: UPPAAL Introduction Chien-Liang Chen. Outline Real-Time Verification and Validation Tools  Promela and SPIN Simulation Verification  Real-Time Extensions:

Philips Bounded Retransmission Protocol (BRP)

[D’Argenio et.al. 97]

Page 70: UPPAAL Introduction Chien-Liang Chen. Outline Real-Time Verification and Validation Tools  Promela and SPIN Simulation Verification  Real-Time Extensions:

Protocol Overview

Protocol developed by Philips. Transfer data between Audio/Video

components via infra-red communication. Data files are sent in smaller chunks. Problem: Unreliable communication medium. Solution:

Sender retransmits if receiver responds too late. Receiver aborts if sender sends too late.

Page 71: UPPAAL Introduction Chien-Liang Chen. Outline Real-Time Verification and Validation Tools  Promela and SPIN Simulation Verification  Real-Time Extensions:

Overview of BRP

Sender Receiver

S R

K

L

Input: file = p1, …, pn

lossy

lossy

Output: p1, …, pn

BRP

pi

ack

Page 72: UPPAAL Introduction Chien-Liang Chen. Outline Real-Time Verification and Validation Tools  Promela and SPIN Simulation Verification  Real-Time Extensions:

How It Works

Sender input: file = p1, …, pn.

S sends (p1,FST,0), (p2,INC,1), …, (pn-1,INC,1), (pn,OK,0).

R sends: ack, …, ack. S retransmits pi if timeout. Receiver recives: p1, …, pn. Sender and Receiver receive NOK or OK.

whole file OK

more parts

will followfirst part of file

Page 73: UPPAAL Introduction Chien-Liang Chen. Outline Real-Time Verification and Validation Tools  Promela and SPIN Simulation Verification  Real-Time Extensions:

BRP Model Overview

Sender Receiver

S R

K

L

Input: file = p1, …, pn

ack

(pi,INDicator,abit)

lossy

lossy

OK, NOK, DK IND, OK, NOK

Output: p1, …, pn

BRP

Page 74: UPPAAL Introduction Chien-Liang Chen. Outline Real-Time Verification and Validation Tools  Promela and SPIN Simulation Verification  Real-Time Extensions:

The Lossy Media

value-passing

lossy = may drop

messages

one-place

capacity

delay

Page 75: UPPAAL Introduction Chien-Liang Chen. Outline Real-Time Verification and Validation Tools  Promela and SPIN Simulation Verification  Real-Time Extensions:

Bounded Retransmission

BRP Sender S sends a chunk pi and waits for ack from BRP Receiver R.

If timeout occurs, the chunk is retransmitted. If too many timeouts occur, the transmission

fails (NOK is sent to the Sender).

If the whole file is successfully transmitted, then OK is sent to the Sender.

BRP Receiver is similar.

Page 76: UPPAAL Introduction Chien-Liang Chen. Outline Real-Time Verification and Validation Tools  Promela and SPIN Simulation Verification  Real-Time Extensions:

Process S – BRP Sender

Page 77: UPPAAL Introduction Chien-Liang Chen. Outline Real-Time Verification and Validation Tools  Promela and SPIN Simulation Verification  Real-Time Extensions:

Process R – BRP Receiver

Page 78: UPPAAL Introduction Chien-Liang Chen. Outline Real-Time Verification and Validation Tools  Promela and SPIN Simulation Verification  Real-Time Extensions:

Sender and Receiver - Applications