Updated Algorithmic Modeling Proposal for SERDES Tx and Rx

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Updated Algorithmic Modeling Proposal for SERDES Tx and Rx

Cadence, SiSoft

DesignCon IBIS Summit

Feb 1, 2007

Updated IBIS SerDes Modeling Proposal – DesignCon IBIS Summit - Feb 1, 20072

Contributors

• C. Kumar, Cadence• Hemant Shah, Cadence• Barry Katz, SiSoft• Walter Katz, SiSoft• Mike Steinberger, SiSoft• Todd Westerhoff, SiSoft


Modeling trends

IBIS

‘98 ‘04 ‘05

Transistor Models

Algorithmic

• IBIS enjoyed 5 years as THE digital IO model format• Higher frequencies brought new issues and more skeptics• Gigabit serial links brought rapid transistor model increase in 2004• Increasing Matlab use for algorithmic modeling

– Lacks “interoperability”


Who Needs These Models?

• System Designers– Predict end-end link BER and evaluate system-level design

tradeoffs

• ASIC designers– Evaluate different TX/RX architectures and behavior in

hypothetical system environments

• SerDes circuit designers– Validate with standard test beds

• Measurement Equipment Vendors– Model device-specific equalization & clock recovery


High Speed Modeling – Then and Now

• IBIS 1.0 – 1993– Common clock design, ~25 MHz– Nonlinear drivers, uncontrolled impedances, reflections, ringing,

irregular routing– Needed way to efficiently encapsulate push-pull output driver

behavior

• IBIS-ATM – 2007– Serial link design, 3+ Gbps– Highly linear drivers, controlled transmission paths– Linear Time Invariant (LTI) network theory applies– Need way to model transmitter / receiver equalization, clock

recovery behavior, predict BER


SerDes Proposal Discussion History

• June 2006 – Initial Cadence proposal for SerDes device modeling• Sep 2006 – Arpad’s peak distortion analysis with VHDL-AMS• Oct 2006 – Cadence proposal in IBIS BIRD format

– Based on request from the IBIS-ATM team

• Dec 2006 - SiSoft proposes LTI modeling terminology

• Today we share improvements to the original Cadence proposal – This team believes all major issues for the proposal in June / July by

Cadence, IBM are addressed

– Provides for future extensibility

– Provides IBIS a unique opportunity take a leadership position in SerDes device modeling


Issues with Original Proposal

• Network representation– Issue: concerns over whether impulse response compromised

accuracy and pole/zero representation was required

– Recommendation: Any time-domain or frequency-domain representation can be converted into any other. It’s true the impulse response must be long enough to contain needed low-frequency components, but this is readily achievable


Issues with Original Proposal

• Model parameter representation– Issue: All parameters were IP vendor definable with no

commonality; EDA tools need models to expose parameters in a standard way to consume them

– Recommendation: addressed in this proposal

• Methodology dependency– Issue: concern that “getwave” was predicated on a certain

approach to time-domain convolution

– Recommendation: addressed in this proposal


Let’s Talk LTI …

• Analysis can be performed in either time or frequency domain

• Circuit behavior is “characterized” in terms of impulse response (time domain) or transfer function (frequency domain)

• This isn’t “circuit simulation” as much as “signal processing”

• Terminology and techniques may be new to digital designers, but methods are very well established (~40 years old)

4Serial Link Terminology – IBIS-ATM - J anuary 26, 2007

©2006, SiSoft. Reuse permitted with SiSoft logo present

LTI Theory

5Serial Link Terminology – IBIS-ATM - J anuary 26, 2007

©2006, SiSoft. Reuse permitted with SiSoft logo present

Network Parameters


HSpice/Linear Modeling Correlation Studies

http://www.vhdl.org/pub/ibis/summits/dec05/wang.pdf

http://www.vhdl.org/pub/ibis/summits/jun05/huq.pdf

http://www.vhdl.org/pub/ibis/summits/dec05/wang.pdf

http://www.vhdl.org/pub/ibis/summits/jun05/huq.pdf


LTI Terminology

• We’ll use definitions fromhttp://www.vhdl.org/pub/ibis/macromodel_wip/archive/20061212/toddwesterhoff/Serial%20Link%20Terminology/serial_link_terminology.pdf

http://www.vhdl.org/pub/ibis/macromodel_wip/archive/20061212/toddwesterhoff/Serial%20Link%20Terminology/serial_link_terminology.pdf

http://www.vhdl.org/pub/ibis/macromodel_wip/archive/20061212/toddwesterhoff/Serial%20Link%20Terminology/serial_link_terminology.pdf


The LTI Analysis Continuum

Channel Impulse Response hTX(t) h(t) hRX(t)

Channel Pulse Response (No EQ)p(t) hTX(t) h(t) hRX(t)

Channel Pulse Response (TX EQ) hTE(t) p(t) hTX(t) h(t) hRX(t)

Channel Pulse Response (TX, RX EQ)hRE(t) hTE(t) p(t) hTX(t) h(t) hRX(t)

Equalized RX Datab(t) hRE(t) hTE(t) p(t) hTX(t) h(t) hRX(t)

Billions of bits in a reasonable time

Circuit Simulation

Signal Processing

Limited

No









Circuit Simulation

Signal Processing

No









Circuit Simulation

Signal Processing


Defining a Standard

• Serial channel analysis involves a combination of circuit simulation and signal processing techniques

• There are many ways to combine the two sets of analyses

• A meaningful standard must define explicitly what data the models consume and produce– It’s useful to show how the models can be employed in the

context of a specific analysis process– The example process doesn’t mean this is the only way the

models can be used


Two Main Analysis Schemes

• Impulse Response Processing (“Init”)1. Channel impulse response is obtained from circuit analysis

2. Transmitter equalization is applied

3. Receiver equalization is applied

4. Recovered clock behavior is predicted

• Waveform Processing (“GetWave” – bit by bit sim)1. Time-Domain waveform can come from any simulation

method

2. Transmit equalization is applied

3. Receive equalization is applied

4. Recovered clock behavior is predicted


Obtaining The Equalized Impulse Response

• Channel impulse is passed to transmitter model, model returns impulse after transmit equalization

• Resulting impulse is passed to receiver model, model returns impulse after receive equalization, along with recovered clock distribution

TransmitterAlgorithmic

Model

ReceiverAlgorithmic

ModelChannel Impulse Response

With TX EQ With TX, RX EQ

Clock Distribution

ControlSettings

ControlSettings


Transmitter Algorithmic Model

Impulse ResponseV(t)

Standard Device Settings

OptimizedDevice Settings

(Optional)

Updated (Filtered)Impulse Response

V(t)

Model-Specific Device Settings

(Optional)


Receiver Algorithmic Model - Init

Impulse ResponseV(t)



(Optional)

Updated (Filtered)Impulse Response

V(t)


(Optional)

Recovered ClockDistribution


Equalized Impulse Response Processing

hTX(t) h(t) hRX(t) hTE(t) hRE(t)

TransmitterElectrical

Characteristics

ReceiverElectrical

Characteristics

TransmitEqualization

ReceiveEqualization

EqualizedImpulse Response

ChannelCharacteristics

ChannelImpulse Response

Circuit Simulation Signal Processing


Receiver Algorithmic Model - GetWave

Waveform streamV(t)



(Optional)

Updated (Filtered)Waveform Stream

V(t)


(Optional)

Recovered ClockDistribution


Algorithmic Models

• Need defined standard for input and output time-domain waveform formats

• Need standard defined parameters, indicating which parameters are required (if any)

• Need a standard mechanism for defining additional model-specific parameters

• Can be implemented in any language or scheme that allows them to accept input and produce output as defined (black box)


IBIS Support for Algorithmic Modeling

S

ClockRecovery

Equalizer Sampler

[Component] MY_COMP

…

[Model] ModelName

Model_Type SerDes_TX– Existing IBIS buffer syntax

– [Algorithmic Model]…

– [End Algorithmic Model]

CircuitSimulation

SignalProcessing


IBIS Algorithmic Modeling Extensions

• Delimited with– [Algorithmic Model] … [End Algorithmic Model]

• Reserved keywords for standard model parameters– Defined as part of IBIS standard, enables EDA “built-in” models

• IP vendors can add keywords– [User-Defined Parameters]

• Protects IP by using “black box” model to hide details of filtering and clock recovery/optimization algorithms


Defining Algorithmic Parameter Types & Syntax

<keyword name> <usage> <data type> <data format> <values>

<usage>In Parameter is required Input to executableOut Parameter is Output only from executableIO Optional Input to executableIf input then its value will be usedIf output then its value will be determined by executable and will be in the output file(Note: Input parameters may be echoed into the executable output file)

<data type> (default is float)floatintegerstring

<data format> (default to range)range <typ value> <min value> <max value>list <typ value> <value> <value> <value> ... <value>corner <typ value> <slow value> <fast value>table #columnsGaussian <mean> <sigma>Dual-Dirac <mean> <mean> <sigma> | Composite of two GaussianDjRj <minDj> <maxDj> <sigma> | Convolve Gaussian (sigma) with uniform Modulation PDF


Sample IBIS Model

[IBIS Ver] 4.2[File name] serdes_device.ibs[Date] 01/27/2007[File Rev] 1.0 [Source] From HSpice and Matlab analysis|[Notes] Rev 1.0: 01/27/2007 - Initial model|[Component] MY_SERDES[Manufacturer] SERDESCORP[Package]|variable typ min maxR_pkg 100m 50m 150mL_pkg 2.0nH 1.5nH 2.5nH C_pkg 0.8pF 0.6pF 1.0pF||[Pin] signal_name model_name R_pin L_pin C_pin|A1 TX_ MY_TXA2 TX+ MY_TXB1 RX_ MY_RXB2 RX+ MY_RX

|****************DIFF PIN******************[Diff_pin] inv_pin vdiff tdelay_typ tdelay_min

tdelay_max|A1 A2 NA 0ns NA NAB1 B2 .1V 0ps NA NA


Sample IBIS Model - SerDes_TX

[Algorithmic Model]|| Executable (optional)Executable Solaris SerDesTx61.solaris Executable Linux SerDesTx61.linuxExecutable Windows SerDesTx61.windows|| TX Jitter Rj, Dj | Default to NoneJitter DjRj 0 3ps 2ps|| ModulationModulation NRZ | Default to NRZ|| Tap DataTaps 4 | Default to 4Primary_Tap 2 | Default to 2Tap_Gain_Min -1. -1. -1. -.25 | Default to -1. -1. -1. -1.Tap_Gain_Max 1. 1. 1. .25 | Default to 1. 1. 1. 1.Tap_Gain_Steps 32 32 32 8 | Default to infinite granularityMax_Tap_Sum 1. | Default 1.|| Tap Spacing | Default SynchTap_Spacing Synch | Synch ' Bit_Time| Tap_Spacing 160p | Uniform spacing, but not bit_time| Tap_Spacing 160p 130p 120p | Non uniform spacing|[User Defined Parameters] | For executable onlySecretsauce in integer range 5 1 9[End User Defined Parameters][End Algorithmic Model]| End Model MY_TX

| *********************************| SERDES TRANSMITTER MODEL| *********************************[Model] MY_TXModel_type SerDes_TX|Vmeas = 0.500VVref = 0.500VCref = 0.000FRref = 50.000Ohm| typ min max|C_comp 1.00pF 0.80pF 1.20pF|[Voltage Range] 1.00V 0.95V 1.05V[Temperature Range] 60.0 100.0 0.0||***************************************************************************|[Pulldown]| Voltage I(typ) I(min) I(max)...[Pullup]| Voltage I(typ) I(min) I(max)...|***************************************************************************[Ramp]R_load = 50.00Ohm| typ min maxdV/dt_r 781.447mV/372.457ps 737.729mV/382.334ps 823.953mV/385.013psdV/dt_f 784.341mV/360.004ps 741.357mV/350.697ps 829.867mV/356.268ps|[Falling Waveform]V_fixture = 1.000VV_fixture_min = 0.95VV_fixture_max = 1.05VR_fixture = 50.00Ohm|| Time V(typ) V(min) V(max)|...


Sample IBIS Model - SerDes_RX

[Algorithmic Model]|| Rx Optimize/Filter/ClockPDF Executable| Executable Models (Required)Executable Solaris SerDesRx61.solaris Executable Linux SerDesRx61.linuxExecutable Windows SerDesRx61.windows|| Reserved Parameter Names, Allowed ValuesNumber_Aggressors integer range 0 0 8 | Default to 0 0 8Modulation NRZ | Default to NRXEncoding string list scrambled 8b10b 64b66b | Default to scrambledFrequency_Offset 200u 0 600u | Default to 200u (200ppmDifferential_Offset 10mV | Default to 10mV Decision Point ThresholdQuality | Output by model if present (Bigger is Better)Taps 4 | Default to 4Tap_Usage IOPrimary_Tap 2 | Default to 2Tap_Gain_Min -1. -1. -1. -.25 | Default to -1 -1 -1 -1Tap_Gain_Max 1. 1. 1. .25 | Default to 1 1 1 1Tap_Steps 64 64 64 16 | Default to infinite granularityMax_Tap_Sum 1. | Default to 1.Tap_Spacing Synch | Default to Synch=Bit_Time|clock_PDF table 2 | Optional If not returned by exe and if not | specified EDA tool will assume some default PDF-40ps 0-30ps 1e-8…40ps 1e-850ps 0end_table|[User Defined Parameters]Secretsauce IO integer range 5 1 9BER | Output by model if present[End User Defined Parameters][End Algorithmic Model]| End Model MY_RX

[END]

| *********************************| SERDES RECEIVER MODEL| *********************************|[Model] MY_RXModel_type SerDes_RXC_comp 1.00p 0.95p 1.05p|Vinl = 0.4Vinh = 0.6|[Temperature Range] 60 100 0[Voltage Range] 1.0 0.95 1.05

[GND Clamp]...

[Power Clamp]...


Executing the Transmit Model

Output FileTap_Gain –2 26 -2 1Strength .875Frammistat 8[Begin Impulse Response]...[End Impulse Response]

SerDesTx61.solaris <Input file> <Output File>

Input FileBit_Time 160psTime_Step 10psStrength 1.Frammistat 7Tap_Gain –3 24 -3 1[Begin Impulse Response]...[End Impulse Response]


Executing the Receiver Model

SerDesRx61.solaris <Input file> <Output File>

Input FileBit_Time 160psTime_Step 10psEncoding 64b66bFrequency_Offset 200uNumber_Aggressors 0Frammistat 7[Begin Impulse Response]0..01.11.1.01-.01.01[End Impulse Response]

Output FileFrammistat 9[Begin Impulse Response]0..01-.01.01[End Impulse Response][Begin Clock PDF]…[End Clock PDF]


Executing the Receiver Model (“GetWave”)

SerDesRx61.dll

InputTD Waveform, Waveform Size

OutputModified waveform

Clock tics

• AMI interface simplified based on feedback• Sample interval dropped, since it is set in the init call


Executable Model Options

Tx Init .exe

.dll

Rx Init .exe

.dll

.dllGetWave


Summary

• Serial link analysis involves two different types of simulation– Circuit simulation – for derivation of impulse response

– LTI analysis – transmit/receive equalization and clock recovery

• Existing IBIS models largely address circuit simulation needs• Equalization and clock recovery algorithms can be effectively

modeled with IP vendor-supplied routines• Model calling sequence can be clearly defined and is user-extensible• This amended proposal addresses major issues discussed in IBIS-

ATM meetings for the past 6 months– Leverages existing IBIS model parameters and circuit simulation

infrastructure

– Provides IP vendors ability to do as much as they wish in the (black box) model


Next Steps

• Update BIRD– With documentation

• Present to ATM (Target: Mid-February)– Detailed technical review

• Present to IBIS Open Forum

Updated Algorithmic Modeling Proposal for SERDES Tx and Rx

Documents

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