UNNATI SHAH

201 S fourth St Apt. 435 San Jose, CA, 95112| unnati.shah@sjsu.edu | (669)262-7271 | https://www.linkedin.com/in/shahunnati

OBJECTIVE

Seeking internship opportunities in the field of ASIC/SoC/FPGA/Digital Design and Verification.

SUMMARY

Graduate student in Electrical Engineering with 4 years of professional experience as a Lead Engineer. Further experience in,

● RTL design - Simulation and DC Synthesis, STA ● SoC Design and Verification ● DFT insertion using SCAN and BIST ● Digital Design Programming, Simulation and Debugging

EDUCATION

Master of Science – Electrical Engineering - San Jose State University, San Jose, CA Aug 2015 – May 2017

Bachelor of Engineering – Electronics - Maharaja Sayajirao University of Baroda, Gujarat July 2007 - April 2011

TECHNICAL PROFICIENCY

Digital VLSI System Design and Debugging, DC Synthesis, Static Timing Analysis, DFT- SCAN Chain, BIST

Low Power Analysis, Place and Route, Fault Analysis using D-Algorithm, FPGA Design

Computer Architecture – MIPS Processor, Cache Organization

Modbus, IEC101, IEC104 Communication, AMBA AHB, APB, AXI, I2C, SPI, PCIe, PC/AT buses

SOFTWARE PROFICIENCY

Languages: Verilog HDL, SystemVerilog, C

EDA Tools: Cadence Virtuoso, Synopsys VCS, GTK Wave, Multisim

Scripting Language : PERL, Python

Platform: LINUX, UNIX, Virtual machine, Windows

Software Tools : Visual Studio, MATLAB, Multisim, Cadence PSpice, Microsoft Office Suite

COURSEWORK

SoC Design and Verification with System Verilog, CMOS ASIC Design, Advance Computer Architecture, Advanced Digital

System Design & Synthesis, Digital System designing, Designing Digital Circuits using FPGA, Digital communication,

Principle of Semiconductor devices

PROJECTS

LCD Controller LPC2478 RTL Design using SystemVerilog on AMBA AHB Bus: April-2016

- Dual LCD controller design in SystemVerilog where Data are being selected and driven through FIFO, Pixel serializer,

RAM palette and provided as output. Design is Synthesized on Perl based Test bench in Synopsys VCS tool.

- Timing Analysis is done on Design Vision tools.

- Communication is established on AMBA Bus - AHB master and Slave modules for writing data into the Memory and

reading data from Memory.

Arbiter Designing for AMBA - AHB Bus on SystemVerilog: April-2016

- An Arbiter Design with 4 masters is implemented for AHB bus. Masters should have bandwidth of 30,20,10,10

respectively in the scale of 100. Round Robin with priority arbitration is implemented.

- This design is implemented, simulated and synthesized on SystemVerilog.

- Timing Analysis is done on Design Vision tools.

Design and Implemented Floating point Random number Distribution in Verilog HDL : March 2016

- Two uniformly distributed random numbers ranging between 0 and 1 are converted to floating point. Calculation is

performed with an interpolated lookup table.

- Normalization and Demoralization of double precision floating point number is done in Verilog. Floating point adder and

Multiplier modules are used in pipeline for speeding up the process.

- Design is made synthesizable on Design Vision at 220 MHz.

Designed 5-stage pipeline Altera NIOS II 32-bit MIPS Processor using Verilog March-2016

- Implemented the data path of NIOS II processor to perform the dot product of input vectors and factorial operation.

- Designed MIPS architecture in Verilog which avoids data hazards, structural hazards and control hazards by having

a hazard detection unit in the MIPS architecture. Used VCS for simulation

PROFESSIONAL EXPERIENCE

GE Power (Previously known as - Alstom India Ltd.) July 2011- July 2015

Job Description: Lead Engineer, Control Systems

Integration of 3rd party system architecture and communication with 3rd party software using Gateway

DCS System architecture design and Integration, Logical Programming, Simulation and Testing

RTDS system development and data acquisition using OPC server, Virtual machine development

REFERENCES

Available upon request