University of Toronto (TH2B - 01) 65-GHz Doppler Sensor with On-Chip Antenna in 0.18µm SiGe BiCMOS...

University of Toronto

(TH2B - 01)

65-GHz Doppler Sensor with On-Chip Antenna in 0.18µm SiGe BiCMOS

Terry Yao, Lamia Tchoketch-Kebir, Olga Yuryevich,

Michael Gordon and Sorin P. Voinigescu

65-GHz Doppler Sensor with On-Chip Antenna in 0.18um SiGe BiCMOS 2

Outline

• Motivation• System Overview and Design• Experimental Results• Conclusions• Acknowledgments


Motivation

• mm-wave integration in silicon accelerated by:Significantly smaller form factors of on-chip

passives (inductors, transformers, antennae)Advances in SiGe BiCMOS

• Target applications:mm-wave sensors

for medical and security applications

Short range automotive radar

Side Crash

Side Crash

Parking AidLane ChangeRear Crash(0.2-5m)

Parking Aid (0.2-5m)Stop-and-Go Traffic Radar (20m)Forward-Looking Radar(150m)

Blindsp

ot

BlindspotInte

rsec

tion

Intersection


State-of-the-Art in mm-Wave Integration

• SiGe favoured over CMOS due to higher breakdown voltage higher PA power, lower phase noise VCOs

• Critical challenge tuning BW, phase noise and output power of VCO

• No Tx/Rx IC with antenna and fundamental VCO

SystemAntenna on chip?

Integrated Fund. VCO?

Freq. (GHz)

Process (fT/fMAX) Reference

Tx

Y N 77 SiGe (200/250GHz) A. Natarajan (ISSCC, 2006)

Y N 60 SiGe (120/130GHz) C.H. Wang (ISSCC, 2006)

N N 60 SiGe (200/250GHz) B. Floyd (ISSCC, 2006)

Rx

Y N 77 SiGe (200/250GHz) A. Babakhani (ISSCC, 2006)

N Y 65 SiGe (150/160GHz) M. Gordon (SiRF, 2006)

N N 60 SiGe (200/250GHz) B. Floyd (ISSCC, 2006)

N N 60 0.13µm CMOS B. Razavi (ISSCC, 2005)


Integrated Fundamental Frequency VCO• Challenges:

Accurate fosc modeling of passives and parasitics Low phase noise high-Q tank, large BVCEO, large Vosc

High POUT large BVCEO, IBIAS, accurate matching Wide tuning range high capacitance-ratio varactors

• Benefits: Less EMI, no filtering required Area and power savings (multiplier structure, off-chip

transition eliminated, etc.) Higher integration level = lower overall cost

Note: Static frequency dividers equally important as VCO; so far only SiGe ones demonstrated >60GHz with low power

(T. Dickson, SiRF ’06; E. Laskin, BCTM ’06)


Outline



System Highlights and Overview

• Extensive use of small footprint inductors as matching elements area savings

• HBT cascodes for higher gain, isolation

IF Amp

Output Buffer

IF

IF

Out

Out

On-Chip Patch Antenna

61-67GHz LO

LNA

Gilbert Mixer

Vdd Rx

Tx


System Design – Receive Path

2-stage single-ended

cascode LNA with vertically

stacked transformer output

Down-convert mixer noise- and

power-matched to 200Ω differential

Zout of LNA

RF+

RF-

IF+

IF-

EF

3.3V

Downconvert Mixer

3.3V

Vb6

IF Out+

IF Amplifier

IF Out-

Vb1

3.3V

RF In

Vb2

Vb3 Vb4

Patch Antenna

EF

LO+LO-

EF

LNA

Microstrip Feedline

Vb5

61-67GHz LO

To Tx

Bipolar IF amplifier

for reduced 1/f noise


System Design – Transmit Path

Differential Colpitts 61-

67GHz VCO (shared with

receive path)

2-Stage

emitter

follower

buffers

65GHz output buffer

driving 50Ω loads per

side

LO+MIXER

4V

Vtune

C1

C2 C2

LB

LE

LEE L

EE

LE

C1

Vdd

Vbb

4V

Out-LO+ LO-

EF

LO+

LO-

EF

To Rx Mixer

Output Buffer

Out+

On-Chip VCO

LB

LO-MIXER

LO+TX

LO-TX

Vb7


Building Blocks: Mixer

• Key design goals:

59-65GHz operation

Low noise at low IF

High conversion gain

• HBT for reduced 1/f noise

• Simultaneously noise- and power-matched to 200Ω differential LNA output

• Simulated: G ~ 9.2dB; IIP3 ~ 4.2dBm; NF ~ 13dB

• 13.2mW from 3.3V supplyinC

minffm ZR

gZj

gG

T

2

)(1

2

},min{ 3,3max, SATCECECco VVRIV

3,3 SATCECECC VVRI

3.3V

RF+

RF-

LO+

LO-

IF+

IF-

EF

Downconvert Mixer

RC

LE

LE

RC

LB

LB

Q1

Q2

Q3

Q4

Q5

Q6


mm-Wave Passives• Reduced form factor of on-chip passives at mm-waves

• Inductors preferred for area efficiency and low-loss

• ASITIC with >90% accuracy; 2-π model

Stacked transformer and power transfer measured up to 94GHz

65-GHz polyphase filter and measured phase response 1-65GHz

34 µm


Patch Antenna Design

• Patch Antenna Gain: -8.5dBi

• Patch has similar gain as dipole but better isolation on Si

M6 Slotted Patchr = 4.2

M1 Ground Plane

L = 1.14 mm

P+-substrateContacts to substrate

Ground Plane

h

r

1.7mm

Patch

L_Inset = 400µm

Feed

Loc

atio

n

Si Wafer1.

3mm


Outline



Fabrication Technology

• Jazz Semiconductor’s SBC18 SiGe BiCMOS process

• fT, fMAX >150 GHz

• 6-metal backend


Fabricated Structures1.7mm

LNA

VCO Output BufferIF

Amp

Mixer

1mm

1mm

1.7mm x 1.3mm Patch Antenna 1.

3mm

1mm

1mm

LNA

VCO

Mixer

IF Amp

Output Buffer

2.5mm x 2.5mm 1mm x 1mm


2-Stage Cascode LNA Measurements

RF+

RF-

Vb1

3.3V

RF In

Vb2

Vb3 Vb4

Patch Antenna

LNA

Microstrip Feedline

To Mixer

• Breakout measurements:

14dB S21 @ 65GHz

Input P1dB = -12.8dBm

• Simulated NF = 10.5dB

• 40mW from 3.3V supply

• Total Area: 370 x 480µm2


• on-wafer probing of sensor without on-chip antenna• measurement using horn antenna/suspended probe

and adjustable metal reflector

Experimental Results



• SE meas. with external RF input of -48dBm @ 64GHz

• SE down-conversion gain of 16.5dB

• SE transmit output spectrum• Diff. output power +4.3dBm

after de-embedding set-up loss


• 6 elevations of horn antenna over Rx patch antenna (~ 15mm - 100mm)

• Propagation loss contributes to loss in conversion gain


• 16.5dB w/o antenna• -24.5dB suspended probe

over antenna• -26dB horn antenna over

patch antenna



Gain in good agreement with spectral measurement

Measured IIP3 = -20dBm


Performance Summary

Rx conversion gain (on-wafer probed)

16.5dB (S)

Rx conversion gain (horn antenna) -26dB (S)

Rx conversion gain (suspended probe)

-24.5dB (S)

Rx IIP3 -20dBm

Rx P1dB, in -30dBm

Rx noise figure (min.) 12.5dB

Tx output power (@ 65GHz) 1.3dBm (4.3dBm D)

LO tuning range 61-67GHz

Power consumption 640mW

Area 1 x 1mm2 (no patch antenna)2.5 x 2.5mm2 (with patch

antenna)S: Single-ended D: Differential


Conclusions

• Single-chip 65-GHz Doppler sensor featuring:

61-67GHz integrated varactor-tuned fundamental frequency VCO

on-chip patch antenna

extensive use of lumped passives to minimize chip area

• Chip demonstrates:

high level of mm-wave integration achievable in today’s production silicon technology

feasibility of low-cost mm-wave systems for sensor and radio applications


Acknowledgments

• NSERC and Micronet for financial support

• Jazz Semiconductor for fabrication

• CMC for CAD tools

• K. Tang, K. Yau and S. Shahramian at U of T for simulation and measurement support


Thank You.

Questions…


Backup Slides


System Design Considerations

• System acts as speed and motion sensor according to the Doppler effect:

f

cfv d

2

1target

targetreturn2

1vtDist

• Range of detectable speeds dependent on Doppler freq. shift

Upper bound set by IF amplifier BW

Lower bound set by VCO phase noiseP

min

Log(IF)10kHz 10MHz

Sensitivity

Phase Noise -20dB/dec


Building Blocks: On-Chip VCO• Integrated 61-67GHz VCO

• Frequency scaled from earlier 60-GHz design by C. Lee (CSICS, ’04) with phase noise of -104dBc/Hz @ 1MHz carrier offset

• Differential Colpitts configuration with accumulation mode nMOS varactor (C2) and inductive emitter degeneration (LE) for wide tuning range, low phase noise

Bbe

m RCCCω

gR

212 )(

Vdd = 4V

Vtune

C1

C2 C2

LB

LE

LEE L

EE

LE

C1

Vdd

Vbb

LO+ LO-

LB

21

21

)(

)(,

2

1

CCC

CCCC

CLf

be

beEQ

EQtank

osc


System Design Considerations

Why Patch Antenna?• Low profile planar configuration ease of integration• Can be accurately designed and analyzed using transmission-line

model • Metal ground plane and substrate contacts help maximize isolation,

reduce coupling into substrate

Ground Plane

Patch


Simulated Antenna Gain Results


Lowest Horn Antenna Elevation

Highest Horn Antenna Elevation

Radar Measurement Setup

University of Toronto (TH2B - 01) 65-GHz Doppler Sensor with On-Chip Antenna in 0.18µm SiGe BiCMOS...

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