Metal Oxide Resistive Switching Memory

Shimeng Yu, Byoungil Lee, H.-S. Philip Wong

Center for Integrated Systems and Department of Electrical Engineering, Stanford University

13.1 Introduction

Information storage device is a key component of nanoelectronic

systems. Conventional memories such as SRAM, DRAM, and

FLASH are facing formidable device scaling challenges. Emerging

memory device concepts have been actively pursued both in industry

and academia in hopes of finding solutions for future information

storage needs [1-2]. The ideal characteristics for a memory device

include fast programming speed (~ns), long retention time (>10

years), low power consumption, good reliability, high integrated

density, and continued scalability. Several candidates have been pro-

posed to achieve the above goals, such as magnetoresistive random

access memory (MRAM) [3], ferroelectric random access memory

(FeRAM) [4]. In recent years, memory devices based on the electri-

cally switchable resistance phenomenon have been extensively stud-

ied. The basic principle of this kind of memory is to use a high resis-

2

tance state (HRS) or low resistance state (LRS) to store the informa-

tion data “0” or “1”, and the transition between the two states can be

triggered by electrical inputs. Roughly speaking, resistive switching

memories can be classified into three groups [5]: (i) phase-change

memory (PCM) based on chalcogenides [6-9], which relies on the

temperature induced change between the crystalline phase (corre-

sponding to LRS) and the amorphous phase (corresponding to HRS)

(ii) programmable-metallization-cell (PMC) memory based on solid

electrolytes or polymers [10-13], which relies on the formation (cor-

responding to LRS) or the rupture (corresponding to HRS) of a

metallic conducting bridge between two electrodes, and (iii) resis-

tance random access memory (RRAM) based on metal oxides.

Among these resistive switching memories, metal oxide memory is

promising for practical applications due to its compatibility with sili-

con CMOS fabrication technology. Here, we review the research

progress of metal oxide memory including the physical mechanism

of switching, state of the art device performances, as well as device

cell structure for integration into a memory array.

The negative differential resistances phenomenon in oxides was

firstly reported in the 1960s [14-15], then it was reviewed by G.

Dearnaley et al. [16] in 1970. Recent work on the resistive switching

metal oxide memory can be traced back to the discovery of hystere-

sis I-V characteristics in perovskite oxides [17-19] such as Pr0.7-

Ca0.3MnO3, SrTiO3, SrZrO3, etc. in the late 1990s and the early

2000s. Since 2004, the research activities have focused on binary

metal oxides [20-26] such as NiO, TiO2, ZrO2, ZnO, Cu2O, Al2O3,

3

HfO2, etc. because of the simplicity of the material and good com-

patibility with silicon CMOS fabrication process. Recently, the per-

formance of perovskite oxide memories and related physical mecha-

nism of resistive switching were reviewed by R. Waser et al. [27-28]

and A. Sawa [29]. Therefore, here we focus this review on binary

metal oxide memory.

13.1.1 Device Operation It is necessary to first introduce some basic concepts and termi-

nologies about metal oxide memory. The typical metal oxide mem-

ory cell is a simple metal-insulator-metal (MIM) structure, as shown

in Fig. 1 (a). The switching event from high resistance state (HRS)

to low resistance state (LRS) is referred to as the “set” process. Con-

versely, the switching event from LRS to HRS is referred to as the

“reset” process. In some cases, for the fresh samples in its initial re-

sistance state (IRS), a larger voltage is needed to trigger on the resis-

tive switching behaviors for the subsequent cycles. This is called the

“electroforming” or “forming” process. The switching modes of

metal oxide memory can be broadly classified into two switching

modes: unipolar and bipolar. Unipolar switching means the switch-

ing direction depends on the amplitude of the applied voltage but not

on the polarity, thus set/reset can occur at the same polarity, and usu-

ally it can symmetrically occur at both forward and reversed volt-

ages, as illustrated in Fig. 1(b). Bipolar switching means the switch-

ing direction depends on the polarity of the applied voltage, thus set

can only occur at one polarity and reset can only occur at the reverse

4

polarity, as illustrated in Fig. 1 (c). To avoid a hard dielectric break-

down in the set process, it is recommended to enforce a set compli-

ance current, which is usually provided by the semiconductor pa-

rameter analyzer, or more practically, by a memory cell selection (or

access) transistor/diode or a series resistor. To read the data from the

cell, a small voltage is applied that does not affect the state of the

memory cell. For non-volatile application, the cell should retain its

state at standby mode and free from disturb from reading/writing of

neighboring cells.

Fig. 1 (a) Schematic of metal-insulator-metal (MIM) structure for metal oxide

memory cell, and schematic of metal oxide memory’s I-V curves, showing two

modes of operation: (b) unipolar and (c) bipolar

13.1.2 Device Characteristics To further understand how the metal oxide memory works, the de-

vice characteristics of HfO2 based memory cell [30-31] from Indus-

trial Technology Research Institute (ITRI) are presented as an exam-

ple. Fig. 2 (a) shows the transmission electron microscopy (TEM)

image of the concave structure device of TiN/Ti/HfOx/TiN stack

with 30 nm cell size; here 5 nm HfOx layer is used for the main

switching layer, TiN is used for the electrode material, and a thin Ti

buffer layer is used for improving the switching stability. Fig. 2 (b)

shows the typical I-V curve of such memory cell. A 200 µA set com-

pliance current is enforced, and the device exhibits bipolar switch-

ing. Fig. 2 (c) shows the switching endurance testing result. The set/

reset programming condition is +1.5 V/-1.4 V pulse with 500 µs

5

width, and it is seen that after 106 switching cycles, the HRS/LRS re-

sistance ratio is still larger than 100, although there is some degrada-

tion. Fig. 2 (d) shows the data retention testing result, the measure-

ment is performed at 150 °C, and it is seen that 10 years lifetime is

expected using a simple linear extrapolation. Besides, fast switching

speed (~5 ns), and multi-bit storage potential is also demonstrated in

the HfO2 memory.

Besides HfO2, other binary metal oxides such as NiO, TiO2, ZrO2,

ZnO, Cu2O, Al2O3 have been extensively explored. Up to now,

dozens of binary metal oxides have been found to exhibits electric-

field-induced bistable resistance switching behavior. Most of the

metals are transition metals, and some are lanthanide series metals.

The materials for switching layer and electrode layer are summa-

rized in Table 13.1. Note that some nitrides, e.g. TiN are also used

for the electrode layer.

Fig. 2 (a) Transmission electron microscopy (TEM) image of the concave struc-

ture device of TiN/Ti/HfOx/TiN stack; (b) Typical I-V curve of the device with the

cell size of 30 nm; (c) Endurance testing by 500 µs pulse: successive 106 switching

cycles is achieved; (d) Retention testing at 150 °C: 10 years lifetime is expected.

Reprinted from Ref [30-31]

Table 13.1 Summary of the materials that has been used for binary metal oxide

memory. Yellow metals corresponding binary oxides are used for switching layer;

blue metals are used for electrode layer.

13.2 Possible Physical Mechanism for Resistive Switch-

6

ing in Metal Oxides The physical mechanism for resistive switching in metal oxide

memory is still under a heated debate. According to ITRS 2007 [32],

resistive switching mechanism can be roughly classified into three

groups: thermal effect, electronic effect, or ionic effect. Thermal ef-

fect refers to the thermal dissolution of conductive filaments trig-

gered by local Joule-heating and works like a traditional household

fuse albeit at the nanoscale [33-34]. It is also referred to as fuse/anti-

fuse switching type. The electronic effect mechanism conjectures

that injected charges are trapped by interface defects. These trapped

charges modify the Schottky barrier height between electrodes and

oxides and thereby changing the conductance through the MIM

structure [35-36]. Another case of electronic effect is Mott metal-in-

sulator-transition due to the strong electron-electron correlation in

some transition metal oxides [37-38]. Ionic effect refers to the mi-

gration of ions with related electrochemical reactions to form a con-

ducting bridge between electrodes [39-40]. It is also referred to as

reduction/oxidation type. Actually, this ionic effect is just the operat-

ing principle of programmable-metallization-cell memory in solid

electrolytes or polymers as mentioned before. Metal oxides can also

serve as fast ions conductors for some particular metal ions like Ag+

and Cu2+ [41-42]. Here we plan to focus on the intrinsic properties of

metal oxides, thus we would not include those metal oxides memory

with Ag or Cu electrodes in the following discussions.

So far, no single model mentioned above can explain all the ex-

7

perimental results obtained in various materials. It seems that the

thermal dissolution model can address parts of the unipolar switch-

ing characteristics, while the ionic migration model can explain most

of the bipolar switching characteristics. However, the distinction be-

tween the two switching behaviors is ambiguous. Here we discuss

several key issues such as the conducting mechanism, the nature of

electroforming/set/reset process, the effect of electrode materials on

switching modes, with the aim of seeking a rational mechanism for

both unipolar and bipolar switching characteristics.

13.2.1 Conduction Mechanism

A lot of conductive atomic force microscopy (C-AFM) measure-

ments [43-47] have been reported in the literature, revealing that

conductive filaments (CFs) with nanoscale diameters are formed in

the oxide layer during the set process, and large conducting current

passes through these filaments in LRS. Fig. 3 shows one of these C-

AFM measurements results [45]. Typically, CFs are sparsely and

non-homogeneously distributed under the electrodes. This means

that the conducting area in LRS is an extremely small portion of the

entire electrode area, which is typically quite large in most experi-

ments. Therefore, the conductance in LRS would not decrease as

much as the conductance in HRS does when the electrode area is de-

creased, resulting a larger HRS/LRS resistance ratio, which is a ben-

efit of scaling down memory cell size. It has been experimentally

demonstrated that these CFs can be formed by C-AFM tip individu-

ally [48], but in most cases multiple CFs exist in the oxide layer,

8

which is believed to be responsible for the multi-level switching be-

haviors exhibited in some metal oxide memory devices [49-50]. Al-

though the filamentary conduction mechanism is widely recognized,

some researchers argued that a bulk conduction mechanism domi-

nates the LRS resistance in their TiO2 devices [51]. They proposed

that charged dopants (mainly oxygen vacancies) migrate under a

voltage bias to the TiO2/electrode interface. The interfacial changes

modify the Schottky barrier height at the interface and lead to the re-

sistive switching in their devices. In essence, such arguments do not

contradict with the filamentary conduction mechanism, provided

that the so-called bulk conduction is regarded as many parallel CFs.

It should be noted that if CFs are dense enough in ultra-scaled de-

vices, the bulk conduction behavior may arise. A usual experiment

that aims at distinguishing filamentary or bulk conduction is to mea-

sure the trend of the HRS/LRS resistance ratio versus the cell area. If

the ratio goes up when the cell area is scaled down, filamentary con-

duction prevails. If the ratio remains almost constant when the cell is

scaled down, bulk conduction prevails. However, so far, these exper-

iments have not been performed for devices with truly nanometer

scale size (< 100 nm) memory cells and therefore the results are not

yet conclusive.

Fig. 3 Conductive atomic force microscopy (C-AFM) of LRS (a) and HRS (b) con-

ductance in Al2O3 memory, showing filamentary conduction dominates in LRS.

(scanned area: 2 µm×2 µm; maximum y scale: (a) 105 nA, (b) 5 nA). Reprinted

from [45]

9

The CFs are conjectured to be made up of oxygen vacancies (Vo)

in most metal oxide memory devices, and this assumption was con-

firmed by micro X-ray fluorescence (XRF) and X-ray absorption

near-edge spectroscopy (XANES) [52]. It is well known that Vo can

act as an effective donor in n-type metal oxides. Ab-initio calcula-

tion of the rutile TiO2 electronic structure [53] reveals that Vo can

produce a defect state within the band gap. This state is occupied by

two electrons that are localized on Ti 3d orbital of the nearest Ti

atoms to Vo. If a chain of such Vo forms, it is expected that electrons

delocalization occurs and the hopping probability can increase re-

markably along these CFs and ultimately lead to the LRS. Although

Vo plays an important role in the switching behaviors of most metal

oxide memory devices, the composition of CFs is not limited to Vo.

There are quite a few reports that the CFs in NiO memory are com-

posed of excess metallic Ni in NiO. This suggestion is confirmed by

measurement of the dependence of the LRS resistance on tempera-

ture [54] and XPS composition analysis [55]. It was further verified

by electron energy loss spectroscopy (EELS) that there exists a Ni-

rich phase at the grain boundaries, which implies that the CFs of Ni

are formed as precipitates at the grain boundaries [56]. A simple way

to distinguish whether the CFs are metallic or semiconducting is to

measure the LRS resistance temperature dependency. If the LRS re-

sistance goes up with the increase of temperature, the CFs are metal-

lic and may consist of metal precipitates. On the contrary, if the LRS

resistance drops with the increase of temperature, CFs are semicon-

ducting and may consist of Vo.

10

There are many efforts to fit the I-V characteristics of HRS and

LRS to current conduction models in the literature. Most of the re-

ports show an Ohmic relationship in the LRS. And in the semicon-

ducting CFs, Mott variable hopping conduction [57] is proposed to

dominate in LRS, and this assumption was supported by some tem-

perature varying measurements [58-59] and AC conductance mea-

surement [60]. But, the conduction fitting results in HRS are quite

diverse, Poole-Frenkel emission (I~V*exp(V1/2)) [61-62], Schottky

emission (I~exp(V1/2)) [63-64], the space charge limited current

(SCLC) characteristic (the Ohmic region I~V, followed by the

child’s square law region I~V2) [65-66], were observed in various

metal oxide memories. The diverse I-V characteristics in HRS in-

volving different leakage mechanism may be associated with the dif-

ferent dielectric properties or different fabrication processes condi-

tions, e.g. annealing temperature, annealing ambient, and the proper-

ties of the interface between the oxides and the electrodes. Neverthe-

less, the key issue of metal oxides memory modeling is not the leak-

age current mechanism in HRS, but to investigate the mechanism

that triggers the resistive switching. So in the next section, we will

discuss the forming/set and reset process, respectively.

13.2.2 Electroforming/Set/Reset Process with Oxygen Migration

Dielectric breakdown is a process of local materials transitioning

from insulating to conductive under a high external electric field.

This phenomenon is well-known for gate dielectrics in MOSFETs

and has been studied for a long time. Recently, by site-specific struc-

11

tural analysis using high resolution transmission electron mi-

croscopy (HR-TEM) with EELS, X. Li et al. [67] revealed that after

dielectric breakdown, oxygen atoms in gate dielectric SiO2 were

missing. Substoichiometric silicon oxide SiOx (with x<2) was

formed, and the local energy gap was lowered with intermediate

bonding state of silicon atoms Si1+, Si2+, and Si3+ in the percolation

leakage path. Also, chemical bond breakage and the local Joule heat-

ing due to large current flowing through the percolation path are be-

lieved to be the main driving forces leading to the oxygen dissocia-

tion.

Similarly, in metal oxides, the electroforming/set process is inter-

preted to be some kind of soft dielectric breakdown [60, 68-69]. J. J.

Yang et al. [70] claimed that they observed oxygen gas bubbles at

the electrode surface of their bipolar TiO2 memory devices in the

electroforming process. They regarded the electroforming process in

metal oxide memory as an electro-reduction and Vo creation process

caused by high electric field, which is then enhanced by local Joule

heating. During electroforming, Vo are created and drift towards the

cathode, forming localized CFs in the oxide. Simultaneously, oxygen

ions drift towards the anode where they discharge to evolve oxygen

gas. M.-J. Lee et al. [71] investigated the composition change in

their unipolar NiO memory devices during the set process by sec-

ondary ion mass spectroscopy (SIMS), as shown in Fig. 4. The au-

thors suggested that the oxygen atoms within the NiO layer migrated

toward the Pt electrode after the switching, thus leaving the Ni rich

filaments in the NiO layer.

12

Fig. 4 (a) X-ray photoelectron spectroscopy (XPS) analysis of NiO memory; the

sample deposited at an oxygen partial pressure of 5% shows the coexistence of Ni

(852.8 keV) and NiO (854.3 keV) peaks, which exhibited bistable resistive switch-

ing; the sample deposited at an oxygen partial pressure of 30% did not exhibit any

stable resistive switching phenomenon, suggesting CFs may consist of metallic Ni

precipitates. (b) Secondary-ion mass spectroscopy (SIMS) data in NiO memory,

showing the migration of oxygen atoms towards the electrodes after electrical

switching. Reprinted from [71]

Therefore, in both unipolar and bipolar switching metal oxide

memory devices, the electroforming/set process is conjectured to be

associated with the generation of Vo and the migration of the oxygen

atoms, generating CFs consist of either Vo or metal precipitates. In

fresh samples, usually the amount of Vo is small, thus a high voltage

is needed to trigger the electroforming process. After electroforming,

the devices have switched to LRS, and a sufficient amount of Vo is

present. In subsequent switching cycles, only a portion of the Vo, the

ones near the anode, can be recombined during the reset process.

This is why the set voltage would be smaller than forming voltage

and the resistance in HRS would be much smaller than the resistance

in IRS. Through fitting of electrical parameters, the formation and

rupture of the CFs is estimated to occur in a localized region (3–10

nm) thick near the anode [72]. The remaining Vo rich region is re-

ferred to as the “virtual cathode” [28].

Obviously, it is not desirable to have a large electroforming voltage

in practical applications. Thus significant efforts have been made to

achieve the so-called “forming-free” devices. The forming voltage is

13

linearly dependent on the thickness of the oxide film [30, 73-75]. So

a thinner oxide film is effective in reducing the forming voltage. H.

Y. Lee et al. [30] claimed that the as-fabricated atomic layer deposi-

tion (ALD) HfO2 device is free from the electroforming process as

the thickness of the film is thinned to be 3 nm. Besides, controlling

the annealing ambient during deposition to obtain oxygen deficient

films is also helpful in reducing the forming voltage [76-78].

So far, we have stated that the nature of dielectric breakdown is

the formation of oxygen deficient percolation leakage paths. Note

that gate dielectric breakdown is a permanent and irreversible

process, while the switching process in metal oxide memory is a re-

versible process. So the memory device should have a location to

store the missing oxygen atoms during the set process and then drive

them back during the reset process. The concept of an “oxygen

reservoir” is thus envisioned. Usually, the anode electrode materials

act as the oxygen reservoir, and it also prevents the oxygen from es-

caping from the device to the ambient. The anode electrode material

then provides a source of oxygen for reset process. Fig. 5 illustrates

how the oxygen reservoir works in a Ti/MnO2/Pt memory device

[79]. X-ray photoelectron spectroscopy (XPS) reveals that amount of

non-lattice oxygen became less in LRS than in HRS, and the corre-

sponding shift of Ti 2p peak indicates that an interfacial TiOx layer

was formed. This observation suggests that during the set process,

oxygen ions moved toward the Ti anode when a positive bias was

applied, where they reduced the Ti and formed TiOx. This interfacial

TiOx layer is believed to act as an oxygen reservoir that stores oxy-

14

gen atoms. When a negative bias was applied to the Ti anode, oxy-

gen ions moved away from the interfacial layer toward the oxide

bulk layer and recombine with Vo. Therefore, the bipolar switching

characteristics are assumed to be the formation and rupture of the

CFs consisting of Vo associated with oxygen ion migration.

Fig. 5 XPS spectra of Ti/MnO2 interface. (a) The O 1s core levels spectra of the

lattice peak (529.45 eV) and an additional non-lattice peak (531.33 eV), the

change of non-lattice oxygen indicates oxygen ions migration during switching;

(b) The spectra of Ti 2p, the shift of Ti 2p peak indicates an formation of interfa-

cial TiOx layer, which can be regarded as an oxygen reservoir. Reprinted from

[79].

In the bipolar switching case, it is straightforward to conceive of

oxygen ions migrating away from the interface, since oxygen ions

are negative charged. Under a negative bias, oxygen ions can be

pushed toward the oxide bulk layer and then recombine with Vo and

rupture the CFs if the CFs are made up of Vo. C. Yoshida et al. [80]

performed C-AFM writing experiments in 18O tracer gas atmos-

phere and related composition analysis by SIMS on the NiO films.

Their results suggest that external oxygen can penetrate into the ox-

ide layer, and the composition change of the surface region may be

responsible for the resistance change. H. Y. Jeong et al. [81] per-

formed EELS oxygen element mapping experiments in HRS and

LRS of Al/TiO2/Al structure. The results suggest that the drift of

oxygen ions by the applied bias is the microscopic origin of the

bistable resistivity switching. So the reset mechanism for bipolar

15

switching is quite unambiguous in the literature [82-84]. Recently,

the nonlinear dynamical properties of bipolar switching TiO2 were

modeled by the drift and diffusion of ionized dopants (oxygen va-

cancies) in the oxide thin film [85-87]. In essence, the description

using oxygen vacancies is equivalent to the description using oxygen

ions here.

In the unipolar switching case, the mainstream viewpoint of reset is

due to a thermal dissolution of CFs by local Joule heating [88-90].

Electro-thermal calculation [88] suggests that the local temperature

can rise to around 600 K during the switching process. But this

model is only phenomenological and does not reveal the micro-

scopic nature of the rupture of CFs. Firstly, it does not address

whether the loss of oxygen during set process can be recaptured in

subsequent switching cycles or not, and the model does not address

the question of whether the set process is a reversible process. Sec-

ondly, if the CFs are assumed to be simply “dissolved” by local

Joule heating, then the CFs should rupture in the middle of the fila-

ment where the temperature is highest [91], since the metal elec-

trodes work as a large heat sink. The local Joule heating conjecture

contradicts with the many experimental observations that switching

occurs in the region near the anode as mentioned before. Alterna-

tively, M.-J. Lee et al. [71] regarded the reset process of their unipo-

lar NiO memory as an oxidation process of the metallic CFs, which

is a consequence of the thermally activated oxygen atoms diffusing

from anode side followed by oxidation of the Ni-rich CFs. This ar-

gument acknowledges that the reset in unipolar switching is a Joule

16

heating-assisted process. At the same time, this argument is essen-

tially consistent with the electrochemical ionic migration model for

bipolar switching devices. The model provides an inherent link be-

tween unipolar and bipolar switching. In the next section, we discuss

another important question of why some materials exhibit unipolar

characteristics, while some other materials exhibit bipolar character-

istics before we make the final conclusion.

13.2.3 The Effect of Electrode Materials on Switching Modes There are many reports [92-94] on the effect of electrode materials

on the resistive switching characteristics of metal oxide memory. In

most cases, the switching mode is not an inherent property of the ox-

ide film but an effect of the interaction between the oxide and elec-

trode materials. R. Waser et al. pointed out that for bipolar switching

the MIM structure should have some asymmetry, such as different

electrode materials, while for uniploar switching the MIM structure

may be symmetric [27]. Fig. 6 shows two examples: the Pt/ZnO/Pt

[61] and Pt/NiO/Pt [20] structure show uniplolar switching, while

the TiN/ZnO/Pt [95] and Pt/NiO/SrRuO3 [96] structure show bipolar

switching. Besides, many other metal oxides can show either unipo-

lar or bipolar behavior depending on what electrode materials are

used. Pt/ZrO2/Pt [97], Pt/TiO2/Pt [21], Pt/HfO2/Pt [62] all show

unipolar switching, and Ti/ZrO2/Pt [97], Pt/TiO2/TiN [98], TiN/

HfO2/Pt [99] all show bipolar switching. It should be noted that the

unipolar switching I-V curves are usually symmetric, since there is

no distinction of either of the electrodes. As a result, for unipolar

17

switching devices, bipolar switching behaviors can also be demon-

strated [100], which means the set can be triggered at one polarity

and reset can be triggered at the reversed polarity. Such case is also

referred to “non-polar” switching [74]. But in bipolar switching de-

vices, there is always one polarity that reset cannot occur when the

same polarity bias as set process is applied.

Fig. 6 (a) I-V characteristics of Pt/ZnO/Pt and TiN/ZnO/Pt devices, (b) Pt/NiO/Pt

and Pt/NiO/SrRuO3 devices, showing the electrode materials effect on switching

modes.

Data are collected from:

Ref [1] W.-Y. Chang, Y.-C. Lai, T.-B. Wu, S.-F. Wang, F. Chen, and M.-J. Tsai,

Appl. Phys. Lett. 92, 022110 (2008).

Ref [2] N. Xu, L. F. Liu, X. Sun, C. Chen, Y. Wang, D. D. Han, X. Y. Liu, R. Q.

Han, J. F. Kang, and B. Yu, Semicond. Sci. Technol. 23, 075019 (2008).

Ref [3] S. Seo, M. J. Lee, D. H. Seo, E. J. Jeoung, D.-S. Suh, Y. S. Joung, and I. K.

Yoo, I. R. Hwang, S. H. Kim, I. S. Byun, J.-S. Kim, J. S. Choi, and B. H. Park,

Appl. Phys. Lett. 85, p. 5655 (2004).

Ref [4] J. S. Choi, J.-S. Kim, I. R. Hwang, S. H. Hong, S. H. Jeon, S.-O. Kang, B.

H. Park, D. C. Kim, M. J. Lee, and S. Seo, Appl. Phys. Lett. 95, 022109 (2009).

The electrode materials can be roughly classified into two groups:

one is noble metals, such as Pt, Au, Ru, etc, which are resistant to

oxidation; the other one is non-noble metals, such as Ti, Al, Cu, Ni,

W, TiN, TaN, etc, which may suffer oxidation during the switching

process. As observed above, devices using noble metals always

show unipolar behaviors. Even with the Pt/TiO2/TiN [98] structure,

unipolar switching can occur at the Pt side. However, the unipolar

switching cannot occur at TiN side, and only bipolar switching is ob-

18

tained at the TiN side. As mentioned before, during the set process,

the oxygen ions migrate toward the anode. Thus, the anode materials

may react with the oxygen and form an interfacial layer if the anode

materials are oxidizable. P. Zhou et al. [101] compared the different

roles played by the Pt electrode and the TaN electrode on the switch-

ing modes of CuxO memory. Fig. 7 (a) and (b) shows depth profile

by Auger Electron Spectroscopy (AES) for Pt/CuxO/Cu structure and

TaN/CuxO/Cu structure, we can see that the oxygen concentration

has an obvious shift towards the TaN layer, which indicates that a re-

action occurs between the TaN electrode and oxide film. This inter-

facial TaON layer was further confirmed by XPS binding energy

depth spectra. The bright gray areas under the TaN electrode in the

TEM picture of Fig. 7 (c) are assumed to be the TaON ultra-thin

layer. And Fig. 7 (d) illustrates that with Pt as top electrode, reset

can occur at both bias polarities, showing a unipolar switching be-

havior, while with TaN as top electrode, reset can occur only under

the reversed bias, showing a bipolar switching behavior. Therefore,

we can infer that if noble metals like Pt are used for the electrode, it

hardly forms such interfacial oxide layer. And without the diffusion

barrier, the thermally activated oxygen ions may diffuse back during

the reset process to the oxide bulk layer since there is a large con-

centration gradient of oxygen across the interface region. This may

account for the unipolar reset mechanism. If oxidizable materials are

used for the electrode, it may form an interfacial oxide layer be-

tween the electrode and oxide films, which may act as an oxygen

diffusion barrier. Thus, it is difficult for the oxygen ions to diffuse

19

back through the thermal activation. Then only by the acceleration

of a reversed electric field can the oxygen ions drift back to rupture

the CFs. This may account for the bipolar reset mechanism. Numeri-

cal simulation [102] based on the oxygen ions non-linear transport

model is employed to support the above assumptions.

Fig. 7 (a) Auger Electron Spectroscopy (AES) depth profile of (a) Pt/CuxO/Cu

structure and (b) TaN/CuxO/Cu structure, indicating the existence of an interfacial

TaON layer; (c) TEM picture of the TaN/CuxO/Cu structure, showing the interfa-

cial TaON layer; (d) I-V characteristics of Pt/CuxO/Cu structure with unipolar

switching behavior and TaN/CuxO/Cu structure with bipolar switching behavior.

Reprinted from [101]

13.2.4 Summary of the Physical Mechanism for Resistive Switch-ing in Metal Oxide Memory

Here, we would like to summarize the physical resistive switch-

ing mechanism in metal oxide memory. It should be noted, however,

while a self-consistent physical picture can be constructed through

the discussions above, the resistive switching phenomenon in metal

oxides involves a large variety of materials, so the model described

here may not apply to all combinations of materials.

Basically, resistive switching is conjectured to be due to the for-

mation and dissolution of conductive filaments localized at the an-

ode interface, and is a reversible switching process. The conductive

filaments may consist of oxygen vacancies or excess metallic precip-

itates. Multiple, parallel filaments may be formed. The filaments

may preferentially be located at the grain boundaries. Experimental

evidences suggest that the switching process is an electrochemical

20

process associated with oxygen migration, oxidation and reduction.

As shown in Fig. 8, during the electroforming process, soft dielectric

breakdown occurs and oxygen ions drift to the anode interface by

the high electric field, where they are discharged as neutral non-lat-

tice oxygen if the anode materials are noble metals or react with the

oxidizable anode materials to form an interfacial oxide layer. Mean-

while in the bulk, the resultant oxygen vacancies or metal precipi-

tates form the highly conducting paths. During the reset process,

oxygen ions migrate back to the bulk either to recombine with the

oxygen vacancies or to oxidize the metal precipitates. In the unipolar

switching case, the Joule heating thermally activates the diffusion of

oxygen ions. Oxygen ions diffuse against the electric field from the

anode due to the concentration gradient. In the bipolar switching

case, usually interfacial layer between the anode and oxide acts as a

diffusion barrier, and oxygen ions can only drift back aided by the

electric field. Usually only a part of the conducting paths is ruptured,

leaving the bottom part of the conducting paths to be a virtual cath-

ode that extend partially into the film. Then during the subsequent

set process, a process similar to the electroforming occurs but only

in the region near anode. The physical picture presented here does

not contradict with the previous thermal model for unipolar switch-

ing or ionic model for bipolar switching. And it can at best be

viewed as a phenomenological description of experimental observa-

tions. Details of the physics of switching remain an area of active re-

search.

21

Fig. 8 Schematic of the switching process in metal oxide memory

13.3 Performances of Metal Oxide Memory Devices

Firstly, we would like to discuss the fabrication techniques briefly.

Currently, the fabrication of metal oxide memory devices uses

mainly conventional semiconductor fabrication processes. Sputter-

ing of metals followed by annealing in oxygen ambient or reactive

sputtering in oxygen ambient are the most common deposition tech-

niques for metal oxide layers. Other methods used are atomic layer

deposition (ALD) [30, 43], pulsed laser deposition (PLD) [103],

metal organic chemical vapor deposition (MOCVD) [26] and the

sol-gel method [104]. Several papers report resistive switching be-

havior of self-assembly grown nanostructure, e.g. NiO nanowires

[105-106]. The thickness of the metal oxide layer is usually around

10-50 nm. The substrate of the devices is mainly silicon; however,

there are several efforts to fabricate metal oxide memory on trans-

parent substrate, e.g. glass [107] or flexible substrate, e.g. polyether-

sulfone (PES) [108-109]. In the rest of this section, we will discuss

the characteristics of metal oxide memory devices including noise

margin, scalability, power consumption, speed, reliability and uni-

formity.

The noise margin for the read operation is characterized by the

HRS/LRS resistance ratio. Generally, a ratio >10 is desired for easier

sense amplifier design. Almost all the metal oxide memory devices

in the literature exceed this requirement.

Scalability is one of the key concerns for any kind of memory. Be-

22

cause of the filamentary conduction nature, metal oxide memory de-

vices may be scaled down to the nanoscale. Sub-100nm feature size

cells have been fabricated by 193-nm lithography with a contact

hole structure [78], as well as by nanoimprint lithography or e-beam

lithography with a crossbar arrays structure [51, 110-111]. Recently,

aggressively scaled 30 nm×30 nm HfO2 memory devices in 1Kb ar-

ray have been demonstrated with excellent yield [31]. Resistive

switching behavior has been successfully triggered by C-AFM tip on

a 10 nm × 10 nm region of NiO thin films [71], suggesting the po-

tential to scale the cell size even down to the sub-10 nm regime. Fig.

9 plots the general scaling trend of HRS and LRS resistance. The

leakage current in HRS is mainly due to bulk leakage current. Thus,

the resistance of HRS increases as the inverse of the cell area,

roughly following the Ohm’s law. The conduction current in LRS is

mainly filamentary conduction current, as discussed before. So the

resistance of LRS has only a slight dependency on the cell area. This

trend of increasing HRS/LRS resistance ratio as cell area decreases

is a benefit of device scaling.

Fig. 9 HRS and LRS resistance versus cell area of metal oxide memory devices.

Data are collected from:

Ref [1] I. G. Baek, M. S. Lee, S. Seo, M. J. Lee, D. H. Seo, D.-S. Suh, J. C. Park, S.

O. Park, H. S. Kim, I. K. Yoo, U.-I. Chung, and I. T. Moon, Tech. Dig. IEDM, p.

587 (2004).

Ref [2] H. Y. Lee, P. S. Chen, T. Y. Wu, Y. S. Chen, C. C. Wang, P. J. Tzeng, C. H.

Lin, F. Chen, C. H. Lien, and M.-J. Tsai, Tech. Dig. IEDM, p. 297 (2008).

Ref [3] N. Xu, B. Gao, L. F. Liu, B. Sun, X. Y. Liu, R. Q. Han, J. F. Kang, and B.

23

Yu, Tech. Dig. Symp. VLSI Technol., p. 100 (2008).

Ref [4] S. Kim, H. Moon, D. Gupta, S. Yoo, and Y.-K. Choi, IEEE Trans. Electron

Devices 56, p. 696 (2009).

Ref [5] M. K. Yang, J.-W. Park, T. K. Ko, and J.-K. Lee, Appl. Phys. Lett. 95,

042105 (2009).

Ref [6] H. B. Lv, M. Yin, X. F. Fu, Y. L. Song, L. Tang, P. Zhou, C. H. Zhao, T. A.

Tang, B. A. Chen, and Y. Y. Lin, IEEE Electron Device Lett. 29, p.309 (2008).

Ref [7] X. Sun, B. Sun, L. F. Liu, N. Xu, X. Y. Liu, R. Q. Han, J. F. Kang, G. Xiong,

and T. P. Ma, IEEE Electron Device Lett. 30, p. 334 (2009).

Although the read noise margin is improved in the scaled memory

cell, the filamentary conduction nature of the memory cell results in

increasing power density as devices scale down. The typical switch-

ing voltage in literature is around 1-5 V, while the switching current

can be many orders different, depending on the material and the de-

vice structure. The key to reducing power consumption is to reduce

the reset switching current. The peak value of current in metal oxide

memory is the LRS current at the point when the reset process oc-

curs, which is usually referred to as the reset current. Recently, Y.

Wu et al. [112] have demonstrated extremely low reset current (~1

μA) for ALD grown Al2O3 memory cell. Yet, most reports in the lit-

erature show a typical reset current for a single device on the order

of mA or hundreds of μA. Fig. 10 plots the general scaling trend of

reset current and corresponding reset current density. It is seen that

the reset current reduce only slightly when the devices are scaled

down, thus leading to a remarkable increase of the current density

required for reset. This presents a significant challenge for the mem-

ory cell selection devices, which need to provide such a large current

24

density for ultra-scaled cells, e.g. ~ MA/cm2 even for a relatively

large 100 nm×100 nm cell area. Although there is contrary view-

point that the reset current would decrease with reduced cell area

[113], it should be noted that it is not a fair comparison because in

those experiments smaller set compliance was applied for the

smaller memory cell. We will see in the following discussions that

the reset current value can be modulated by controlling of the set

compliance value. Fig. 11 plots the relationship between reset cur-

rent and set compliance current. It is seen that reset current is usually

only a little larger than the set compliance current, and more impor-

tantly, the reset current decreases almost linearly with the decrease

of set compliance current. A possible reason for this relationship is

that with a smaller set compliance current, less oxygen atoms mi-

grate to the anode and weaker CFs are formed during the set process.

Thus a smaller reset current is needed to rupture the CFs. In the liter-

ature the reset current of single memory cell is usually difficult to be

reduced down to sub mA regime, even if sub mA set compliance

current is applied. The deviation from the linear relationship be-

tween reset current and set compliance is most probably due to the

parasitic capacitance in the measurement setup as discussed in [114].

Thus the reset current tends to be elevated at the mA level even if

the set compliance of the parameter analyzer used in the measure-

ment is reduced down to the μA level. By using an on-chip 1 transis-

tor-1 resistor (1T-1R) structure rather than the single resistor (1R)

structure, the parasitic capacitance is greatly reduced, thus the reset

current tends to follow the linear relationship with set compliance

25

current. Sub-100 μA reset current has been successfully demon-

strated in several 1T-1R cell structures by adjusting the selection

transistor’s gate voltage to deliver a small set compliance current

[30, 115-117]. As a consequence, however, the smaller set compli-

ance may result in a smaller HRS/LRS resistance ratio. Fig. 12 plots

the dependence of the LRS resistance on the set compliance current.

The LRS resistance increases almost inversely with the decreasing

set compliance current. Smaller set compliance forms weaker CFs,

thus leading to a larger LRS resistance. Given certain HRS resis-

tance, the requirement for a sufficient ratio limits the smallest set

compliance that can be used. Remember that HRS resistance rises up

rapidly with the decrease of cell area, as mentioned before. This

means for the scaled memory cell, a larger LRS resistance can be

tolerated, and a smaller set compliance can be utilized to achieve

lower reset current. With this methodology, by using 5 μA set com-

pliance, a greatly reduced reset current (~50 μA) is demonstrated in

a 100 nm×100 nm NiO memory cell with sufficient HRS/LRS ratio

(~104) [71, 113].

Fig. 10 The peak value of reset current and corresponding current density versus

cell area

Data are collected from:

Ref [1] I. G. Baek, M. S. Lee, S. Seo, M. J. Lee, D. H. Seo, D.-S. Suh, J. C. Park, S.

O. Park, H. S. Kim, I. K. Yoo, U.-I. Chung, and I. T. Moon, Tech. Dig. IEDM, p.

587 (2004).

Ref [2] H. Y. Lee, P. S. Chen, T. Y. Wu, Y. S. Chen, C. C. Wang, P. J. Tzeng, C. H.

Lin, F. Chen, C. H. Lien, and M.-J. Tsai, Tech. Dig. IEDM, p. 297 (2008).

26

Ref [3] C. Rohde, B. J. Choi, D. S. Jeong, S. Choi, J.-S. Zhao, and C. S. Hwang,

Appl. Phys. Lett. 86, 262907 (2005).

Ref [4] K. M. Kim, B. J. Choi, B. W. Koo, S. Choi, D. S. Jeong, and C. S. Hwang,

Electrochem. Solid-State Lett., 9, G343 (2006).

Ref [5] K. M. Kim, B. J. Choi, and C. S. Hwang, Appl. Phys. Lett. 91, 012907

(2007).

Ref [6] C. Yoshida, K. Tsunoda, H. Noshiro, and Y. Sugiyama, Appl. Phys. Lett. 91,

223510 (2007).

Ref [7] Y. C. Shin, J. Song, K. M. Kim, B. J. Choi, S. Choi, H. J. Lee, G. H. Kim, T.

Eom, and C. S. Hwang, Appl. Phys. Lett. 92, 162904 (2008).

Ref [8] W.-Y. Chang, Y.-T. Ho, T.-C. Hsu, F. Chen, M.-J. Tsai, and T.-B. Wu, Elec-

trochem. Solid-State Lett., 12, H135 (2009).

Ref [9] X. Sun, B. Sun, L. F. Liu, N. Xu, X. Y. Liu, R. Q. Han, J. F. Kang, G. Xiong,

and T. P. Ma, IEEE Electron Device Lett. 30, p. 334 (2009).

Fig. 11 The reset current versus set compliance current

Data are collected from:

Ref [1] S. Seo, M. J. Lee, D. H. Seo, E. J. Jeoung, D.-S. Suh, Y. S. Joung, and I. K.

Yoo, I. R. Hwang, S. H. Kim, I. S. Byun, J.-S. Kim, J. S. Choi, and B. H. Park,

Appl. Phys. Lett. 85, p. 5655 (2004).

Ref [2] K. Kinoshita, K. Tsunoda, Y. Sato, H. Noshiro, S. Yagaki, M. Aoki, and Y.

Sugiyama, Appl. Phys. Lett. 93, 033506 (2008).

Ref [3] K. Tsunoda, K. Kinoshita, H. Noshiro, Y. Yamazaki, T. Iizuka, Y. Ito, A.

Takahashi, A. Okano, Y. Sato, T. Fukano, M. Aoki, and Y. Sugiyama, Tech. Dig.

IEDM, p. 767 (2007).

Ref [4] C. Rohde, B. J. Choi, D. S. Jeong, S. Choi, J.-S. Zhao, and C. S. Hwang,

Appl. Phys. Lett. 86, 262907 (2005).

Ref [5] H. Shima, F. Takano, H. Muramatsu, H. Akinaga, Y. Tamai, I. H. Inque,

and H. Takagi, Appl. Phys. Lett. 93, 113504 (2008)

27

Fig. 12 LRS resistance versus set compliance current

Data are collected from:

Ref [1] K. Tsunoda, K. Kinoshita, H. Noshiro, Y. Yamazaki, T. Iizuka, Y. Ito, A.

Takahashi, A. Okano, Y. Sato, T. Fukano, M. Aoki, and Y. Sugiyama, Tech. Dig.

IEDM, p. 767 (2007).

Ref [2] B. Lee, H.-S. P. Wong, Tech. Dig. Symp. VLSI Technol., p. 28 (2009).

Ref [3] C.-Y. Lin, C.-Y. Wu, C.-Y. Wu, C. Hu, and T.-Y. Tseng, J. Electrochem. Soc.

154, G189 (2007).

Ref [4] D. Lee, D.-J. Seong, H. J. Choi, I. Jo, R. Dong ,W. Xiang, ,S. Oh, M. Pyun,

S.-O Seo, S. Heo, M. Jo, D.-K. Hwang, H. K Park, M. Chang, M. Hasan, and H.

Hwang, Tech. Dig. IEDM, p. 1 (2006).

An attractive feature of metal oxide memory is the nanosecond

switching speed, which is comparable to DRAM and is substantially

faster than Flash on a single bit programming basis. It is at least

three to ten times faster than the emerging phase change memory.

Fig. 13 plots the HRS and LRS resistance versus the programming

pulse width. It is seen that with smaller pulse width, HRS resistance

drops while LRS resistance rises, leading to a smaller HRS/LRS re-

sistance ratio. The shorter pulses result in a less complete switching

process. Thus, the requirement to maintain a sufficient noise margin

limits the switching speed. The measurement of switching speed in-

volves a delicate procedure [118]: a load resistor is connected in se-

ries with the memory cell; the programming pulse (Vp) is applied to

the stacked resistor and cell structure through a pulse generator,

while an oscilloscope is used to monitor the voltage (Vcell) across the

memory cell. Note that Vcell = Vp×Rcell / (Rcell+RL), thus the time

28

when Vcell suddenly rises or drops can be estimated as the switching

time of reset or set process for the applied cell voltage Vcell. The

magnitude of the current can be calculated from the measured cell

voltage at the oscilloscope divided by load resistor, Icell = Vcell/Rcell.

With this methodology, the relationship between the switching time

and the pulse amplitude can be investigated. There are reports indi-

cating that in order to achieve faster switching, a larger pulse ampli-

tude is required [119]. Therefore, a trade-off exists between fast

switching speed and low power consumption. Bipolar switching de-

vices have shown ultra-fast switching speed using reasonable volt-

age pulse amplitudes, e.g. +2 V/10 ns for set and -1.5 V/10 ns for re-

set in TaOx memory [64], +3.2 V/5 ns for set and -2.7 V/5 ns for re-

set in HfO2 memory [30]. Some earlier works showed that for unipo-

lar switching devices, the reset process needs a much longer pulse

width than set process, e.g. +1 V/10 ns for set and +0.5 V/5 μs for

reset in NiO memory [73], +3 V/10ns for set and +2.5 V/5 μs for re-

set in TiO2 memory [120]. It is suggested that a certain amount of

time (~μs) is necessary to sufficiently heat up the CFs to trigger the

rupture [120], since the unipolar reset mechanism involves a ther-

mally assisted oxygen diffusion process. But recently, several works

demonstrated that ultra-fast reset switching speed that is comparable

to the set switching speed is also achievable in unipolar switching

devices, e.g. +2.8 V/10 ns for set and +1.8 V/5 ns for reset in Ti-

doped NiO memory [121], +1.5 V/10 ns for set and +1 V/10 ns for

reset in scaled NiO memory [113]. It is shown that the reset switch-

ing time decreases significantly with decreasing cell area, from 1 μs

29

(30 μm×30 μm cell) to 10 ns (100 nm×100 nm cell) for unipolar

NiO memory [71]. If individual CFs are similar in size or resistivity

and only the number of CFs varies between different cell areas, then

the switching time should be insensitive to the cell area, because

CFs are connected in parallel and ruptured independently. Therefore,

it is inferred the CFs should be weaker or have larger resistivity for

the smaller cells [71]. This trend that smaller cells have faster

switching speed can also be due to the smaller parasitic capacitance

of the smaller cell.

Fig. 13 HRS and LRS resistance versus the programming pulse width

Data are collected from:

Ref [1] S. Muraoka, K. Osano, Y. Kanzawa, S. Mitani, S. Fujii, K.Katayama, Y.

Katoh, Z. Wei, T. Mikawa, K. Arita, Y. Kawashima, R. Azuma, K. Kawai, K. Shi-

makawa, A. Odagawa, and T. Takagi, Tech. Dig. IEDM, p. 779 (2007).

Ref [2] K. Tsunoda, K. Kinoshita, H. Noshiro, Y. Yamazaki, T. Iizuka, Y. Ito, A.

Takahashi, A. Okano, Y. Sato, T. Fukano, M. Aoki, and Y. Sugiyama, Tech. Dig.

IEDM, p. 767 (2007).

Ref [3] A. Chen, S. Haddad, Y. C. Wu, Z. Lan, T. N. Fang, and S. Kaza, Appl.

Phys. Lett. 91, 123517 (2007).

Ref [4] B. J. Choi, S. Choi, K. M. Kim, Y. C. Shin, C. S. Hwang, S.-Y. Hwang, S.-S.

Cho, S. Park, and S.-K. Hong, Appl. Phys. Lett. 89, 012906 (2006).

Ref [5] Y. H. Do, J. S. Kwak, Y. C. Bae, K. Jung, H. Im, and J. P. Hong, Appl.

Phys. Lett. 95, 093507 (2009).

The reliability characteristics include the endurance and retention.

Current Flash technology shows a maximum number of program-

ming cycles between 103 and 107, depending on the device type.

30

Metal oxide memory should provide at least the same endurance,

preferably a better one. Excellent endurance records in the literature

are shown for unipolar NiO memory (>106) [73], bipolar HfO2 mem-

ory (>106) [30], and bipolar TaOx memory (>109) [64] at the single

cell level. The failure of switching may be due to grain structure

change near the anode region [56] and insufficient non-lattice oxy-

gen ions to rupture the CFs [83], since during the repeated switching

cycles, oxygen may escape from the device. Most non-volatile mem-

ory applications specify at least 10 years data retention time at typi-

cal operating temperatures (e.g. 85 0C). Promising retention records

in the literature are shown for unipolar Ti-doped NiO memory

(>1000 hours @ 150 0C) [121], and bipolar TaOx memory (>3000

hours @ 150 0C) [64]. A practical method to estimate the retention

capability is to draw the Arrhenius plot of retention time versus the

reciprocal of temperature, and extrapolate the data obtained in high

temperature regime to the operating temperature (e.g. 85 0C) [64,

122]. The loss of data in LRS or HRS may be associated with the

diffusion of oxygen ions or oxygen vacancies due to their concentra-

tion gradient, and this process can be accelerated at elevated temper-

ature because of the temperature dependent diffusion coefficient.

This is the basis of any temperature varying experiments to estimate

the retention time. A more complicated statistical method to estimate

the retention capability by temperature–accelerated measurement is

developed by A. Chen et al. [123].

Uniformity of device characteristics is a key problem that hinders

the metal oxide memory from entering large-scale manufacturing.

31

Significant parameter fluctuations exist in terms of variations of the

switching voltages as well as the resistance in HRS and LRS. These

parameters fluctuate from programming cycle to programming cycle

and from device to device. Many efforts have been expended to im-

prove the uniformity. D. C. Kim et al. [124] proposed to use IrO2 as

the top electrode for the NiO memory to help stabilize the local oxy-

gen migrations for the formation and rupture of CFs. W.-Y. Chang et

al. [125] proposed to embed Pt nanocrystals into the TiO2 memory to

provide an easy path for the formation and rupture of CFs by local

enhancement of the electric field adjacent to the Pt nanocrystals. S.

Yu et al. [126] proposed to stack a thin Al buffer layer on HfO2

memory to diffuse Al impurity atoms into the switching layer, aim-

ing to stabilize the formation and rupture of CFs along the impurities

due to a lower Vo formation energy caused by the impurities. Q. Liu

et al. [127] proposed to implant Ti into ZrO2 memory to provide a

source of Vo and play the role of a seed for forming CFs. The key

idea of these techniques is to induce the formation and rupture of

CFs in specific locations during the switching instead of allowing

them to occur randomly. Besides materials solutions mentioned

above, novel programming methods are also helpful in reducing pa-

rameter fluctuations. Using multiple pulses rather than a single pulse

[128] or using a ramped series of pulses [129] can remarkably im-

prove the cycle to cycle uniformity.

To summarize, the scalability of metal oxide memory devices is the

most competitive characteristics compared with other emerging

memories. It is foreseeable to achieve sufficient noise margin

32

(>10X), low energy consumption (<pJ per switching cycle), fast

switching speed (~ns) for nanoscale (10 nm×10 nm) cells in the near

future. However, the reliability and uniformity of metal oxide mem-

ory needs to be further improved before this technology can be com-

mercialized.

13.4 Cell Structure of Metal Oxide Memory Arrays

For random access application, each metal oxide memory cell is

usually connected with a cell selection transistor). This cell structure

is referred to as 1 transistor-1 resistor (1T-1R). By controlling the se-

lection transistor’s gate voltage, varying current can be provided to

control the switching characteristics of memory cell. As mentioned

in Section 3, a smaller set compliance results in a larger LRS resis-

tance, which is preferred to reduce reset current. At the same time,

the set compliance should be larger enough to guarantee a sufficient

HRS/LRS resistance ratio. By adjusting the selection transistor’s

gate voltage, it is easy to optimize the programming current for the

set and reset processes [115-116, 119]. However, the area penalty of

using a selection transistor is apparent, even with a delicate layout

design of integrating the memory cell into the via contact of the tran-

sistor. The 1T-1R cell area can range from 6F2 (F: feature size used

for patterning the cell) using aggressive DRAM-like design rules

with borderless contacts and zero gate to source/drain spacing to 8F2

33

(with F/2 gate to source/drain spacing) and 18F2 (contacts with bor-

ders).

For high-density integration, a crossbar matrix with 4F2 area is

preferred. The simplest way is to connect the word and bit lines at

each node by a memory cell. The crossbar matrix can be a set of or-

thogonal nanoscale metal wires with the metal oxide as the memory

element at the crossbar junction. TiO2 memory with junction area

(50 nm×50 nm) [51], NiO memory with junction area (70 nm×70

nm) [110] have been reported. B. Lee et al. [111] demonstrated a

novel structure for NiO memory which utilizes the sidewalls be-

tween the two nanoscale metal wires as the active switching region.

Thus, the active memory cell area is even smaller than the layout

cell area (48 nm×48 nm).

A cross-talk problem with the above simple crossbar matrix may

arise in read operation [130]. As shown in Fig. 14 (a), if the cell to

be read out happens to be in HRS with surrounding cells in LRS, the

reading current can easily flow through the surrounding cells in the

LRS and thus a LRS data will be mistakenly read out. In order to

avoid these parasitic leakage paths, a cell selection element with

large I-V non-linearity should be added at each node. The cell selec-

tion element is usually envisioned to be a diode (with an exponential

I-V characteristics). Therefore, this cell structure refers to 1 diode-1

resistor (1D-1R). The reverse biased diodes effectively cuts off the

leakage current paths, thus the interference between neighboring

cells is prevented, as shown in Fig. 14 (b). The diode on/off ratio re-

quired ranges from 104 to 106 depending on the memory array size,

34

the on/off ratio of the memory cell, and the resistance of the inter-

connect wire, etc. It should be noted for the 1D-1R structure, the re-

sistive switching element must be unipolar switching devices be-

cause the diode limits the reversed current that a bipolar switching

device requires.

Fig. 14 The crossbar matrix (a) without cell selection elements and (b) with cell

selection elements

With such crossbar structure, the cell area can in principle be

scaled down to 4F2. Furthermore, by stacking the crossbar structure

in the third dimension, the effective cell size can be further reduced

to 2F2, 1F2, and so on [131]. The 1D-1R structure can be stacked for

3-D integration. Thus there are successive attempts to fabricate

stacked nanowire arrays for NiO memory with different cell selec-

tion elements [132-135].

Here we would like to discuss the cell selection element material.

A p–n diode is the most common device for the cell selection ele-

ment. Although high performance p–n diode is easily fabricated with

current epitaxial silicon technology for the planar device structures,

it is not feasible to implement epitaxial silicon-based p–n diode into

the stacked crossbar metal oxide memory structures because it is dif-

ficult to grow epitaxial silicon on a metal layer and high processing

temperatures are required. On the other hand, amorphous silicon al-

lows for lower processing temperatures. But it does not meet the re-

quirement for current density for memory cell programming. There-

fore, new materials need to be explored for the cell selection ele-

35

ment, which should both allow for low processing temperatures and

also provide high current drive. Compared with silicon diode, oxide

diode is attractive because it offers better flexibility in processing

technology because it can be fabricated over any substrate even at

room temperature [131]. If the oxide material is oxygen deficient

with sufficient amount of oxygen vacancies, such as TiO2, ZrO2,

ZnO and indium tin oxide (ITO), it is n-type; while if the oxide ma-

terial is metal deficient with sufficient amount of metal vacancies,

such as NiO, it is p-type. Thus a combination of p-type oxide and n-

type oxide essentially forms a p-n diode. The research on oxide

diode started earlier than that on the metal oxide memory even in the

1990s, e.g. p-NiO/n-Al: ZnO [136], p-NiO/n-ITO [137]. Recently,

several kinds of oxide diodes [133], such as p-NiO/n-TiO2, p-NiO/n-

ZnO, p-NiO/n-InZnO, p-CuO/n-InZnO, have been stacked with Pt/

NiO/Pt structure in series, among which p-CuO/n-InZnO is regarded

as the best candidate. Besides the p-n oxide diode, single oxide ma-

terials can also be applied to rectify the current. Y. C. Shin et al.

[138] demonstrated a Schottky-type cell structure consisting of Pt/

ITO/TiO2/Pt stacked layers. The low and high potential barrier at the

ITO/TiO2 and TiO2/Pt junctions, respectively, constitute the rectify-

ing properties of the stacked structure, where TiO2 acts as the resis-

tive switching layer. VO2 is found to exhibit electric field-induced

metal–insulator transition [139]. Unlike other metal oxide memory

devices, the resistive switching behavior in VO2 is not bistable, so it

is sometimes referred to threshold switching. The sharp transition of

current in VO2 when turned on provides an ideal behavior for

36

switching element. M.-J. Lee et al. [140] demonstrated a prototype

cell structure consisting of Pt/VO2/Pt/NiO/Pt stacked layers. Table

13.2 compares several switching elements mentioned here for the

metal oxide memory cell in aspects of forward current density, for-

ward/reverse current ratio, and turn on voltage. Generally, high for-

ward current density, high forward/reverse current ratio, and low

turn on voltage are preferred. Programming current density of the or-

der of 10 MA/cm2 is required for metal oxide memory today. Thus,

the oxide based diodes reported to date are several orders of magni-

tude too low in current drive for the crossbar memory application.

p-NiO/n-TiO2

Ref [1]p-NiO/n-ZnO

Ref [1]p-NiO/n-IZO

Ref [1]p-CuO/n-IZO

Ref [1]ITO

Ref [2]VO2

Ref [3]Forward Current Density (A/cm2) ~20 ~300 ~10,000 ~30,000 ~1,400 ~4,000*

Forward/Reverse Current Ratio 4.7×105 2.6×105 3×104 3×104 1×104 N/A

Turn on Voltage (V) 2.72 1.55 0.73 0.66 0.62 0.6

Table 13.2 Comparison of several oxide switching elements for the metal oxide

memory cell. Forward current density is extracted at +2V bias, forward/reverse

current ratio is defined at the current ratio at +2V and -2V, and turn on voltage is

defined as J = 100 A/cm2. *estimated.

Data are collected from:

Ref [1] M.-J. Lee, Y. Park, B.-S. Kang, S.-E. Ahn, C. Lee, K. Kim, W. Xianyu, G.

Stefanovich, J.-H. Lee, S.-J. Chung, Y.-H. Kim, C.-S. Lee, J.-B. Park, I.-G. Baek,

and I.-K.Yoo, Tech. Dig. IEDM, p. 771 (2007).

Ref [2] Y. C. Shin, J. Song, K. M. Kim, B. J. Choi, S. Choi, H. J. Lee, G. H. Kim, T.

Eom, and C. S. Hwang, Appl. Phys. Lett. 92, 162904 (2008).

Ref [3] M.-J. Lee, Y. Park, D.-S. Suh, E.-H. Lee, S. Seo, D.-C. Kim, R. Jung, B.-S.

Kang, S.-E. Ahn, C. B. Lee, D. H. Seo, Y.-K. Cha, I.-K. Yoo, J.-S. Kim, and B. H.

37

Park, Adv. Mater. 19, p. 3919 (2007).

Recently, M.-J. Lee et al. [141] demonstrated a 8×8 1D-1R array

with word/bit line selection transistors, as shown in Fig. 14. The

memory cell is aPt/NiO/Pt/p-CuO/n-InZnO/Pt stacked structure, and

the word line selection transistor is amorphous gallium indium zinc

oxide (GaInZnO) thin film transistor (TFT). Oxide TFT rather than

silicon transistor is utilized for the low processing temperature re-

quired for 3-D integration.

Fig. 15 (a) Scanning electron microscopy (SEM) image of an 8×8 1D–1R arrays

integrated with GaInZnO selection TFTs. Top image is the cross-section view of a

row in the 8×8 1D-1R arrays. (b) Image of the integrated devices shown over a

glass substrate. (c) I–V characteristics of a NiO cell, a 1D–1R cell, and a 1D–1R

cell with TFT selection transistor. (d) Schematic diagram of a 1D–1R cell with se-

lection transistor. Reprinted from [141]

13.5 Summary

A review of recent research progress of metal oxide memory is pre-

sented here. Possible physical mechanism of resistive switching in

metal oxides is discussed. Filamentary conductive paths dominate

the conduction in LRS. Electrochemical/electrothermal oxygen mi-

gration, oxidation and reduction may be the microscopic origin of

resistive switching behavior. Electrode materials play an important

role in determining the switching modes: bipolar or unipolar. The

38

device characteristics of metal oxide memory cells reported in the

literature are summarized. Sufficient noise margin, excellent scala-

bility, low power consumption, ultra-fast speed, good endurance and

retention make metal oxide memory a competitive candidate for fu-

ture non-volatile memory. Device uniformity must be further im-

proved in order to meet the large-scale manufacturing requirements.

Cell structure for high density memory array is discussed. The 1D-

1R crossbar array structure is promises ultra-high integration density

with the potential for 3-D integration. Low process temperature

memory cell selection element with the required current drive and

on/off ratio is the key to realizing 3-D stackable crossbar memory

arrays.

39

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