Universal Digital Controller for Boost CCM Power Factor Correction Stages Based on Current...

3818 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 29, NO. 7, JULY 2014

Universal Digital Controller for Boost CCM PowerFactor Correction Stages Based on Current

Rebuilding ConceptVictor M. Lopez, Student Member, IEEE, Francisco J. Azcondo, Senior Member, IEEE,

Angel de Castro, Member, IEEE, and Regan Zane, Senior Member, IEEE

Abstract—Continuous conduction mode power factor correction(PFC) without input current measurement is a step forward withrespect to previously proposed PFC digital controllers. Inductorvolt-second (vsL) measurement in each switching period enablesdigital estimation of the input current; however, an accurate com-pensation of the small errors in the measured vsL is required forthe estimation to match the actual current. Otherwise, they are ac-cumulated every switching period over the half-line cycle, leadingto an appreciable current distortion. A vsL estimation method isproposed, measuring the input (vg) and output voltage (vo). Dis-continuous conduction mode (DCM) occurs near input line zerocrossings and is detected by measuring the drain-to-source MOS-FET voltage vds . Parasitic elements cause a small difference be-tween the estimated voltage across the inductor based on input andoutput voltage measurements and the actual one, which must betaken into account to estimate the input current in the proposedsensorless PFC digital controller. This paper analyzes the currentestimation error caused by errors in the ON-time estimation, volt-age measurements, and the parasitic elements. A new digital feed-back control with high resolution is also proposed. It cancels thedifference between DCM operation time of the real input current,(T g

DCM ) and the estimated DCM time (T rebDCM ). Therefore, the

current estimation is calibrated using digital signals during opera-tion in DCM. A fast feedforward coarse time error compensation iscarried out with the measured delay of the drive signal, and a finecompensation is achieved with a feedback loop that matches theestimated and real DCM time. The digital controller can be used inuniversal applications due to the ability of the DCM time feedbackloop to autotune based on the operation conditions (power level,input voltage, output voltage. . .), which improves the operationrange in comparison with previous solutions. Experimental resultsare shown for a 1-kW boost PFC converter over a wide power andvoltage range.

Index Terms—Boost converter, continuous conduction mode,digital control, digital error compensation, power factor correc-tion, sensorless controller.

Manuscript received December 20, 2012; revised March 10, 2013, May 10,2013, and August 11, 2013; accepted August 16, 2013. Date of current versionFebruary 18, 2014. Recommended for publication by Associate Editor S. K.Mazumdar.

V. M. Lopez and F. J. Azcondo are with the Universidad de Cantabria, San-tander 39005, Spain (e-mail: [email protected]; [email protected]).

A. de Castro is with the Universidad Autonoma de Madrid, Madrid 28049,Spain (e-mail: [email protected]).

R. Zane is with the Department of Electrical Communication Engineer-ing, Utah State University. Logan, UT 84322-4120 USA (e-mail: [email protected]).

Color versions of one or more of the figures in this paper are available onlineat http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TPEL.2013.2280077

Fig 1. (a) Traditional PFC converter with current sensor. (b) Thermal imageat full load.

Fig. 2 (a) Typical PFC scheme with digital control and a current sensor.(b) Analog to digital conversion circuit of the input current.

I. INTRODUCTION

SOME advantages that motivate the use of digital control inPFC stages include: reduction of discrete components, re-

duction of size, reduction of sensitivity to parameter tolerances,ease of controller implementation, and extension of its perfor-mance limits. A resistive sensor is the most commonly usedsolution for current sampling. The power dissipated by this re-sistor causes a hot spot in the converter, as shown in Fig. 1. Thefirst criterion to determine the value of the resistor is often thegain of the amplifier stage (see Fig. 2) [1]. Furthermore, the cur-rent analog-to-digital converter (ADC) must have a wide band-width, increasing the cost in comparison with voltage ADCs.Current estimation techniques to reduce cost and maintain per-formance based on voltage measurements are presented in [2],[5] for single-phase and multiphase converter applications,

0885-8993 © 2013 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.See http://www.ieee.org/publications standards/publications/rights/index.html for more information.

LOPEZ et al.: UNIVERSAL DIGITAL CONTROLLER FOR BOOST CCM POWER FACTOR CORRECTION STAGES 3819

Fig. 3. Input voltage and power range of the recent works in sensorless PFCcontrollers. The green area represents the goal of this study.

respectively. For PFC applications, several works have beenpresented to avoid sensors or ADC chips in the converter, sim-plifying the control circuit. Approaches such as [6], [7] eliminatethe voltage sensor in the input or output voltage, [8] uses thediode current as a variable to compute the duty cycle, and [9]and [10] avoid the use of an ADC chip in the current acquisition,but a current sensor is used. In [11], the current sensor is avoidedto detect zero current in a critical mode (CRM) boost converter.

In continuous conduction mode (CCM) boost PFC convert-ers, the most recent works with current sensorless solutions toobtain power factor correction are [12]–[17]. A digital PFC us-ing analog comparators and no ADC is presented in [12], whilea predictive duty-cycle is presented in [13] and [14] with animplementation in a DSP and in an FPGA, respectively. In [15]and [16], the current loop is avoided with a sinusoidal inputvoltage, while the same approach is improved in [17] underdistorted input voltage.

With the aforementioned controllers, high power factor valueand low THD of the input current (THDi) are achieved in thevoltage and power ranges presented for each reference in Fig 3(according to the experimental results presented in each work).Furthermore, the influence of the parasitic elements and theeffects of the nonidealities are not analyzed in detail. The greenarea represents the goal of this study, which corresponds withthe typical range of commercial analog ICs [18] for CCM PFCcontrollers (universal input voltage range and wide output powerrange).

This study is based on the input current rebuilding con-cept [19]–[22]. The variable volt-seconds (vsL ) across the in-ductor is estimated in each switching period, and the small error(current estimation error) accumulated per switching period overthe half-line cycle causes current distortion. The effect of theswitching delays is presented in [19]. One of the aims of thisstudy is to find a good tradeoff between resolution and speed, inwhich the current estimation error is cancelled using a twofoldstrategy:

1) a fast and coarse feedforward control to compensate au-tomatically the effect of the switching delays, presented

Fig 4. (a) Basic model of the boost converter and (b) Boost converter currentestimator.

in the previous work [19], measuring these delays everyswitching period;

2) a fine low-frequency feedback control, with high resolu-tion, to compensate automatically the current estimationerror.

The error compensation strategy is found in the study andmodeling of the influence of the different sources of currentestimation error such as the parasitic elements and errors in thevoltage acquisition data. This analysis is the second objectiveof the study.

This paper is organized as follows. In Section II, a briefoverview on input current estimation without a current sensoris provided. Section III shows the estimation mismatch due toerrors in the capture of voltage data, which are due to tolerancesand offsets in the voltage measurement circuits (resistors, ADC,etc.), the differences between the estimated inductance and thereal one, the influence of the parasitic elements, and delay in thedrive signal. The digital compensation technique of the errors isdescribed in Section IV, supported with simulation results. Anauxiliary circuit for DCM detection is presented in Section Vand applied to a novel feedback corrector of the estimation errorin Section VI. Experimental results are presented in Section VIIfor a 1-kW boost converter operating over a wide range of inputvoltage and load power.

II. DIGITAL CURRENT ESTIMATION WITHOUT

CURRENT SENSOR

Fig. 4(b) shows the simulation block diagram of the currentestimator implemented in a digital device, which represents abehavioral model of the boost converter illustrated in Fig. 4(a).The input and output voltages of the converter (vg and vo) are ap-plied to the inductance L, and define the real input current (ig ),so they have to be measured and quantized to estimate the cur-rent value in the digital controller. The hardware scheme of the


TABLE ILIST OF CORRESPONDENCE BETWEEN THE ANALOG

AND THE DIGITAL VARIABLES

TABLE IIEXPRESSION OF THE CURRENT RIPPLE FOR THE REAL

AND REBUILT INPUT CURRENT

current estimator is presented in [19]. Digital input and outputvoltage data (v∗

g and v∗o ) have an LSB resolution (expressed in

volts per bit) represented by qg and qo , respectively, and given by

qg =vg

v∗g

(V

bit

); qo =

vo

v∗o

(Vbit

). (1)

The voltage across the inductor is defined by the power con-verter states (ON-state and OFF-state), designated in the currentestimator by the on–off signal that drives the power switch Q.The result is in an estimated inductor voltage v∗

L and a quan-tized rebuilt inductor voltage vL,reb . The ON and OFF timesare initially known because they are generated by the controller.The bin q represents the LSB resolution defined by the designer.Ideally, qg = qo = q, but a real analog-to-digital conversioncauses a small difference between them

qg = q (1 − εg ) ; qo = q (1 − εo) (2)

where εg and εoare the per unit error of the input and outputanalog-to-digital conversions, respectively.

Theoretically, the inductance L is known, but tolerances, tem-perature, switching frequency, and the inductor current cause adifference between the estimated inductance (Lest) and the realone that depends on the core material. The inductor is modeledas an integrator with a gain equal to the inverse of its induc-tance, whose output is the digitally rebuilt (estimated) inputcurrent ireb . This signal ireb is used in the PFC current loopinstead of the real ig .

Table I shows the correspondence between the analog vari-ables (actual variables in the converter) and their correspondingdigitally estimated variables expressed in the same units. Thesevariables define ig and ireb according to the expressions pre-sented in Table II, where Δig and Δireb are the peak-to-peakcurrent ripple of the real and rebuilt input current, respectively.

If the analog and digital variables are equivalent, with vg =v∗

g q, vo = v∗oq, being q = qg = qo , L = Lest and ton = t∗on , then

both currents agree (ireb = ig ) when neglecting quantizationeffects. The waveforms are as depicted in Fig. 5, where ireb [k]represents the estimated current in the clock cycle k, and i−reb [j]

Fig. 5. Digital signal ireb [k], compared with the analog real input current ig ,under ideal conditions. The on-off signal is the output of the digital device andvL the analog inductor voltage.

and i−g (jTsw ) are the estimated and real current at the endof the switching cycle j (valley values), respectively. In thissituation, there is no current estimation error, defined as thedifference between ig and ireb , ierror = ig − ireb , and thereforeireb corresponds with an accurate quantization of ig .

At the beginning of the line voltage semicycle, ireb = ig = 0.Since the input current is not measured, the line zero crossingsare the only points where the real current is known. Small errorsin the digital variables compared with the analog (see Table I)cause a current estimation error in each switching period j. Thedominant current estimation errors are due to:

1) voltage data errors due to the tolerances of the voltagedividers, noise, offset, quantization process, or nonlin-earity of the ADCs (vg �= v∗

g q and/or vo �= v∗oq and/or

qg �= qo �= q);2) the difference between the estimated inductance (Lest)

and the real one (L);3) the influence of the parasitic elements (RL,Ron , RD ,

VD );4) delays in the drive signals (ton �= t∗on).All of these errors are described separately in Section III,

where the current estimation error caused by these differentsituations is modeled.

III. MODELING THE CURRENT ESTIMATION ERRORS

To simulate the effect of the different causes of error andperform a first validation of the model, the system has beenmodeled with the switching converter in PLECS and the behav-ioral control algorithm in Simulink as shown in Fig. 6.

The real input current ig and estimated input current ireb aresolved for CCM operation according to Fig. 7 and the currentestimator presented in Figs. 4 and 6. Analytical expressionsat the end of each switching period j, i−g (jTsw ) and i−reb [j]respectively, are given by

i−g (jTsw ) = i−g ((j − 1) Tsw ) +Tsw

L{vg [j] − vo [j] d′ [j]}

(3)

i−reb [j] = i−reb [j − 1] +Tsw

L

{vg [j] q

qg− vo [j] q

qod′ [j]

}(4)


Fig. 6. Simulations Blocks in Simulink with PLECS toolbox. (Bottom)PLECS subcircuit in Simulink with the current estimator. (Top) Boost converterin PLECS with a block to simulate the drive signal delays.

Fig. 7. Digital estimated current ireb [k] compared with the analog real inputcurrent ig under errors in data capture voltage across the inductance whenqg �=qo �=q. The on-off signal is the output of the digital device and vL theanalog inductance voltage.

where (1 − d[j]) is notated as d′[j], and constant voltage valuesare assumed over each switching period j. The current esti-mation error, defined as ierror = ig − ireb , is evaluated after nswitching periods, as the accumulation of the difference between(3) and (4)

ierror [n]=Tsw

L

j=n∑j=0

{vg [j]

(1 − q

qg

)− vo [j]

(1 − q

qo

)d′[j]

}.

(5)The error from (5) can be expressed as a function of ireb

ierror [n] = ireb [n] ×(

qg

q− 1

)

+Tsw

L

j=n∑j=0

{vo [j]d′[j]

(qg

qo− 1

)}(6)

Fig. 8. Steady-state simulated waveforms with the Simulink/PLECs model ofthe system with Vg = 230 Vrm s , Vo = 400 Vdc , Po = 640 W, fsw = 72 kHz,L = 1 mH, and C = 220 μF, when q = 0.4617 V/bit, qg = 0.4620 V/bit,qo = 0.4624 V/bit (Top) Real and estimated currents. (Bottom) current errorobtained from the model and from (6).

Fig. 9. Digital estimated current ireb compared with the analog real inputcurrent ig , when the estimated inductance value Lest is higher than the realL. The on-off signal is the output of the digital device, and vL the inductancevoltage.

and it is possible to calculate the value of the real input currentafter n switching periods as

ig [n] = ireb [n] × qg

q+

Tsw

L

j=n∑j=0

{vo [j]d′[j]

(qg

qo− 1

)}.

(7)Expressions (6) and (7) have two different terms. The first

term defines a current proportional to ireb , which is the variablecontrolled by the PFC controller and ideally has a sinusoidalshape. Therefore, the first term does not create distortion (har-monics) in ig . The second term is not sinusoidal and nonzerowhen qg �= qo , causing current distortion and decreasing thepower factor. Fig. 8 shows the simulation of ireb and ig atthe top of the figure, and the simulated current error ierror,simcompared with the modeled error defined by (6), ierror , whenqg �= qo �= q, at the bottom.

The second cause of error analyzed in this study is due to thedifference between the real inductance (L) and the estimatedone Lest . The behavior of the sensorless boost converter is il-lustrated in Fig. 9 in the switching periods j and j + 1 when L


Fig. 10. Steady-state simulated waveforms with the Simulink/PLECS model of the system with Vg = 230 Vrm s , Vo = 400 Vdc , Po = 640 W, fsw =72 kHz,and C= 220 μF, when q =qg =qo for (a) L = 1 mH and Lest = 1.8 mH, and (b) nonlinear inductance L = 1.5–0.147ig [mH], Lest = 1.0 mH.

�= Lest and qg = qo = q, i.e., considering the inductance erroronly.

According to Fig. 9, the current values are defined at the endof the switching period j by

i−g (jTsw ) = i−g ((j − 1) Tsw ) +Tsw

L{vg [j] − vo [j] d′ [j]} (8)

i−reb [j] = i−reb [j − 1] +Tsw

Lest{vg [j] − vo [j] d′ [j]} . (9)

Comparing (8) and (9), the relation between ireb and ig yieldsto expressions (10) and (11) for ig and ierror , respectively. As ithas been addressed before, ireb is the variable controlled by thePFC control algorithm, so it has a sinusoidal shape (proportionalto the input voltage). Considering L constant over the line cycle,ig is sinusoidal too, and no current distortion appears despite thecurrent estimation error, as it is presented in Fig. 10(a). Fig. 10(b)shows the current waveforms with a nonlinear current dependentinductance L(i) [23], as is the case of one of the inductors builtwith a soft-saturation core used in the experimental results. Themodel of soft-saturation inductor used in this study is presentedin [24], which considers the permeability dependence on themagnetizing force

ig = ireb × Lest

L(10)

ierror = ireb ×(

Lest

L− 1

). (11)

Up to this point, it can be seen that the difference betweenqo and qg causes current distortion and decreases the PF valuebecause it means a difference between the V/bit resolution in theON-state and in the OFF-state, and consequently, a differencein the A/bit also. To analyze the behavior of the PFC controllerwith the current estimator, it is assumed that q = qg and Lest =L, and the current error accumulated in n switching periods isdefined by

ierror [n] =Tsw

L

j=n∑j=0

{vo [j]d′[j]

(qg

qo− 1

)}. (12)

Fig. 11. Boost converter diagram with parasitic elements.

The last cause of current distortion analyzed in this study isthe influence of the parasitic elements. Fig. 11 shows the modelof the boost converter with parasitic elements, RL being theeffective series resistor of the inductor, VD and RD the forwardvoltage at zero current and the ON-state resistor of the powerdiode, and Ron the MOSFET ON-resistance.

The controller varies the duty cycle d such that the averageinput current over the switching period is 〈ig 〉 = vg/Re , wherethe emulated resistance Re is chosen by the controller to obtainthe desired dc output voltage. By solving the volt-second balancein L, assuming the small-ripple approximation

〈vg 〉 − 〈vo〉 (1 − d) = RL 〈ig 〉 + Ron 〈ig 〉 d

+ RD 〈ig 〉 (1 − d) + VD (1 − d). (13)

Substituting〈ig 〉 = vg/Re in (13), it is possible to solve thecommand d given by the PFC controller to obtain a sinusoidalcurrent [25]

d =vg − (RL + RD ) vg

Re− VD − vo

(Ron − RD ) vg

Re− VD − vo

. (14)

Defining 〈vpar〉as the average voltage drop across the parasiticelements, in each switching period

〈vpar〉 = −RL 〈ig 〉 − Ron 〈ig 〉 d − RD 〈ig 〉 (1 − d)

− VD (1 − d) = vo (1 − d) − vg (15)

and substituting (14) into (15), we get

〈vpar〉 = vg

(vo (Ron + RL − Re)

vg (Ron − RD ) − (VD + vo) Re− 1

). (16)


Fig. 12. Simulated current waveforms without consideration of the parasiticelements influence. (Top) Real and rebuilt input current. (Bottom) Simulatedcurrent estimation error.

Fig. 13. Digital signals estimated current ireb [k] compared with the analogreal input current ig , with on-time modification Δton for the switching periodsj and j+1. The on-off signal is the output of the digital device and the inductorvoltage, vL .

Fig. 12 shows 〈ig 〉 and 〈ireb〉 waveforms when the esti-mated volt-seconds across the inductor is lower than the actualone due to the noncompensation of the parasitic effects withVg = 230 Vrms , Vo = 400 Vdc , Po = 640 W, fsw = 72 kHzand reactive components L = 1 mH and C = 220 μF. The par-asitic elements are RL = 0.3 Ω, RD = 0.2 Ω, VD = 0.6 V, andRon = 0.18 Ω. These values are obtained from the datasheetsof the RHRP860 Fairchild Power Diode and the IRFP27N60KInternational Rectifier Power MOSFET, the switching devicesused in the laboratory prototype. It can be observed that thecurrent estimation error, ig is not sinusoidal, with PF = 0.770and THDi = 44%.

An additional error in the estimated volt-seconds applied tothe inductor is caused by time errors and is addressed in [19],where it is concluded that they are mainly due to the differencebetween the ON-time applied in the real converter (ton) andthe estimated ON-time, t∗on . The effect of this time-error isillustrated in Fig. 13, defining Δton [j] = ton [j] − t∗on [j] as the

Fig. 14. Auxiliary circuit used to adapt the drain-to-source voltage as a digitalsignal. Comparison with the on-off signal and the drive signal’s delays Δton -offand Δton -off .

on-time modification in the switching period j

ierror [n] =j=n∑j=1

vo [j]L

Δton [j] . (17)

IV. DIGITAL CORRECTION OF THE CURRENT

ESTIMATION ERRORS

Two compensation strategies, working at the same time,are presented in this section. The first one is time compensa-tion, meaning an improvement in comparison with the previ-ous work [19]. The ON-time error Δton [j] is measured everyswitching period, and it is compensated by accounting for itwhen the digital circuit calculates the required on-time in ev-ery switching period. In this case, as is presented in [20], anauxiliary circuit, which includes a resistor divider and a signaldiode, is used to detect the drain-to-source voltage drop acrossthe power MOSFET and obtain the digital signal (v∗

ds) whichindicates the real ON–OFF transitions in the boost converter, asis presented in Fig. 14.

The digital controller compares the on–off signal with v∗ds

to measure the ON-time modification every switching period(Δton [j] = Δton−off [j] − Δtoff−on [j]) in terms of clock peri-ods of the digital circuit.

This strategy constitutes a coarse and fast feedforward com-pensation of the volt-seconds error caused by a time error.The resolution of the Δton measurement depends on the clock-period of the digital device and the minimum error is ±Tclk /2[22]. For the boost parameters presented before and a 10 ns(±Tclk /2 = ±5 ns) clock period, the current error accumulatedin half line cycle, i.e., nu switching periods, is ierror [nu ] =±1.40 A, where nu =fsw /(2fu ). The clock-frequency is a bot-tleneck in this controller because it fixes the minimum Δtonvalue. Higher fsw leads to higher current estimation error [19].

A second error compensation strategy is proposed, based onthe modification of the current estimator block presented inFig. 4. The new approach is presented in Fig. 15. It consists ofintroducing a new digital signal vdig , which modifies the outputvoltage signal v∗o in the current rebuilding algorithm.

Assuming q = qg , the signal vdig means a modification of vL

in each switching period given by (18)

〈vdig〉 = −vdigqg (1 − d) . (18)


Fig. 15. Behavioral model of the modified current estimator.

Fig. 16. Simulation results with the proposed compensation setting vdig =β/qg with Vg = 230 Vrm s , Vo = 400 Vdc , Po = 640 W, fsw = 72 kHz andreactive components L = 1 mH, and C = 220 μF. The values of the parasiticelements are RL = 0.3 Ω, RD = 0.2 Ω, VD = 0.6 V, Ron = 0.18 Ω.

If it is considered only the effect of the parasitic elements, thevalue of vdig that compensates this effect is obtained comparing(16) and (18) to assure 〈vpar〉 = 〈vdig〉, resulting in

vdig =1qg

vo (Ron + RL ) + VD Re − vg (Ron − RD )Re − (Ron + RL )

(19)

β =Vo (Ron + RL ) + VD Re − Vg (Ron − RD )

Re − (Ron + RL ). (20)

Expression (19) describes a waveform almost constant overthe line cycle. Neglecting the output voltage ripple vo ≈ Vo , andconsidering Ron ≈ RD , the new signal can be approximated asvdig = β/qg , where β is a constant defined by (20). Fig. 16shows the simulation of the error compensation using vdig withVg = 230 Vrms , Vo = 400 Vdc , Po = 640 W, fsw = 72 kHzand reactive components L = 1 mH, and C = 220 μF. Theparasitic elements are RL = 0.3 Ω, RD = 0.2 Ω, VD = 0.6 V,and Ron = 0.18 Ω. The resulting power factor is 0.997 withTHDi = 1.78%, improving the results obtained in Fig. 12.

With the vdig signal added to the current estimator, not onlythe influence of the parasitic elements is compensated but alsothe current error due to qg �= qo . Note that both sources of errorcause equivalent ierror shape.

Fig. 17. Auxiliary circuit for the actual DCM detection and waveforms.(a) Hardware architecture. (b) Circuit waveforms.

V. DISCONTINUOUS CONDUCTION AUXILIARY

DETECTION CIRCUIT

Accumulated current estimation error over the half-line cyclecauses input current distortion, decreasing the power factor. Asit has been shown in Figs. 8 and 12, when it happens the timein which discontinuous conduction mode (DCM) occurs is aparameter that enables the detection of discrepancy betweenireb and ig .

An auxiliary circuit, capable of detecting the converter modeof operation (CCM or DCM) is presented in this study. Fig. 17shows the hardware architecture(see Fig. 17(a)) and the circuitbehavior (see Fig. 17(b)). A digital signal DCMig , indicates theconverter operation mode by its logic level (e.g., DCMig = “0”for CCM operation and DCMig = “1” for DCM operation). Thiscircuit, similar to the one described in [26] and [27], comparesthe output voltage vo , with the MOSFET drain-to-source voltagevds (previously used to measure the drive signal delays), adaptedwith two equal resistor dividers (Rds1 = Ra , Rds2 = Rb ). InCCM operation, vds > vo (due to the influence of the parasiticelements) during the whole OFF-time, but this is not true inDCM operation. Drain-to-source voltage vds , adopts a valueclose to the input voltage as soon as input current ig reacheszero. But the inherited parasitic elements of the power switchescause oscillations in the drain-to-source voltage around vg [28].


Fig. 18. Experimental waveforms. Input voltage vg , real input current igwaveforms and digital signals DCMig and DCMireb for: (a) eDCM < 0, thenireb > ig , and (b) for eDCM > 0and then ireb < ig .

The comparator output signal x1 , is registered at the beginningof the switching period using the on–off signal rising edge,which is internally available in the digital device. If x1 is highat this sample instant, the boost converter is operating in DCM(DCMig = “1”). Conversely, if sampled x1 is low, the converteris operating in CCM (DCMig = “0”).

In the case of the digitally rebuilt input current ireb , thesignal DCMireb , indicates whether ireb = 0 at the beginningof the switching period. DCM operation is estimated whenDCMireb = “1” and CCM operation is estimated whenDCMireb = “0.”

VI. HIGH RESOLUTION FEEDBACK LOOP

ANALYSIS AND STABILITY

Recent works [12]–[17], [19] avoid the input current mea-surement and propose a PFC digital control that includes themeasurement of the parasitic elements (RL, VD ,RD ,Ron) andapplies a duty cycle command d, according to these elements, orsimply neglects their influence. But parasitic elements influencechange with the temperature, frequency, and the componentsused in the PFC converter. It can be observed that in thesepreviously proposed solutions for sensorless PFCs use high in-ductance values and low switching frequencies in comparisonwith the state-of-the-art of CCM PFCs that include a currentsensor.

The estimated input current ireb , presents a DCM time, T rebDCM ,

while ig has a different DCM time, T gDCM . A distortion in ig

leads to T gDCM �= T reb

DCM reducing the power factor. The compen-sator for current estimation error captures DCMig and DCMireband measures and compares T g

DCM with T rebDCM to obtain the

DCM time error eDCM ,

eDCM = T rebDCM − T g

DCM . (21)

Thus, an indirect measurement of the current estimation er-ror is obtained by eDCM . The output voltage loop assures thedesired output voltage vo , and depending on the vdig value, twodifferent situations, shown in Fig. 18, can occur. If eDCM < 0(see Fig. 18(a)), then ig < ireb, and it is necessary to increasevdig to match DCM times. On the other hand, in Fig. 18(b), the

Fig. 19. Block diagram of the proposed controller.

situation with eDCM > 0 is shown with ig > ireb , where it isnecessary to decrease vdig .

To obtain a universal PFC controller that compensates all thecurrent estimation errors, the proposed the new feedback loopadjusts vdig to match T reb

DCM = T gDCM . A block diagram of the

proposed control loop is presented in Fig. 19. The DCM timeerror eDCM is the input of a compensator, which modifies itsoutput signal, vdig , until the DCM times match, i.e., eDCM = 0.

At the same time, this new feedback loop compensates withhigh resolution for the estimation errors not compensated by thefeedforward strategy, due to the ±Tclk /2 resolution of the Δtonmeasurement (addressed in Section IV). In this study, 10-bitADCs are used and vdig is a 14-bit signal. Therefore, the outputvoltage signal used to estimate the input current (v∗

o2 in Fig. 15)has 14 bits (4 LSB added). The current error for a given vdig isdefined by

ierror [n] =Tsw

L

j=n∑j=0

{(qg vdig − β) d′[j]} (22)

which is zero if vdig = β/qg . Due to the finite resolution, the dig-ital controller sets a value vdig = β/qg ± 1 LSB. This ±1 LSBuncertainty in vdig represents an accumulated current error in thelast switching period nu of the half line cycle of, ierror [nu ] =±0.15 A, with the parameters previously presented. The newfeedback loop has a resolution of one order magnitude higherthat the feedforward compensation, resulting in ierror [nu ] =±1.40 A, limited by the digital device clock-period as presentedin detail in [22].

The output voltage loop in a PFC controller has a typicalbandwidth around fc = 5–10 Hz to set vo according to a ref-erence. To not interfere with this, the DCM time compensationloop has a lower bandwidth, using a sample period equal to Ts =1/fc . With this assumption, a complete derivation of the modelis presented in detail in [30], where the model of the system(plant) is given by

T gDCM(s)vdig (s)

= − 1Γ

z−1 with Γ =VoL (πfu )2

R

(2

M 2g

− 1K

)

(23)and Mg = Vg

√2/Vo and K = 2fswL/R. Using a PI compen-

sator, KPI/(z − 1), the Jury stability criterion defines the rangeof values of KPI for a stable system as

0 > KPI > −Γ (24)


Fig. 20. (a) Schematic diagram of the Boost PFC Converter. (b) Laboratoryprototype.

Fig. 21. Experimental results: ON-time (top) and the duty cycle modification(Δton ) due to the drive signal delays acquisition (bottom) over the half linecycle.

VII. EXPERIMENTAL RESULTS

A 1-kW boost converter with the proposed digital feedbackloop and feedforward time compensation has been built andtested to illustrate the behavior of the auxiliary circuit that cap-tures the drain-to-source voltage and the performance of the

Fig. 22. Experimental results for the DCM condition detection circuit for thereal input current.

Fig. 23. Comparison of the harmonic content with the limits defined by theStandard IEC 61000-3-2 for Classes A, C, and D.

TABLE IIIPOWER FACTOR AND THDI FOR DIFFERENT CONDITIONS

error compensation. The circuit scheme and a picture, whichcorrespond to the experimental prototype, are shown in Fig. 20.In comparison with traditional digital PFC controllers, the cur-rent sensing circuit is replaced here by two resistor dividers, asignal diode and a comparator. The output voltage reference is400 Vdc with an input voltage rangingfrom 85 to 250 Vrms


Fig. 24. Experimental results. (a) Vo = 400 Vdc , L1 = 1 mH and RL 1 = 0.25 Ω. Left: Vg = 230 Vrm s (50 Hz), Pg = 970 W. Right: Vg = 85 Vrm s (60 Hz),Pg = 320 W. (b) Vo = 400 Vdc , L2 = 1.5 mH and RL 2 = 0.35 Ω. Left: Vg = 230 Vrm s (50 Hz), Pg = 970 W. Right: Vg = 85 Vrm s (60 Hz), Pg = 320 W.

Fig. 25. Experimental results. eDCM time evolution under a 970 to 640 Wload step down.

(universal input voltage range). The switching frequency is72 kHz. To demonstrate the universal nature of the proposedapproach, two different inductors were built and the results wereachieved without modifying any parameter of the digital con-troller. The first inductor was built with an RM12-3C90 core, re-sulting in inductance L1 = 1 mH and RL1 = 0.25 Ω. The secondinductor was built with a soft saturation Kool mμ core 77071.In this case, the inductance L2 = 1.5 mH and RL2 = 0.35 ω.Both inductors were measured with a HP 4284A precision LCRmeter at 75 kHz and 5 A DC bias current. The output capacitorC = 220 μF, the MOSFET, and diode used to built the prototypeare IRFP27N60K from International Rectified with Ron = 0.18

Ω and RHRP860 Power Diode from Fairchild with VD = 0.6 Vand RD = 0.2 Ω. The laboratory prototype was built to workunder wide voltage and current ranges and shows the behaviorof the controller under different operating conditions withoutchanging the components. The digital PFC controller and thefeedback loop were described in VHDL and implemented in aXilinx XC3S200E field programmable gate array (FPGA). A“nonlinear-carrier” (NLC) controller [29] was used in this caseas PFC controller technique, controlling the rebuilt input currentireb . A second order ad hoc sigma delta ADC [19] was used tosample the output voltage and a commercial TLV1572 serial10-bit ADC was used for the input voltage.

The ON-time and the ON-time modification (Δton ) due to thedrive signal delays over the half-line cycle are shown in Fig. 21for different loads (320, 480, and 970 W). The delay is a functionof the MOSFET gate resistance, drain current, and the MOSFETparasitic elements. With the auxiliary circuit shown in Fig. 14,Δton is measured each switching period and the active time ofthe drive signal is compensated instantaneously [19], [20].

Fig. 22 shows the main waveforms of the DCM conditiondetection circuit for the real input current with Rds1 = Ra =1.2 MΩ and Rds2 = Rb = 9.31 kΩ. The digital signal, DCMigchanges to “1” when the first DCM oscillation in the drain-to-source voltage occurs. Experimental and simulated waveformsare in good agreement as shown in Fig. 17.

The experimental results in steady-state operation are shownin the waveforms of Fig. 23 for different input voltages (85Vrms – 60 Hz and 230 Vrms – 50 Hz), output power and bothinductances (L1 and L2). It is observed that DCM times arematched and sinusoidal input current is achieved. Power factor


and total harmonic distortion of the input current (THDi) valuesare listed in Table III for input voltage ranging from 85 Vrms –60 Hz to 250 Vrms – 50 Hz at different output power, fulfillingthe goal set in Fig. 3. A comparison of the harmonic content atnominal conditions (230 Vrms – 50 Hz, 1 kW) with the limitsdefined by IEC 61000-3-2 for Classes A, D, and C is shown inFig. 23.

Measured THDi values are a little lower with L1 than withL2 . This is caused by the current dependent inductance of theinductor built with a soft saturation core [23]. The aim of usingthis inductance in the proposed controller is to show the behaviorof the controller under two different conditions. The use ofL2 on one hand introduces a nonlinear behavior that produceshigher current distortion as the current increases and on theother hand keeps the CCM operation for a higher load range.Despite this aspect, the experimental results demonstrate highpower factor for all the tested conditions. It is important to notethat the digital controller has not been re-tuned to operate underthe different conditions. This shows the universal nature of theapproach presented in this study with switching frequency andinductance similar to traditional and commercial analog PFCdesigns.

The time evolution of the eDCM value under a load stepdown (970–640 W) is shown in Fig. 24. After the error valuepeak which occurs when the load step is applied, the fine errorfeedback loop modifies vdig , compensating the DCM times errorreaching a steady-state condition with eDCM = 0 in around6 s. During the transient time with eDCM �= 0 not excessivedeterioration of the power factor occurs due to the feedforwardcompensation of the estimation error. The value of Γ = 60.3and gain of the PI controller has been settled to KPI = −1.

VIII. CONCLUSION

A universal current sensorless controller for Boost PFC stagesoperating in CCM has been presented. The current is digitallyrebuilt in a digital device and this digital signal is used in the PFCcurrent loop. Making the most of the digital control capabilities,the traditional current sensing analog circuit is substituted bya simpler circuit (two resistor dividers and a comparator) thatdetects the DCM condition in the input current by translatingthe pulsated drain-to-source voltage into a digital signal, search-ing for the best tradeoff between the circuit complexity versusresolution and speed response. With this circuit, an indirect mea-surement of the current distortion is obtained by comparing theactual and estimated DCM times.

The effect of the parasitic elements in the input current es-timation for sensorless PFC boost digital controllers operatingin CCM has been analyzed. In this case, the current estimationis carried out by measuring the input, output, and MOSFETdrain-to-source voltages.

The error between the estimated and actual DCM periodsclose to the zero crossing of the input voltage is a key variableto accurately correct the error in the estimation of the input cur-rent and the consequent distortion. An auxiliary circuit detectsDCM condition in the input current comparing drain-to-sourcevoltage with the output voltage during the MOSFET OFF-time.

The single digital signal acquired from the MOSFET drain-to-source voltage drop is used by both the feedforward and feed-back compensators. The feedforward one represents a coarsecompensation of current estimation errors due to time delays.And the new feedback loop generates a constant digital signalto compensate current estimation errors, modifying the outputvoltage measurement used to estimate the input current, andminimizes this DCM time error. This feedback loop autotunesthe value of the digital signal when the converter operates in awide load or voltage range with a high resolution, resulting inan average real input current proportional to the input voltagein each switching period. A universal Boost PFC digital con-troller is achieved without current measurement, so in the pointof view of the designer the complexity of the PFC controllerdecreases. With this feedback loop, parasitic element values donot need to be measured and are compensated for automatically,representing a step forward in comparison with the previousworks about PFC sensorless controllers. The prototype has beentested with two different inductors (linear and nonlinear), andthe experimental results show, in both cases, high power fac-tor with reliable performance under different load and voltageconditions.

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Victor Manuel Lopez (S’10) was born in Tor-relavega, Cantabria, Spain, in 1985. He received theElectronics and Control Engineering degree fromthe University of Cantabria, Santander, Spain, in2009, where since then he has been working towardthe Ph.D. degree in the Department of ElectronicsTechnology, Systems and Automation Engineering(TEISA).

From June to September 2012, he was a Visit-ing Scholar in the Colorado Power Electronics Cen-ter (CoPEC), University of Colorado at Boulder, and

from September to December 2012 in the Utah State University Power Labo-ratory, at Logan, Utah. Both periods with the Prof. Regan Zane as advisor. Hisresearch interests include design, modeling, and digital control of topologies forac–dc converters and for resonant inverters.

Mr. Lopez received the IEEE/IEL Electronic Library Award in 2009.

Francisco J. Azcondo (S’90–M’92–SM’00) re-ceived the electrical engineering degree from the Uni-versidad Politecnica de Madrid, Madrid, Spain, in1989, and the Ph.D. from the University of Cantabria,Spain, in 1993.

From 1995 to 2012, he has been an AssociateProfessor in the TEISA Department, ETS II y T, Uni-versity of Cantabria, Cantabria, Spain, where he hasbeen a Professor since 2012. He has been a VisitingResearcher at the Department of Electrical, Com-puter, and Energy Engineering, University of Col-

orado, Boulder, CO, USA, from Feberuary to August 2004 and 2010, the De-partment of Electrical Communication Engineering, the University of Toronto,ON, Canada, during the summer 2006, and the Power Electronics Lab (UPEL)at Deptartment Electrical Communication Engineering, Utah State University,Logan, UT, USA, from June to September 2013. Since Feberuary 2004, he isSpecial Member (appointed as graduate faculty) at the Department of Electrical,Computer, and Energy Engineering, University of Colorado Boulder, renovateduntil spring 2017. He has been the Chair of the IEEE IES – PELS SpanishJoint Chapter from September 2008 to June 2011. His research interests includemodeling and control of switch-mode power converters and resonant converters,digital control capabilities for SMPS, current sensorless control for power factorcorrection stages and applications such as outdoor lighting, electrical dischargemachining, and arc welding.

Angel de Castro ( M’08) was born in Madrid, Spain,in 1975. He received the M.Sc. and the Ph.D. de-grees in electrical engineering from the UniversidadPolitecnica de Madrid, Madrid, Spain, in 1999 and2004, respectively.

He has been an Associate Professor in the Uni-versidad Autonoma de Madrid since 2010, and asAssistant Professor from 2006 to 2010. Previously,he was an Assistant Professor in the Universidad Po-litecnica de Madrid since 2003. His research interestsinclude digital control of switching mode power sup-

plies, power factor correction, and field programmable gate arrays.

Regan Zane (SM’07) received the Ph.D. degree inelectrical engineering from the University of Col-orado, Boulder, CO, USA, in 1999.

He is currently a USTAR Professor in the De-partment of Electrical and Computer Engineeringat Utah State University (USU), Logan, UT, USA.Prior to joining USU, he was a faculty member atthe Colorado Power Electronics Center, University ofColorado-Boulder, from 2001 to 2012, and ResearchEngineer at GE Global Research Center, Niskayuna,NY, USA, from 1999 to 2001. He has recent and on-

going projects in bidirectional power converters for dc and ac micro-grids, highstep-down power converters for dc distribution systems such as high efficiencydata centers, advanced battery management systems (BMS) for electric vehicles,LED drivers for lighting systems and low power energy harvesting for wirelesssensors.

Dr. Zane received the NSF Career Award in 2004 for his work in energyefficient lighting systems, the 2005 IEEE Microwave Best Paper Prize for hiswork on recycling microwave energy, the 2007 and 2009 IEEE Power Elec-tronics Society Transactions Prize Letter Awards for his work on modeling ofdigital control of power converters and the 2008 IEEE Power Electronics So-ciety Richard M. Bass Outstanding Young Power Electronics Engineer Award.He received the 2006 Inventor of the Year, 2006 Provost Faculty Achievement,2008 John and Mercedes Peebles Innovation in Teaching, and the 2011 HollandTeaching Awards from the University of Colorado. He currently serves as As-sociate Editor for the IEEE Transactions on Power Electronics, Letters, and asthe Publicity Chair for the IEEE Power Electronics Society.

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