UNITED STATES PATENT AND TRADEMARK...

UNITED STATES PATENT AND TRADEMARK OFFICE

BEFORE THE PATENT TRIAL AND APPEAL BOARD

MAXLINEAR, INC. Petitioner

v.

CRESTA TECHNOLOGY CORPORATION Patent Owner

CASE: IPR2015-00594

Patent 7,265,792

Title: Television Receiver for Digital and Analog Television Signals

PETITION FOR INTER PARTES REVIEW OF

U.S. PATENT NO. 7,265,792

UNDER 35 U.S.C. § 312 AND 37 C.F.R. § 42.104

Mail Stop PATENT BOARD U.S. Patent Trial & Trademark Office P.O. Box 1450 Alexandria, VA 22313-1450

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TABLE OF CONTENTS

I. COMPLIANCE WITH FORMAL REQUIREMENTS .................................. 1

A. Grounds for Standing (37 C.F.R. § 42.104(a)) ..................................... 1

B. Real Parties-In-Interest (37 C.F.R. § 42.8(b)(1)) .................................. 1

C. Related Matters (37 C.F.R. § 42.8(b)(2)) .............................................. 1

D. Counsel and Service Information (37 C.F.R. § 42.8(b)(3)-(4)) ............ 2

E. Statement of Precise Relief Requested ................................................. 4

II. REASONABLE LIKELIHOOD TO PREVAIL ............................................. 4

III. IDENTIFICATION OF CHALLENGE .......................................................... 4

A. Prior Art Publications ............................................................................ 4

B. Brief Statement of Grounds for Challenge ............................................ 6

1. Grounds are Not Redundant of the Original Prosecution ................ 8

2. Grounds are Not Redundant of Other Petitions for IPR .................. 9

3. The Grounds in the IPR2015-00626 Petition ................................ 10

IV. INVALIDITY OF THE ‘792 PATENT ........................................................ 11

A. Introduction ......................................................................................... 11

B. Prosecution History of the ‘792 Patent ............................................... 12

C. Person of Ordinary Skill in the Art ..................................................... 15

V. CLAIM CONSTRUCTION .......................................................................... 15

A. Summary of Claim Terms Construed ................................................. 16

B. “RF signal” .......................................................................................... 16

C. “format” ............................................................................................... 17

D. “video and audio baseband signals” .................................................... 17

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E. “signal processor” ................................................................................ 18

VI. DETAILED EXPLANATIONS OF THE CHALLENGES .......................... 19

A. Ground 1: Claims 1, 2, 4, 5, 11 and 24-29 are anticipated by Favrat ................................................................................................... 20

B. Ground 2: Claim 3 is obvious over Favrat in view of Arambepola ......................................................................................... 29

C. Ground 3: Claim 6 is obvious over Favrat in view of Yang ............... 30

D. Ground 4: Claim 7, 8, 9 and 12 are obvious over Favrat in view of Wilkie .............................................................................................. 32

E. Ground 5: Claim 10 is obvious over Favrat in view of Vorenkamp .......................................................................................... 35

F. Ground 6: Claims 13-15 and 18 is obvious over Favrat in view of Oku .................................................................................................. 37

G. Ground 7: Claims 16, 17 and 19 are obvious over Favrat in view of Oku ......................................................................................... 44

H. Ground 8: Claims 20-23 are obvious over Favrat in view of Oku and further in view of Eglit and Wilkie ....................................... 46

VI. CONCLUSION .............................................................................................. 52

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EXHIBIT LIST

Exhibit 1101 U.S. Patent No. 7,265,792 (“the ‘792 patent”). Exhibit 1102 Complaint in Cresta Technology Corporation v. Maxlinear, Inc.

et al., Case No. 1:14-cv-00079-RGA before the United States District Court for the District of Delaware (January 21, 2014) (“Complaint”).

Exhibit 1103 Complaint in ITC Investigation No. 377-TA-910 (June 12,

2014) (“ITC Amended Complaint”). Exhibit 1104 Favrat et al., U.S. Patent No. 7,075,585, titled “Broadband

Receiver having a Multistandard Channel Filter,” filed September 6, 2002 (“Favrat”).

Exhibit 1105 Yang, U.S. Patent No. 5,663,768, titled “Multi-Television

Broadcasting Signal Receiving Apparatus and Control Method Thereof,” filed June 6, 1995 (“Yang”).

Exhibit 1106 Wilkie, U.S. Patent No. 5,526,017, titled “Analog Image Signal

Processor for a Multimedia System,” filed October 26, 1993 (“Wilkie”).

Exhibit 1107 Vorenkamp et al., U.S. Patent No. 7,106,388, titled “Digital IF

Demodulator for Video Applications,” filed December 15, 2000 (“Vorenkamp”).

Exhibit 1108 Oku et al., U.S. Patent No. 6,310,654, titled “Decoder Device

and Receiver Using the Same,” filed February 2, 1999 (“Oku”). Exhibit 1109 Gray et al., U.S. Patent No. 4,872,054, titled “Video Interface

for Capturing an Incoming Video Signal and Reformatting the Video Signal,” filed June 30, 1988 (“Gray”).

Exhibit 1110 Eglit et al., U.S. Patent No. 5,642,139, titled “PCMCIA Video

Card,” filed April 29, 1994 (“Eglit”).

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Exhibit 1111 IEEE 100: The Authoritative Dictionary of IEEE Standards Terms, Seventh Edition

Exhibit 1112 Excerpts of the prosecution file history of the ‘792 patent. Exhibit 1114 J. Mitola, “The Software Radio Architecture,” IEEE

Communications Magazine, May 1995 (“Mitola’95”). Exhibit 1115 J. Mitola, “Software Radio Architecture: A Mathematical

Perspective,” IEEE Journal on Selected Areas in Communications, vol. 17, no. 4, April 1999 (“Mitola’99”).

Exhibit 1116 Software Radio Architecture: Object-oriented Approaches to

Wireless Systems Engineering, Joseph Mitola III, Wiley, January 2000 (“Mitola’00”).

Exhibit 1117 D. Efstathiou, “Recent Developments in Enabling Technologies

for Software Defined Radio,” IEEE Communications Magazine, vol. 1, pp. 112 – 117, August 1999 (“Efstathiou’99”).

Exhibit 1118 D. Efstathiou, “SoftCellTM: A Multi-carrier Chip-set for

Software Definable Radio Base-stations,” IEEE Global Communications Conference, vol. 1, pp. 172 – 176, 2000 (“Efstathiou’00”).

Exhibit 1119 J. Razavilar, F. Rashid-Farrokhi, and K. J. Liu, “Software

Radio Architecture With Smart Antennas: A Tutorial on Algorithms and Complexity,” IEEE Journal on Selected Areas in Communications, vol. 17, no. 4, pp. 662 – 676, April 1999 (“Razavilar’99”).

Exhibit 1120 “Micronas Introduces First All CMOS Intermediate Frequency

(IF) Chip To Handle Analog and Digital Broadcast Signals (0020),” November 21, 2000 (“Micronas’00”).

Exhibit 1121 “STV0399 Front-End Single Chip for Digital Satellite

Broadcasting,” STMicroelectronics, 2001 (“STM’01”). Exhibit 1122 W. Boie, “Broadcast Receiver Adapted for Analog and Digital

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Signals,” 1996 European Patent application EP 0696854, 1996 (“Thomson”).

Exhibit 1123 W. Zhang, T. Misko, and J. Woodburn, “Digital

Implementation of Multi-Channel Demodulators,” U.S. Patent 6,704,372, issued March 9, 2004 (filed Sep. 18, 2001) (“Zhang’01”).

Exhibit 1124 Software Radio Technology and Service, Editor: E. Del Re,

Springer, 2001 (“DelRe’01”). Exhibit 1125 A Look at Software Radio: Are They Fact or Fiction,”

Electronic Design, December 1, 1998 (“ED’98”). Exhibit 1126 R. Coy, C. Smith, and P. Smith, “HF-Band Radio Receiver

Design Based on Digital Signal Processing,” Electronics & Communication Engineering Journal, pp. 83 – 90, April 1992 (“Coy’92”).

Exhibit 1127 RF Microelectronics, Behzad Razavi, Publisher: Prentice Hall,

1997 (“Razavi’97”). Exhibit 1128 The Design of CMOS Radio-Frequency Integrated Circuits,

Thomas H. Lee, Publisher: Cambridge University Press, 1998 (excerpt, “Lee’98”).

Exhibit 1129 E. Colin, L. Naviner, P. Loumeau, and J. Naviner, “Trade-Off

Between Antialiasing Filter and Analog-To-Digital Converters Specifications in Homodyne Radio Frequency Receivers,” in IEEE VTC, pp. 2351 – 2354, 2001 (“Colin’01”).

Exhibit 1130 Signals and Systems, A. Oppenheim, Prentice Hall, Second

Edition, 1997 (“Oppenheim’97”). Exhibit 1131 Digital Signal Processing – A Computer-Based Approach,

Sanjit Mitra, McGraw Hill, Second Edition, 2001 (“Mitra’01”). Exhibit 1132 CMOS Wireless Transceiver Design, Jan Crols and Michiel

Steyaert, Kluwer Academic Publishers, 1997 (excerpt, “Crols’97”).

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Exhibit 1133 C. Strolle and S. Jaffe, “Multiple Modulation Format Television

Signal Reception System,” US Patent 6,005,640, December 1999 (“Strolle’99”).

Exhibit 1134 C. Robbins, R. Friedman, and M. Fazili, “Digital Signal

Processor for Multi-Standard Television,” US Patent 6,147,713, November 2000 (“Robbins’00”).

Exhibit 1135 D. Ehrhardt and T. Benkner, wrote a paper published in the

August 1993 issue of the IEEE Transactions on Consumer Electronics (“Ehrhardt’93”).

Exhibit 1136 H. Yoshida and H. Tsurumi, “Software Radio Technology and

Service.” (“Yoshida’01”). Exhibit 1137 A. Balaban, M. Low, and E. Fox, “Receiver for Analog and

Digital Television Signals,” US Patent 6,369,857, April 2002 (“Balaban”).

Exhibit 1138 R. Van De Plassche, A. Bruekers, G. Giellis, “Multi-Standard

Reception,” US Patent 6,643,502, November 2003 (“VDP”). Exhibit 1139 Arambepola et al., U.S. Patent No. 7,280,616, titled

“Optimizing a Filter Bandwidth in a Digital Receiver,” filed October 27, 2003, which claims priority to British Application 0225598.2, with a priority date of November 2, 2002

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Petitioner hereby requests that the United States Patent and Trademark

Office proceed with an inter partes review of claims 1–29 of U.S. Patent No.

7,265,792 (“the ’792 patent”) (Ex. 1101).

I. COMPLIANCE WITH FORMAL REQUIREMENTS

A. Grounds for Standing (37 C.F.R. § 42.104(a))

In accordance with 37 C.F.R. § 42.104(a), Petitioner certifies that the ’792

patent is available for inter partes review. Petitioner further certifies that Petitioner

is not barred or estopped from requesting an inter partes review challenging the

’792 patent on the grounds identified in this Petition.

B. Real Parties-In-Interest (37 C.F.R. § 42.8(b)(1))

MaxLinear, Inc. (“Petitioner”) and Cresta Technology Corporation (“Patent

Owner” or “CrestaTech”) are the real parties-in-interest in this matter.

C. Related Matters (37 C.F.R. § 42.8(b)(2))

Patent Owner has filed two actions against Petitioner in which Patent Owner

alleges that Petitioner infringes the ‘585 patent: Cresta Technology Corporation v.

Maxlinear, Inc. et al., Case No. 1:14-cv-00079-RGA, filed on January 21, 2014, in

the United States District Court for the District of Delaware (Complaint, Ex.

1102); and Investigation No. 337-TA-910, filed on January 28, 2014, in the

International Trade Commission (“ITC”) (ITC Amended Complaint, Ex. 1103). In

both cases, Patent Owner also sued certain of Petitioner’s customers (Sharp and

VIZIO, Inc.).

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In addition to these lawsuits, co-defendant/co-respondent, Silicon

Laboratories, Inc. has also filed the following petitions seeking inter partes review

of the Cresta patents asserted in the ITC Complaint:

Proceeding No. Patent at Issue Filing Date Petitioner

2014-00728 7,075,585 May 5, 2014 Silicon Laboratories

2014-00809 7,265,792 May 23, 2014 Silicon Laboratories

2015-00615 7,075,585 January 23, 2015 Silicon Laboratories

2015-00626 7,265,792 January 26, 2015 Silicon Laboratories

2015-00591 7,075,585 January 28, 2015 MaxLinear



2015-00594

“Petition” 7,265,792 January 28, 2015 MaxLinear

On October 24, 2014, the Board instituted review of claims 1, 2 and 4–17 of

the ‘792 patent in IPR2014-00809.

D. Counsel and Service Information (37 C.F.R. § 42.8(b)(3)-(4))

Address all e-mails and telephone calls to lead and back up counsel (each

associated with the above Customer Number), listed below:

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Lead Counsel Back-Up Counsel Name: Thomas J. Wimbiscus (Reg. No. 36,059) ([email protected]) Direct: 312-775-8109

Name: Christopher C. Winslade (Reg. No. 36,308) ([email protected]) Direct: 312-775-8108

Name: Gregory C. Schodde (Reg. No. 36,668) ([email protected]) Direct: 312-775-8117

Name: Scott P. McBride (Reg. No. 42,853) ([email protected]) Direct: 312-775-8131

Name: Ronald H. Spuhler (Reg. No. 52,245) ([email protected]) Direct: 312-775-8210

Wayne H. Bradley (Reg. No. 39,916) ([email protected]) Direct: 312-775-8187

Address all communications to:

Thomas J. Wimbiscus Christopher C. Winslade Gregory C. Schodde Scott P. McBride Ronald H. Spuhler Wayne H. Bradley MCANDREWS HELD & MALLOY 500 W. Madison, 34th Flr. Chicago, IL 60661 312-775-8000

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Please direct all correspondence regarding this proceeding to the lead

counsel at the address listed above. Patent Owner also consents to electronic

service by e-mail to [email protected].

The Patent Trial and Appeal Board is hereby authorized to charge any fees

associated with this proceeding to Deposit Account 13-0017 (Customer ID 23446).

E. Statement of Precise Relief Requested

In accordance with 37 C.F.R. § 42.22, Petitioner respectfully requests

cancellation of claims 1–29 of the ‘792 patent.

II. REASONABLE LIKELIHOOD TO PREVAIL

This Petition, in accordance with 35 U.S.C. § 314(a), establishes a

reasonable likelihood that Petitioner will prevail with respect to at least one of the

claims challenged in this petition because the Petition provides evidence and

supporting reasoning showing that all of the elements of each of claims 1–29 of the

‘792 patent are unpatentable over the prior art.

III. IDENTIFICATION OF CHALLENGE

A. Prior Art Publications

Petitioner relies on the following prior art publications:

1. Favrat et al., U.S. Patent No. 7,075,585, titled “Broadband Receiver having a

Multistandard Channel Filter,” filed September 6, 2002 (Exhibit 1104)

(“Favrat”). Favrat claims priority to Provisional U.S. Patent Application

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60/322,548 filed September 17, 2001. Favrat is prior art at least under 35

U.S.C. § 102(e) (pre-AIA).

2. Yang, U.S. Patent No. 5,663,768, titled “Multi-Television Broadcasting

Signal Receiving Apparatus and Control Method Thereof,” filed June 6,

1995 (Exhibit 1105) (“Yang”). Yang claims priority to Korean Patent

Application 94-12940, with a priority date of June 9, 1994. Yang is prior art

at least under 35 U.S.C. § 102(e) (pre-AIA).

3. Wilkie, U.S. Patent No. 5,526,017, titled “Analog Image Signal Processor

for a Multimedia System,” filed October 26, 1993 (Exhibit 1106) (“Wilkie”).

Wilkie claims priority to U.S. Patent Application No. 625,734 filed

December 11, 1990, abandoned. Wilkie is prior art at least under 35 U.S.C.

§ 102(e) (pre-AIA).

4. Vorenkamp et al., U.S. Patent No. 7,106,388, titled “Digital IF Demodulator

for Video Applications,” filed December 15, 2000 (Exhibit 1107)

(“Vorenkamp”). Vorenkamp claims priority to 60/171,199, filed on

December 15, 1999. Vorenkamp is prior art at least under 35 U.S.C. §

102(e) (pre-AIA).

5. Oku et al., U.S. Patent No. 6,310,654, titled “Decoder Device and Receiver

Using the Same,” filed February 2, 1999 (Exhibit 1108) (“Oku”). Oku

claims priority to Japan Application 10-022916, with a priority date of

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February 4, 1998. Oku is prior art at least under 35 U.S.C. § 102(e) (pre-

AIA).

6. Gray et al., U.S. Patent No. 4,872,054, titled “Video Interface for Capturing

an Incoming Video Signal and Reformatting the Video Signal,” filed June

30, 1988 (Exhibit 1109) (“Gray”). Gray is prior art at least under 35 U.S.C. §

102(e) (pre-AIA).

7. Eglit et al., U.S. Patent No. 5,642,139, titled “PCMCIA Video Card,” filed

April 29, 1994 (Exhibit 1110) (“Eglit”). Eglit is prior art at least under 35

U.S.C. § 102(e) (pre-AIA).

8. Arambepola et al., U.S. Patent No. 7,280,616, titled “Optimizing a Filter

Bandwidth in a Digital Receiver,” filed October 27, 2003 (Exhibit 1139)

(“Arambepola”). Arambepola claims priority to British Application

0225598.2, with a priority date of November 2, 2002. Arambepola is prior

art at least under 35 U.S.C. § 102(e) (pre-AIA).

B. Brief Statement of Grounds for Challenge

Petitioner challenges claims 1–29 (“the challenged claims”) of the ‘792

patent. Petitioner requests IPR of Claims 1-29 on the grounds set forth in the table

below, and requests that they be found unpatentable and be canceled. An

explanation of unpatentability under the statutory grounds identified below is

provided in the detailed description that follows, indicating where each element

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can be found in the cited prior art, and the relevance of that prior art. Additional

explanation and support for each ground of rejection is set forth in the Declaration

of Dr. Hashemi. (Ex. 1112).

Grounds ’792 Patent Basis for Rejection

Ground 1 1, 2, 4, 5, 11 and 24-29 Anticipated under §102(e) by Favrat

and Obvious under 35 U.S.C. §103(a)

over Favrat

Ground 2 3 Obvious under 35 U.S.C. §103(a) over

Favrat in view of Arambepola


Favrat in view of Yang

Ground 4 7-9 and 12 Obvious under 35 U.S.C. §103(a) over

Favrat in view Wilkie


Favrat in view of Vorenkamp

Ground 6 13-15 and 18 Obvious under 35 U.S.C. §103(a) over

Favrat in view of Oku

8

Ground 7 16, 17 and 19 Obvious under 35 U.S.C. §103(a) over

Favrat in view of Oku and further in

view of Gray

Ground 8 20-23 Obvious under 35 U.S.C. §103(a) over

Favrat in view of Oku and further in

view of Eglit and Wilkie

1. Grounds are Not Redundant of the Original Prosecution

The application for Favrat, the application for Oku, and Grey were admitted

in the ‘792 patent as being prior art. The Favrat application was relied upon by the

Examiner to initially reject claims 1–4, 11, 12 and 29 (as issued) of the ‘792 patent

during original prosecution of the ‘792 patent. In particular, the Examiner

identified all features of claims 1–4, 11, 12 and 29 in the Favrat application except

for the limitation requiring a plurality of FIR filters in independent claim 1.

The Favrat application and Oku application were relied upon by the

Examiner to initially reject claims 5, 10, 13 and 14. The Favrat application, the

Oku application, and Gray were relied upon by the Examiner to initially reject

claims 6–9, 15, and 18–29.

Despite allowance by the Examiner based on the plurality of FIR filters

feature of claim 1, this feature appeared (almost verbatim) in the Favrat

9

application. Grounds 1-8 in the Petition correct this oversight.

2. Grounds are Not Redundant of Other Petitions for IPR

The grounds in the IPR2014-00809 petition are:

Ground 1: Claims 1, 2, 4, 10, 11, and 26 are invalid under 35 U.S.C. § 103 as

obvious over Thomson (EP 0696854) in view of Harris (A Digital Tuner

for Wideband Receivers).

Ground 2: Claims 1, 2, 4, 10, 11, and 26 are invalid under 35 U.S.C. § 103 as

obvious over Thomson in view of TI App Note.

Ground 3: Claim 3 is invalid under 35 U.S.C. § 103 as obvious over Thomson

and Harris in further view of Gunter (USP 4,782,385) or, in the alternative,

Thomson and TI App Note in further view of Gunter.

Ground 4: Claims 5 and 6 are invalid under 35 U.S.C. § 103 as obvious over

Thomson and Harris in further view of Cirrus Logic (NTSC/PAL digital

video encoder) or, in the alternative, Thomson and TI App Note in further

view of Cirrus Logic.


Thomson and Harris in further view of Kerth (USP 6,804,497) or, in the

alternative, Thomson and TI App Note in further view of Kerth.

Ground 6: Claims 13–17 are invalid under 35 U.S.C. § 103 as obvious over

Thomson and Harris in further view of Oku and Kerth or, in the

10

alternative, Thomson and TI App Note in further view of Oku and Kerth.


Thomson and Harris in further view of Kerth and Cirrus Logic or, in the

alternative, Thomson and TI App Note in further view of Kerth and Cirrus

Logic.


Thomson and Harris in further view of Balaban (USP 6,369,857) or, in the

alternative Thomson and TI App Note in further view of Balaban.

Ground 9: Claims 1 is invalid under 35 U.S.C. § 102 as anticipated by Patel

(USP 6,124,898).

3. The Grounds in the IPR2015-00626 Petition

Ground 1: Claim 29 is invalid under 35 U.S.C. § 103 as obvious over

Thomson in view of Harris.

Ground 2: Claims 24 and 25 are invalid under 35 U.S.C. § 103 as obvious

over Thomson and Harris in view of Grumman.


over Thomson and Harris in view of Zenith.

Ground 4: Claim 27 is invalid under 35 U.S.C. § 103 as obvious over

Thomson and Harris in view of Zenith and Birleson.


11

over Thomson and Harris in further view of Oku, Ericsson, and Nguyen.

Grounds 1-8 in the Petition comprise claims 20-23, which were not included

in IPR2014-00809 or IPR2015-00626.

Grounds 1-8 in the Petition are different and better, in some respects, than

the grounds in the IPR2014-00809 and IPR2015-00626, since Farvat satisfies the

claim limitations more closely than Thomson in view of Harris. For example,

many of the elements in the challenged claims also appear in Favrat. Often, the

only difference between claim elements is that Favrat used “said,” whereas the

‘792 patent used “the.”

This Petition, supported by the Declaration of Dr. Hashemi, demonstrates

that there is a reasonable likelihood that Petitioner will prevail with respect to at

least one of the challenged claims and that each of the challenged claims is

unpatentable for the reasons cited in this petition. (See 35 U.S.C. § 314(a).)

IV. INVALIDITY OF THE ‘792 PATENT

A. Introduction

The ’792 patent, titled “Television Receiver for Digital and Analog

Television Signals,” was filed July 1, 2014 and originally assigned to Xceive Corp.

(Ex. 1101). After Xceive’s business faltered, Cresta purchased certain of Xceive’s

assets including the ‘792 patent on October 10, 2011. (ITC Amended Complaint,

Ex. 1103, p.4.) In January of this year, CrestaTech sued Petitioner and several of

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its customers for infringing two of the patents it acquired from Xceive. (Id.)

The ’792 application describes several iterations of a “signal output circuit,”

labeled “140” in Fig. 1 (below). (Id. at 6:49–51.)

This output circuit converts the “processed IF signals” into “the desired output

signals.” (Id.) Figure 2 goes on to illustrate several other “desired output signals”

including analog v. digital, single-ended v. differential, or serial v. parallel. (Id. at

Fig. 2; 7:34–35 “Turning now to FIG. 2 where alternate embodiments of the signal

output circuit are shown.”)

B. Prosecution History of the ‘792 Patent

The ’792 patent application was filed on July 1, 2004. In the first office

action, claims 1–4, 11, 12 and 30–341 were rejected under 35 U.S.C. § 102(b) as

anticipated by the for Favrat application. Claims 5, 10, 13 and 14 were rejected

under 35 U.S.C. § 103(a) as being unpatentable over the ’585 application in view

of Oku application. Claims 16 and 17 were rejected under 35 U.S.C. § 103(a) as

1 Claim 30 as filed issued as claim 29. (See Ex. 1112, p. 37.)

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being unpatentable over the ’585 application in view of the Oku application, in

further view of Gray. Claims 6–9, 15, and 18–29 were indicated to contain

allegedly allowable subject matter. (Ex. 1112, pp. 58-63.)

In response to the first office action, the applicant amended claim 1 to recite

the limitations formerly of claim 24. The applicant also amended all of the other

claims to depend from claim 1. Because the subject matter of claim 24 had been

indicated as allowable, the applicant argued that independent claim 1 and all

depending claims were therefore allowable. The applicant cancelled claim 24 as

well as claims 31–34 and requested allowance of all remaining claims. (Ex. 1112

pp. 47-53.)

The Examiner then allowed all remaining claims in the application (Ex.

1112, p. 41), despite the fact that the limitation added to claim 1 by amendment

was clearly taught in the ‘585 application. For example, claim 11 of the Favrat

application is virtually identical to the allegedly allowable subject matter. (See Ex.

1104 at claim 10 “wherein said signal processor applies one of a plurality of finite

impulse response filters.”)

It appears that the Patent Owner recognized that the ’792 patent was invalid

and attempted to fix the problem by filing the terminal disclaimer on October 1,

2014 with respect to Favrat. (See Ex. 1112, p. 2.) However, this terminal

disclaimer fails to overcome the fact that Favrat is prior art under § 102(e) (pre-

14

AIA).

Favrat (Ex. 1104) The ‘792 Patent (Ex. 1101) Inventors Pierre Favrat,

Didier Margairaz, Alain-Serge Porret, Dominique Python

Pierre Favrat, Didier Margairaz, Alain-Serge Porret, Dominique Python, Friederich Mombers, Richard P. Perring, Philippe Duc, and Benito Carnero

Filed September 6, 2002 July 1, 2004 Priority Provisional Application

September 17, 2001 None

Published April 1, 2004 January 5, 2006

Favrat is a patent granted on an application for patent by another filed in the

United States before the invention by the applicant for patent.

“Another” means other than applicants, In re Land, 368 F.2d 866, 151

USPQ 621 (CCPA 1966), in other words, a different inventive entity.

The inventive entity is different if not all inventors are the same. The

fact that the application and reference have one or more inventors in

common is immaterial. Ex parte DesOrmeaux, 25 USPQ2d 2040 (Bd.

Pat. App. & Inter. 1992) (The examiner made a pre-AIA 35 U.S.C.

102(e) rejection based on an issued U.S. patent to three inventors. The

rejected application was a continuation-in-part of the issued parent

with an extra inventor. The Board found that the patent was “by

another” and thus could be used in a pre-AIA 35 U.S.C. 102(e)/103

rejection of the application.).

(See, e.g., MPEP § 2136.04.I.)

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Therefore, Favrat is prior art under pre-AIA 35 U.S.C. 102(e). A terminal

disclaimer does not overcome a pre-AIA 35 U.S.C. 102(e) rejection. (See, e.g.,

MPEP § 2136.05.I.)

C. Person of Ordinary Skill in the Art

A person of ordinary skill in the art at the time of the alleged invention of

the ’792 patent (“POSITA”) would have held at least a Masters of Science or

higher degree in electrical engineering, as well as about four years of substantial

experience designing or doing research in the area of wireless communication

receivers and integrated circuit realization of Radio Frequency, known as RF,

wireless communication receivers. (Ex. 1113, Hashemi Dec., ¶¶ 10-14.)

Additional education may compensate for less experience and vice-versa. (Id.)

The field to which the ’792 patent is directed is the field of integrated circuits and

Radio Frequency communication receivers. (Id.) This is a very demanding field

with little margin for error that requires a high level of skill to practice. (Id.) The

POSITA should have a holistic knowledge of wireless communication systems; RF

integrated circuits; and analog, mixed-signal, and digital integrated circuits. (Id.)

V. CLAIM CONSTRUCTION

The claims in an inter partes review should be accorded the broadest

reasonable construction, as commonly understood by those of ordinary skill in the

art in view of the descriptions of the specification. (See 37 C.F.R. § 42.100(b).)

16

Because the standard for claim construction at the Patent Office is different

from that used during a U.S. District Court litigation, the Petitioner expressly

reserves the right to argue a different claim construction in litigation for any term

of the ’792 patent, as appropriate in that proceeding.

A. Summary of Claim Terms Construed

The terms that the Petitioner has decided to construe are summarized below:

Term Claims Petitioner’s Construction

“RF signal” 1, 8, 13, 18, 20, 22, 26,

28 and 29

signal having a frequency

between 10 kHz and 100 GHz

“format”

1, 2, 4, 5, 7, 8, 11, 14,

15, 18, 20-23 and 26-

28

distinct signal format, such as

analog or digital

“video and audio

baseband signals” 8 and 9

at least one signal without

transmission modulation

“signal processor” 1, 13, 18, 20 and 22-26 digital module that processes

signals in the digital domain

B. “RF signal”

The specification of the ’792 patent defines “RF” as an abbreviation for

“radio frequency” (Ex. 1101, 1:36), which The Authoritative Dictionary of IEEE

Standards Terms identifies as a frequency roughly between 10 kHz and 100 GHz.

17

(Ex. 1111, p 912.) The Petitioner construes an “RF signal” as a “signal having a

frequency between 10 kHz and 100 GHz.” The Petitioner’s construction is

supported by Dr. Hashemi Declaration. (Ex. 1113, Hashemi Dec., ¶ 16.)

C. “format”

The ’792 patent specification draws a distinction between “formats” and

“standards”: “Television signals are transmitted in analog or digital formats and in

accordance with a variety of standards.” (Ex. 1101, 1:18-20, emphasis added.)

The specification further identifies “analog or digital TV” as examples of formats

and “NTSC, PAL or SECAM” as examples of television standards. (Id. at 1:57-

58.) The Petitioner construes “format” as “distinct signal format, such as analog or

digital.” The Petitioner’s construction is supported by Dr. Hashemi Declaration.

(Ex. 1113, Hashemi Dec., ¶ 17.)

D. “video and audio baseband signals”

The specification of the ’792 patent admits it was known in the art that a

demodulator for an analog television standard will output a video baseband signal

and an audio baseband signal. The specification of the ’792 patent also admits that

it was known in the art that a demodulator for a digital television standard will

output one baseband signal – an MPEG data stream. (See, e.g., Ex. 1101, 9:63-65

“Demodulator circuit 206 operates to demodulate the DTV low-IF signal and

generates an MPEG data stream as an output signal.) Since the ’792 patent

18

specification clearly indicates that a demodulator for digital television formats will

output one signal (i.e., a MPEG data stream), the terms “video and audio baseband

signals [plural]” is broadly construed as “at least one signal without transmission

modulation.”

Furthermore, claims 8 and 9 do not support a construction of “video and

audio baseband signals” that requires two signals (e.g., a video baseband signal and

an audio baseband signal.) Since the video and audio baseband signals in claims 8

and 9 are demodulated and correspond to the digital television format, the video

and audio baseband signals in claims 8 and 9 include only one baseband signal –

an MPEG data stream. The Authoritative Dictionary of IEEE Standards Terms

defines “baseband signaling” as “[t]he transmission of a signal at its original

frequency, that is, not changed by modulation. Note: It can be an analog or a

digital signal.” (Ex. 1111, p 87.)

The Petitioner construes “video and audio baseband signals” as “at least one

signal without transmission modulation.” The Petitioner’s construction is

supported by Dr. Hashemi Declaration. (Ex. 1113, Hashemi Dec., ¶¶ 18-22.)

E. “signal processor”

The specification supports a construction of “signal processor” that is

limited to digital signal processing, stating, for example:

Another advantage of the dual-format TV receiver of the present

19

invention is that the digital signal processor circuit of the receiver

uses a single processing path to process television signals in either

analog format or the digital format. Thus, the need to duplicate

components is entirely obviated. Finally, the digital signal processor

circuit can be readily reconfigured to support multi-standard

reception, thereby enabling the television receiver of the present

invention to be used in any geographic area of interest.

(Ex. 1101, 3:44-54, emphasis added.)

A salient feature of the dual-format television receiver of the present

invention is the use of a signal programmable digital signal

processing path for the processing the received television signal

regardless of the television format and standard in which the

television signal is transmitted.

(Ex. 1101, 9:24-28, emphasis added.) It appears that the preferred embodiment of

the signal processor is a programmable, reconfigurable digital signal processor.

The Petitioner construes “signal processor” as a “digital module that

processes signals in the digital domain.” The Petitioner’s construction is supported

by Dr. Hashemi Declaration. (Ex. 1113, Hashemi Dec., ¶¶ 23-25.)

VI. DETAILED EXPLANATIONS OF THE CHALLENGES

The detailed explanation provided below, along with the referenced

Declaration of Dr. Hashemi (Ex. 1113), demonstrates each ground for each of the

challenged claims. Challenged claims 2-29 of the ’792 patent each depend from

20

independent claim 1.

A. Ground 1: Claims 1, 2, 4, 5, 11 and 24-29 are anticipated by Favrat

Every limitation in claim 1 (except for the “signal output circuit” limitation)

is copied from Favrat. However, the “signal output circuit” limitation” in claim 1

is a later genus limitation that is anticipated by an earlier species limitation

disclosed by Favrat.

Claim 1 comprises “a signal output circuit for receiving the digital output

signals from the signal processor and for providing one or more output signals

corresponding to the digital output signals.” In claim 11, “the signal output circuit

provides output signals in an analog or a digital signal format.” A circuit that

receives “digital output signals” and “provides output signals in an analog… signal

format” is a digital-to-analog converter (DAC). Therefore, a DAC is one species

of the “signal output circuit” in claim 1.

Claim 2 of Favrat comprises “a digital-to-analog converter coupled between

said signal processor and a first one of said plurality of demodulators, said digital-

to-analog converter converting said digital output signals to an analog format.”

Thus, the “a signal output circuit for receiving the digital output signals from the

signal processor and for providing one or more output signals corresponding to the

digital output signals” limitation in claim 1 is a later genus limitation that is

anticipated by the earlier species limitation in Favrat, claim 2. (See Eli Lilly & Co.

21

v. Barr Labs., Inc. 251 F.3d 955, 971 (Fed. Cir. 2001) “[This court’s] case law

firmly establishes that a later genus claim limitation is anticipated by, and therefore

not patentably distinct from, an earlier species claim.”)

‘792 Patent - Claim 1 (Ex. 1101) Favrat (Ex. 1104) 1. A television receiver comprising: (Ex. 1113, Hashemi Dec., ¶ 28.)

See, e.g., claim 1 (“A receiver comprising”), claim 2 (“television format”). See also Figure 2, 3:44-45 (“FIG. 2 is a block diagram of a television receiver according to one embodiment of the present invention.”); 2:43-46, Abstract.

a frequency conversion circuit for receiving an input RF signal and for converting the input RF signal to an intermediate frequency signal having an intermediate frequency (IF),

(Ex. 1113, Hashemi Dec., ¶ 29.) See, e.g., claim 1 (“a tuner for receiving input RF signals and for converting said input RF signals to intermediate signals having an intermediate frequency (IF)”); claim 17 (“converting said input RF”). See also 3:45-48, Figure 2; 3:48-51, 3:51-52 (“For example, tuner 54 can perform a single or dual super-heterodyne conversion.”), 3:52-55 (“In one embodiment of the present invention, tuner 54 is a commercially available discrete component and outputs intermediate signals having an intermediate frequency (IF) that is determined by the geographic region of interest.”), 3:59-63.

the input RF signal encoding information in one of a plurality of television signal formats;

(Ex. 1113, Hashemi Dec., ¶ 30.) See, e.g., claim 1 (“said input RF signals encoding information in one of a plurality of formats”), claim 2, claim 17 and 18 See also 3:26-30, at 2:48-51, Abstract,

22

3:30-35, 5:27-29 (“receiver 100 can handle television signals in any format (analog or digital) and in any standard (e.g.: NTSC, PAL, SECAM, DVB or ATSC)”)

an analog-to-digital converter for sampling the intermediate frequency signal and generating a digital representation thereof

(Ex. 1113, Hashemi Dec., ¶ 31.) See, e.g., claim 1 (“an analog-to-digital converter for sampling said filtered intermediate signals and generating a digital representation thereof”). See also 4:5-7, 4:25-27, Figure 2.

a signal processor for processing the digital representation of the intermediate frequency signal in accordance with the television signal format of the input RF signal, the signal processor generating digital output signals indicative of information encoded in the input RF signal,

(Ex. 1113, Hashemi Dec., ¶ 32.) See, e.g., claim 1 (“a signal processor for processing said digital representation of said intermediate signals in accordance with said format of said input RF signal, said signal processor generating digital output signals indicative of information encoded in said input RF signal”). See also 2:56-60, 4:51-54, 5:7-22, Figure 2, 4:65.

wherein the signal processor applies one of a plurality of finite impulse response filters to the digital representation of the intermediate frequency signal, each of the plurality of finite impulse response corresponding to a format of the input RF signal

(Ex. 1113, Hashemi Dec., ¶¶ 33.) See, e.g., claim 10 (“wherein said signal processor applies one of a plurality of finite impulse response filters to said digital representation of said intermediate signal, each of said plurality of finite impulse response corresponding to a format of said input RF signal”). See also Figure 2, 4:66-5:1.

a signal output circuit for receiving the digital output signals from the signal processor and for providing one or more output signals corresponding to the digital output signals.

(Ex. 1113, Hashemi Dec., ¶ 34-36.) See, e.g., claim 3 (“The receiver of claim 1, further comprising: a digital-to-analog converter coupled between said signal processor and a first one of said plurality of demodulators, said digital-to-analog

23

converter converting said digital output signals to an analog format.”) . See also 5:54-58 (“In cases where analog demodulator 66a receives analog input signals only, a digital-to-analog converter (DAC) (not shown) can be included between the output terminal of DSP 64 and the input terminal of analog demodulator 66a.”).

‘792 Patent - Claim 2 (Ex. 1101) Favrat (Ex. 1104) 2. The television receiver of claim 1, wherein the plurality of television signal formats comprises

(Ex. 1113, Hashemi Dec., ¶ 37.) See above discussion of ‘792 patent, claim 1. See also Ex. 1104 at claims 1 and 2.

an analog television format and a digital television format.

(Ex. 1113, Hashemi Dec., ¶ 37.) See above discussion of ‘792 patent, claim 1. See also Ex. 1104 at claim 1, claim 2 (“said plurality of formats comprise an analog television format and a digital television format”)

‘792 Patent - Claim 4 (Ex. 1101) Favrat (Ex. 1104) 4. The television receiver of claim 1, wherein the signal output circuit provides

(Ex. 1113, Hashemi Dec., ¶ 38.) See above discussion of ‘792 patent, claim 1.

a first output signal being a video baseband signal corresponding to an analog television format and a second output signal being an audio baseband signal corresponding to the analog television format.

(Ex. 1113, Hashemi Dec., ¶ 38.) See, e.g., 5:49-52 (… “demodulators 66 include a demodulator for analog television signals 66 a …”); 5:59-62 (“Analog demodulator 66a provides three output signals: a Composite Video Baseband Signal (CVBS) containing the video information, and audio 1 and audio 2 containing the audio information.”).

‘792 Patent - Claim 5 (Ex. 1101) Favrat (Ex. 1104) 5. The television receiver of claim 4, further comprising:

(Ex. 1113, Hashemi Dec., ¶ 39.) See above discussion of ‘792 patent,

24

claim 4. a first decoder circuit coupled to decode the video baseband signal for providing video display signals corresponding to the analog television format; and

(Ex. 1113, Hashemi Dec., ¶ 40.) See, e.g., 5:46-48 (“The video and audio baseband signals are usually coupled to video and audio decoders before being displayed or playback on a view screen.”); 1:55-57 (describing prior art Figure 1, “[t]he baseband signals are coupled to appropriate video and audio decoders to generate the display signals (e.g. RGB) or sound.”).

a second decoder circuit coupled to decode the audio baseband signal for providing audio signals corresponding to the analog television format

(Ex. 1113, Hashemi Dec., ¶ 41.) See, e.g., 5:46-48 (“The video and audio baseband signals are usually coupled to video and audio decoders before being displayed or playback on a view screen.”); 1:55-57 (describing prior art Figure 1, “[t]he baseband signals are coupled to appropriate video and audio decoders to generate the display signals (e.g. RGB) or sound.”).

‘792 Patent - Claim 11 (Ex. 1101) Favrat (Ex. 1104) 11. The television receiver of claim 1, wherein the signal output circuit provides

(Ex. 1113, Hashemi Dec., ¶¶ 42.) See above discussion of ‘792 patent, claim 1.

output signals in an analog or a digital signal format.

(Ex. 1113, Hashemi Dec., ¶¶ 42.) See, e.g., 6:2-5 (“An additional digital-to-analog converter may be coupled to the output terminal of demodulator 66a if analog output signals are desired.”), claim 3 (“The receiver of claim 1, further comprising: a digital-to-analog converter coupled between said signal processor and a first one of said plurality of demodulators, said digital-to-analog converter converting said

25

digital output signals to an analog format.”); see also id. at 5:54-58 (“In cases where analog demodulator 66a receives analog input signals only, a digital-to-analog converter (DAC) (not shown) can be included between the output terminal of DSP 64 and the input terminal of analog demodulator 66a.”).

‘792 Patent - Claim 24 (Ex. 1101) Favrat (Ex. 1104)

24. The television receiver of claim 1, wherein


the plurality of finite impulse response filters are stored in a memory, and the signal processor indexes the memory to retrieve one of the plurality of finite impulse response filters.

(Ex. 1113, Hashemi Dec., ¶ 43.) See, e.g., claim 11 (“The receiver of claim 10, wherein said plurality of finite impulse response filters are stored in a memory, and said signal processor indexes said memory to retrieve one of said plurality of finite impulse response filters.”), claim 10 (“wherein said signal processor applies one of a plurality of finite impulse response filters to said digital representation of said intermediate signal, each of said plurality of finite impulse response corresponding to a format of said input RF signal.”). See also 4:60-64 (“In one embodiment, the coefficients of the filter functions are stored in a look-up table in a memory 70. DSP 64 retrieves the coefficients from memory 70 to be applied to the incoming digital signals.”).

‘792 Patent - Claim 25 (Ex. 1101) Favrat (Ex. 1104) 25. The television receiver of claim 1, wherein the signal processor

(Ex. 1113, Hashemi Dec., ¶ 44.) See above discussion of ‘792 patent,

26

comprises claim 1. a first computing unit and a second computing unit, the first computing unit processing a real part of the finite impulse response filter operation while the second computing unit processing an imaginary part of the finite impulse response filter operation.

(Ex. 1113, Hashemi Dec., ¶¶ 44.) See, e.g., claim 12 (“The receiver of claim 10, wherein said signal processor comprises a first computing unit and a second computing unit, said first computing unit processing a real part of said finite impulse response filter operation while said second computing unit processing an imaginary part of said finite impulse response filter operation.”), claim 10. See also 5:1-6 (“Furthermore, in the present embodiment, DSP 64 includes two computing units to speed up the computation time. Specifically, the filtering operations of the real and imaginary parts in the frequency domain are carried out in parallel. In other embodiments, DSP 64 may include only one computing unit.”).

‘792 Patent - Claim 26 (Ex. 1101) Favrat (Ex. 1104) 26. The television receiver of claim 1, further comprising


a format/standard selection circuit coupled to the signal processor, the format/standard selection circuit generating a select signal indicative of a format of the input RF signal and the signal processor selecting a finite impulse response filter in response to the select signal.

(Ex. 1113, Hashemi Dec., ¶ 45.) See, e.g., claim 13 (“The receiver of claim 10, wherein said channel filter further comprises a standard selection circuit coupled to said signal processor, said standard selection circuit generating a select signal indicative of a format of said input RF signal and said signal processor selecting a finite impulse response filter in response to said select signal.”), claim 10. See also 4:55-5:22, 4:55-60 (“…channel filter 58 includes a standard selection circuit 68 for selecting between the

27

several analog television standards and the several digital television standards. DSP 64 applies the appropriate filter function, such as an impulse response, to the digital signals depending on the state of standard selection circuit 68.”), Figure 2 (depicting the standard selection circuit feeding the DSP (64)).

‘792 Patent - Claim 27 (Ex. 1101) Favrat (Ex. 1104) 27. The television receiver of claim 26, wherein the format/standard selection circuit


generates the select signal in response to an input signal from a user.

(Ex. 1113, Hashemi Dec., ¶¶ 46.) See, e.g., claim 14 (“The receiver of claim 13, wherein said standard selection circuit generates said select signal in response to an input signal from a user.”) . See also 5:7-10 (“Standard selection circuit 68 can be implemented in one of many ways. The selection of the correct standard can be made manually by the user of the television system, such as by activating a switch …”).

‘792 Patent - Claim 28 (Ex. 1101) Favrat (Ex. 1104) 28. The television receiver of claim 26, wherein the format/standard selection circuit


generates the select signal by detecting carrier signals identifying one of the formats of the input RF signals.

(Ex. 1113, Hashemi Dec., ¶¶ 47.) See, e.g., claim 15 (“The receiver of claim 13, wherein said standard selection circuit generates said select signal by detecting carrier signals identifying one of said formats of said input RF signals.”) See also 5:7-22 (“Standard selection circuit 68 can be implemented in one of many ways. … In the present

28

embodiment, auto-detection is implemented by detecting in the baseband signals the presence or absence of carrier signals which uniquely identify the television standards. For example, analog television signals can be identified by the analog visual carrier signal while digital television signals can be identified by the pilot carrier. Each demodulator in bank 66 generates a signal which is fed back to standard selection circuit 68 indicating which television standard the input signal is encoded.”).

‘792 Patent - Claim 29 (Ex. 1101) Favrat (Ex. 1104) 29. The television receiver of claim 1, wherein the input RF signal comprises


an RF signal received from terrestrial broadcast, an RF signal received from satellite broadcast, and an RF signal received from cable transmission.

(Ex. 1113, Hashemi Dec., ¶ 48.) See, e.g., claim 16 (“The receiver of claim 1, wherein said input RF signals comprise RF signals received from one of terrestrial broadcast, from satellite broadcast, and from cable transmission.”). See also 6:26-30 (“… the television receiver of the present invention can be used to receive television signals distributed in any manner and provides excellent reception performance. Thus, the TV receiver of the present invention can be used for the reception of terrestrial broadcast and cable transmission.”); 1:24-28 (“A television or video recorder includes a television signal receiver (or television receiver) to receive terrestrial broadcast, cable television or satellite broadcast

29

television signals and to process the television signals into the appropriate video signals for display or for recording.”).

B. Ground 2: Claim 3 is obvious over Favrat in view of Arambepola

Arambepola teaches a multi-standard television receiver, which processes

signals in the digital domain. (See, e.g., Ex. 1139 at Arambepola, 1:6-11 (“The

present invention relates to a digital receiver. Such a receiver may be used for

receiving digital terrestrial television (DTTV) signals and digital audio

broadcasting (DAB) signals. Such a receiver is suitable for orthogonal frequency

division multiplex (OFDM) reception but may be suitable for receiving signals

with other modulation standards.”).) Therefore, a POSITA would be motivated to

use concepts from Arambepola with Favrat, which also teaches a multi-standard

television receiver. (Ex. 1113, Hashemi Dec., ¶ 49.)

Since Favrat already teaches the integration of a receiver “onto the same

piece of integrated circuit the motivation,” a POSITA would be motivated to

incorporate Arambepola idea of using “monolithic integrated circuits.” (See, e.g.,

Favrat , 6:12-15: “In one embodiment of the present invention, TV receiver 50 is

an integrated circuit where tuner 54, channel filter 58 and demodulators 66 are all

integrated onto the same piece of integrated circuit.”) (Ex. 1113, Hashemi Dec., ¶

50.)

30

‘792 Patent - Claim 3 (Ex. 1101)

Favrat (Ex. 1104) and Arambepola (Ex. 1139)


See above discussion of ‘792 patent, claim 1.

the television receiver is formed as a monolithic integrated circuit.

(Ex. 1113, Hashemi Dec., ¶ 49-51.) See, e.g., Ex. 1104, 6:12-15: “In one embodiment of the present invention, TV receiver 50 is an integrated circuit where tuner 54, channel filter 58 and demodulators 66 are all integrated onto the same piece of integrated circuit.” See, e.g., Ex. 1139, 4:2-5 (“The receiver is embodied as one or more monolithic integrated circuits and the filters 7 and 8 are integrated therein as any suitable implementation.”); and id. at 3:15-21 (“It is thus possible to provide an arrangement which the passbands of adjustable filters for baseband components to be adjusted accurately and relatively quickly. Such an arrangement makes possible the use of integrated analog filters which do not need to be highly specified in respect of their passbands. It is therefore possible to provide a receiver of improved performance and reduced cost of manufacture.”).

C. Ground 3: Claim 6 is obvious over Favrat in view of Yang

Yang teaches a multi-standard television receiver. Therefore, a POSITA

would be motivated to use concepts from Yang with Favrat, which also teaches a

multi-standard television receiver. (Ex. 1113, Hashemi Dec., ¶ 52-53.)

Favrat provides the motivation to add Yang’s plurality of detectors. For

example, Favrat teaches “a television (TV) receiver [that] includes a multi-standard

channel filter” (Ex. 1104 at 3:27-28) which uses “a plurality of demodulators” (Id.

at claim 1) “to receive television signals in a variety of television standards and

31

formats” (Id. at 3:29-30), and the background of Favrat describes “NTSC, PAL or

SECAM” (Id. at 2:7) as examples of television standards. Yang provides selectable

NTSC, PAL and ATSC detectors that a POSITA would use. (Ex. 1113, Hashemi

Dec., ¶ 53-54.)

(Ex. 1105, Yang, Fig. 4.)

‘792 Patent - Claim 6 (Ex. 1101) Favrat (Ex. 1104) and Yang (Ex. 1105)

6. The television receiver of claim 5, wherein the first decoder circuit comprises

See above discussion of ’792 patent, claim 5.

a PAL/SECAM/NTSC decoder circuit. (Ex. 1113, Hashemi Dec., ¶ 52-54.) See, e.g., 1104 at 2:7, 2:55-57, 3:27-28, 3:29-30, 4:32-35. See also, e.g., Ex. 1105, Fig. 46:21-32 (“As described above. the multi-television of the present invention is capable of receiving several broadcasting signals of the NTSC

32

broadcasting system, the PAL broadcasting system. and the SECAM broadcasting system. Furthermore. the multi-television is capable of automatically correcting a difference of the chrominance level of the signals received via each broadcasting system by programming the gain control data of each broadcasting system in a microcomputer. As a result. a user can properly view a program corresponding to video signals of a plurality of different broadcasting systems.”).

D. Ground 4: Claim 7, 8, 9 and 12 are obvious over Favrat in view of

Wilkie

Wilkie teaches a system suitable for the transfer of multimedia signals.

Therefore, a POSITA would be motivated to use concepts from Wilkie to enable

the transfer of multimedia signals in Favrat. It would have obvious for a POSITA

to incorporate Wilkie’s selectable driver circuit for converting a signal from single-

ended to differential if a subsequent demodulator required a differential signal.

(Id.) (Ex. 1113, Hashemi Dec., ¶ 56-59.)

Wilkie teaches a signal output circuit with a differential output terminal that

is selectable. (See, e.g., Ex. 1106, Wilkie, Abstract, “An apparatus for transmitting

an analog image signal representing an image over a bus including a driver circuit

which receives a single ended analog image signal from a media source and

provides a differential analog image signal and a switch circuit which selectively

33

provides the differential analog image signal to the bus in response to control

information;” FIG. 11B (below); see also Ex. 1113, Hashemi Dec., ¶ 60.)

(Ex. 1106, Wilkie, Fig. 11B.)

‘792 Patent - Claim 7 (Ex. 1101) Favrat (Ex. 1104) and Wilkie (Ex. 1106)

7. The television receiver of claim 1, wherein the signal output circuit provides


a first output signal and a second output signal corresponding to the digital output signals,

(Ex. 1113, Hashemi Dec., ¶ 55-60.) See the “a signal output circuit for receiving the digital output signals from the signal processor and for providing one or more output signals corresponding to the digital output signals” limitation of claim 1, above.

the first output signal and the second output signal being differential output

(Ex. 1113, Hashemi Dec., ¶ 55-60.) See also, e.g., 1106, Fig. 11B,

34

signals Abstract (“An apparatus for transmitting an analog image signal representing an image over a bus including a driver circuit which receives a single ended analog image signal from a media source and provides a differential analog image signal and a switch circuit which selectively provides the differential analog image signal to the bus in response to control information”).

corresponding to a digital television format.

(Ex. 1113, Hashemi Dec., ¶ 55-60.) Ex. 1104 at 4:53-54 (“DSP 64 processes the digital signals according to the television standard to which the input RF signal is encoded.”), 5:42-45, 6:6-7 . See, e.g., claim 2 (“said plurality of formats comprise an analog television format and a digital television format”).

‘792 Patent - Claim 8 (Ex. 1101) Favrat (Ex. 1104) 8. The television receiver of claim 7, further comprising:


a demodulator circuit for demodulating the first output signal and the second output signal according to the television signal format of the input RF signal, the demodulator circuit generating video and audio baseband signals corresponding to the format of the input RF signal

(Ex. 1113, Hashemi Dec., ¶ 62.) See, e.g., claim 1 (“a plurality of demodulators, each coupled to receive output signals from said signal processor, each of said demodulators for demodulating said digital output signals according to one of said formats of said input RF signal, each of said demodulators generating video and audio baseband signals corresponding to said format of said input RF signal.”), 5:42-44, Figure 2 (depicting the bank of demodulators 66 receiving the digital output signals from the

35

signal processor (DSP) 64.), 5:49-52, 5:59-62.

a decoder circuit coupled to decode the video and audio baseband signals for providing video and audio display signals corresponding to the digital television format.

(Ex. 1113, Hashemi Dec., ¶ 63.) See, e.g., 5:46-48 (“The video and audio baseband signals are usually coupled to video and audio decoders before being displayed or playback on a view screen.”), 6:6-7 , 1:55-57.

‘792 Patent - Claim 9 (Ex. 1101) Favrat (Ex. 1104) 9. The television receiver of claim 8, wherein the video and audio baseband signals comprise


a MPEG data stream and the decoder circuit comprises a MPEG decoder circuit.

(Ex. 1113, Hashemi Dec., ¶ 64.) See, e.g., 6:6-10 (“Digital demodulator 66 b operates to decode the incoming digital television signal. Typically, digital television signals are modulated in a VSB, QAM or COFDM scheme. Digital demodulator 66 b generates an MPEG data stream as output signals.”).

‘792 Patent - Claim 12 (Ex. 1101) Favrat (Ex. 1104) and Wilkie (Ex. 1106)

12. The television receiver of claim 1, wherein the signal output circuit comprises one or more output terminals, each of the one or more output terminals of the signal output circuit comprises a single-ended output terminal or a differential output terminal

(Ex. 1113, Hashemi Dec., ¶ 65.) See above discussion of ’792 patent, claims 1 and 7.

E. Ground 5: Claim 10 is obvious over Favrat in view of Vorenkamp

Vorenkamp teaches an integrated receiver with a tuner for converting a

received signal to a digital IF signal. (See, e.g., Ex. 1107, Vorenkamp, Abstract).

Therefore, a POSITA would be motivated to use concepts from Vorenkamp with

36

Favrat, which also teaches an integrated receiver with a tuner for converting a

received signal to a digital IF signal. (Ex. 1113, Hashemi Dec., ¶¶ 68-70.)

It would have been obvious to a POSITA to incorporate the Vorenkamp

VGA to provide automatic gain control (AGC) and improve the dynamic range of

the receiver. (See, e.g., Ex. 1108, Vorenkamp, 53:29-33 “The improved dynamic

range of the VGA compensates for increased variations in signal amplitude

caused by irregularities in the external differential filter 5430.”) (Ex. 1113,

Hashemi Dec., ¶¶ 68-70.)

37

(Ex. 1107, Vorenkamp, Fig. 5 and Fig. 83, annotation added.)

‘792 Patent - Claim 3 (Ex. 1101) Favrat (Ex. 1104) and Vorenkamp (Ex. 1107)

10. The television receiver of claim 1, further comprising:


a bandpass filter coupled to receive the intermediate frequency signal from the frequency conversion circuit and generate a filtered intermediate frequency signal; and

(Ex. 1113, Hashemi Dec., ¶ 67.) See, e.g., Ex. 1104 , claim 17, “applying a first filter function to said intermediate signals, said first filter function being an anti-aliasing filter and having a center frequency.”), Figure 2; id. at 4:3-7 (“Next, TV receiver 50 includes multi-standard channel filter 58 for filtering and processing the intermediate signals from tuner 54. Multi-standard channel filter 58 includes an anti-aliasing filter 60, an analog-to-digital converter (ADC) 62 and a digital signal processor (DSP) 64.”), 4:20-25 4:31-33.

a variable gain amplifier coupled to receive the filtered intermediate frequency signal and provide the amplified, filtered intermediate frequency signal to the analog-to-digital converter.

(Ex. 1113, Hashemi Dec., ¶¶ 68-71.) See, e.., Ex. 1107, 107:11-12 (“The signal at input IF IN is fed into a variable gain amplifier (VGA) 8317.”). See also, e.g., Ex. 1107, Figs. 5 and 83 (illustrating variable gain amplifier (VGA) between a bandpass filter (BPF) and an analog-to-digital converter (ADC)), 53:29-33.

F. Ground 6: Claims 13-15 and 18 is obvious over Favrat in view of

Oku

Oku and Favrat both teach a multi-standard television receiver. Therefore, a

POSITA would be motivated to use concepts from Oku in Favrat’s “signal output

38

circuit.” It would have been obvious to a POSITA to incorporate Oku’s driver

circuits for interfacing with a subsequent demodulator and/or decoder. (Ex. 1113,

Hashemi Dec., ¶ 74.)

Many of the challenged claims recite the different permutations of these

“desired output signals.” (See, e.g., id. at claim 13.) Converting an output signal

from one desired output form to another is not patentable. A person of ordinary

skill in the art (“POSITA”) would know that a digital-to-analog converter

(“DAC”) would be necessary if the desired output format was analog instead of

digital. (Ex. 1113, Hashemi Dec. ¶ 75). Likewise, a POSITA would know that a

single to differential-ended converter was necessary to convert a single-ended

output to a differential-ended output, if a differential-ended output was desired.

(See, e.g., Ex. 1113, Hashemi Dec. ¶ 56-58, 83). Similarly, a POSITA would

know that a parallel-to-serial converter (i.e., “serializer”) was necessary if the

desired output format was serial rather than parallel. (See, e.g., Ex. 1113, Hashemi

Dec. ¶ 100-101). Such use of known elements in such predictable ways is

obvious. KSR Intern. Co. v. Teleflex Inc., 550 U.S. 398, 421 (2007). All of the

claimed options are well within the grasp of a POSITA, as evidenced by the

legions of prior art references using these options.

‘792 Patent - Claim 13 (Ex. 1101) Favrat (Ex. 1104) and Oku (Ex. 1108)

13. The television receiver of claim 1, wherein the signal output circuit

(Ex. 1113, Hashemi Dec. ¶ 72.) See above discussion of ‘792 patent,

39

comprises: claim 1. a first digital-to-analog converter coupled to receive digital output signals from the signal processor and convert the digital output signals to analog output signals;

(Ex. 1113, Hashemi Dec. ¶ 73.) See, Ex. 1104, claim 3 (“a digital-to-analog converter coupled between said signal processor and a first one of said plurality of demodulators, said digital-to-analog converter converting said digital output signals to an analog format”), 5:54-58 (“In cases where analog demodulator 66a receives analog input signals only, a digital-to-analog converter (DAC) (not shown) can be included between the output terminal of DSP 64 and the input terminal of analog demodulator 66a.”).

a first driver circuit for driving the analog output signals from the first digital-to-analog converter onto a first output terminal;

(Ex. 1113, Hashemi Dec. ¶ 74-76.)

Ex. 1108 at Figures 1, 4, 6-7, 9-17; id. at 2:59-63 (“An object of the present invention is to solve the above problems, facilitate provisions to broadcasted variety of picture formats and realize simultaneous reception of an analog broadcast.), 7:24-32, 7:58-62, 8:45-58, 9:18-40, 12:58-62.

a second driver circuit for driving the analog output signals from the first digital-to-analog converter onto a second output terminal;

(Ex. 1113, Hashemi Dec. ¶ 77.)

40

Ex. 1108, Oku, Fig. 2 and 4.

a second digital-to-analog converter coupled to receive digital output signals from the signal processor encoding audio information and convert the digital output signals to analog output signals; and

(Ex. 1113, Hashemi Dec. ¶ 78.) See, Favrat, claim 3 (“a digital-to-analog converter coupled between said signal processor and a first one of said plurality of demodulators, said digital-to-analog converter converting said digital output signals to an analog format”).

a third driver circuit for driving the analog output signals from the second digital-to-analog converter onto a third output terminal,


Ex. 1108, Oku, Figs. 2 and 4.

wherein the first and second output terminals provide signals indicative of video and audio information encoded in the input RF signal and the third output terminal provides signals indicative of audio information encoded in the input RF signal.

(Ex. 1113, Hashemi Dec. ¶ 80.) See above discussion of ‘792 patent, claim 4. See also Ex. 1104 at 5:49-52 (… “demodulators 66 include a demodulator for analog television signals 66 a …”), 5:59-62 (“Analog demodulator 66a provides three output signals: a Composite Video Baseband Signal (CVBS) containing the video information, and audio 1 and audio 2 containing the audio information.”).

41


14. The television receiver of claim 13, wherein the first driver circuit comprises

(Ex. 1113, Hashemi Dec. ¶ 81.) See above discussion of ‘792 patent, claim 13.

a single-ended driver circuit for driving analog output signals corresponding to an analog television format, the analog output signals being video baseband signals;

(Ex. 1113, Hashemi Dec. ¶ 81.) Ex. 1108 at Figures 2 and 4; Ex. 1104 at 5:49-52 (… “demodulators 66 include a demodulator for analog television signals 66 a …”), 5:59-62 (“Analog demodulator 66a provides three output signals: a Composite Video Baseband Signal (CVBS) containing the video information, and audio 1 and audio 2 containing the audio information.”).

and the third driver circuit comprises a single-ended driver circuit for driving analog output signals corresponding to the analog television format, the analog output signals being audio baseband signals.

(Ex. 1113, Hashemi Dec. ¶ 81.) Ex. 1108 at Figures 2 and 4; Ex. 1104 at 5:49-52 (… “demodulators 66 include a demodulator for analog television signals 66 a …”), 5:59-62 (“Analog demodulator 66a provides three output signals: a Composite Video Baseband Signal (CVBS) containing the video information, and audio 1 and audio 2 containing the audio information.”).


15. The television receiver of claim 13, wherein the second driver circuit comprises

(Ex. 1113, Hashemi Dec. ¶ 82-83.) See above discussion of ‘792 patent, claim 13.

a differential output driver circuit for driving analog output signals corresponding to a digital television format, the analog output signals being DTV low-IF signals, and

(Ex. 1113, Hashemi Dec. ¶ 82-83.) Ex. 1108 at Figures 2 and 4; Ex. 1104 at 5:49-52 (“… demodulators 66 include a demodulator for analog television signals 66 a, a demodulator for digital television signals 66 b and a demodulator 66 c for digital data channels.”); 6:6-7 (“Digital demodulator 66b operates to decode the

42

incoming digital television signal.”). wherein the second output terminal comprises a first differential output terminal and a second differential output terminal.

(Ex. 1113, Hashemi Dec. ¶ 82-83.) Ex. 1108 at Figures 2 and 4; Ex. 1104 at 5:49-52 (“… demodulators 66 include a demodulator for analog television signals 66 a, a demodulator for digital television signals 66 b and a demodulator 66 c for digital data channels.”); 6:6-7 (“Digital demodulator 66b operates to decode the incoming digital television signal.”).


18. The television receiver of claim 1, wherein the signal output circuit comprises:


a first digital-to-analog converter coupled to receive digital output signals from the signal processor and convert the digital output signals to analog output signals;

(Ex. 1113, Hashemi Dec. ¶ 85.) See, Ex. 1104, claim 3 (“a digital-to-analog converter coupled between said signal processor and a first one of said plurality of demodulators, said digital-to-analog converter converting said digital output signals to an analog format”); id. at 5:54-58 (“In cases where analog demodulator 66a receives analog input signals only, a digital-to-analog converter (DAC) (not shown) can be included between the output terminal of DSP 64 and the input terminal of analog demodulator 66a.”).

a first driver circuit for driving the analog output signals from the first digital-to-analog converter onto a first output terminal;


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Ex. 1108, Oku, Figs. 2 and 4, see also id. at Figures 1, 4, 6-7, 9-17; id. at 2:59-63 (“An object of the present invention is to solve the above problems, facilitate provisions to broadcasted variety of picture formats and realize simultaneous reception of an analog broadcast.).

a second driver circuit for driving the analog output signals from the first digital-to-analog converter, the second driver circuit comprising a differential output driver circuit having a first differential output terminal and a second differential output terminal, the first differential output terminal being coupled to the first output terminal and the second differential output terminal being coupled to a second output terminal;

(Ex. 1113, Hashemi Dec. ¶ 87.) Ex. 1108, Oku, Figs. 2 and 4, see also id. at Figures 1, 4, 6-7, 9-17; id. at 2:59-63 (“An object of the present invention is to solve the above problems, facilitate provisions to broadcasted variety of picture formats and realize simultaneous reception of an analog broadcast.).

a second digital-to-analog converter coupled to receive digital output signals from the signal processor encoding audio information and convert the digital output signals to analog output signals; and

(Ex. 1113, Hashemi Dec. ¶ 88.) See, Favrat, claim 3 (“a digital-to-analog converter coupled between said signal processor and a first one of said plurality of demodulators, said digital-to-analog converter converting said digital output signals to an analog format”).

a third driver circuit for driving the analog output signals from the second digital-to-analog converter onto the second output terminal,


(Ex. 1108, Oku, Figs. 2 and 4.)

wherein the first and second output terminals provide differential output signals indicative of video and audio

(Ex. 1113, Hashemi Dec. ¶ 90.) See above discussion of ‘792 patent, claim 4; see also Ex. 1104 at 5:49-52

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information encoded in the input RF signal when the input RF signal has a digital television signal format; and

(… “demodulators 66 include a demodulator for analog television signals 66 a …”), 5:59-62 (“Analog demodulator 66a provides three output signals: a Composite Video Baseband Signal (CVBS) containing the video information, and audio 1 and audio 2 containing the audio information.”).

the first output terminal provides video information encoded in the input RF signal and the second output terminal provides signals indicative of audio information encoded in the input RF signal when the input RF signal has an analog television signal format

(Ex. 1113, Hashemi Dec. ¶ 90.) See above discussion of ‘792 patent, claim 4; see also Ex. 1104 at 5:49-52 (… “demodulators 66 include a demodulator for analog television signals 66 a …”), 5:59-62 (“Analog demodulator 66a provides three output signals: a Composite Video Baseband Signal (CVBS) containing the video information, and audio 1 and audio 2 containing the audio information.”).

G. Ground 7: Claims 16, 17 and 19 are obvious over Favrat in view

of Oku

Oku and Favrat both teach a multi-standard television receiver. Gray teaches

a suitable interface for analog multimedia signals. Therefore, a POSITA would be

motivated to use concepts from Oku and Gray in Favrat’s “signal output circuit.”

It would have been obvious to incorporate Gray’s low pass filter with Oku’s

driver circuit for removing any of the artifacts produced by the DAC before

interfacing with a subsequent demodulator and/or decoder. (Ex. 1113, Hashemi

Dec., 91-94.)

‘792 Patent - Claim 16 (Ex. 1101)

Favrat (Ex. 1104), Oku (Ex. 1108) and

Gray (Ex. 1109)

45

16. The television receiver of claim 13, wherein the signal output circuit further comprises:

(Ex. 1113, Hashemi Dec. ¶ 91-94.) See above discussion of ‘792 patent, claim 13. See also Ex. 1108 at Figures 1, 4, 6-7, 9-17; id. at 2:59-63.

a low pass filter coupled between the first digital-to-analog converter and the first and second driver circuits, the low pass filter providing low pass filtering function.

(Ex. 1113, Hashemi Dec. ¶ 91-94.) See, e.g., Ex. 1109, Gray, 15:21-22 (“A low pass filter (111) removes any of the artifacts produced during the conversion from digital to analog.”); Figure 9.

‘792 Patent - Claim 17 (Ex. 1101)


Gray (Ex. 1109) 17. The television receiver of claim 13, wherein the signal output circuit further comprises:

(Ex. 1113, Hashemi Dec. ¶ 95-96.) See above discussion of ‘792 patent, claim 13; see also Ex. 1108 at Figures 1, 4, 6-7, 9-17; id. at 2:59-63.

a low pass filter coupled between the second digital-to-analog converter and the third driver circuit, the low pass filter providing low pass filtering function

(Ex. 1113, Hashemi Dec. ¶ 95-96.) See, e.g., Ex. 1109, Gray, 15:21-22 (“A low pass filter (111) removes any of the artifacts produced during the conversion from digital to analog.”) ; Figure 9.

‘792 Patent - Claim 19 (Ex. 1101)


Gray (Ex. 1109) 19. The television receiver of claim 18, wherein the signal output circuit further comprises:

(Ex. 1113, Hashemi Dec. ¶ 97-98.) See above discussion of ‘792 patent, claim 13; see also Ex. 1108 at Figures 1, 4, 6-7, 9-17; id. at 2:59-63.

a low pass filter coupled between the first digital-to-analog converter and the first and second driver circuits, the low pass filter providing low pass filtering function.

(Ex. 1113, Hashemi Dec. ¶ 97-98.) See, e.g., Ex. 1109, Gray, 15:21-22 (“A low pass filter (111) removes any of the artifacts produced during the conversion from digital to analog.”) ; Figure 9.

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H. Ground 8: Claims 20-23 are obvious over Favrat in view of Oku and further in view of Eglit and Wilkie

Oku and Favrat both teach a multi-standard television receiver. Eglit and

Wilkie teach suitable interfaces for multimedia signals. (Ex. 1113, Hashemi Dec. ¶

100-101.)

Therefore, a POSITA would be motivated to use concepts from Oku, Eglit

and Wilkie in Favrat’s “signal output circuit” to enable the transfer of multimedia

signals in Favrat. (Ex. 1113, Hashemi Dec. ¶ 100-101.)

‘792 Patent - Claim 20 (Ex. 1101)

Favrat (Ex. 1104), Oku (Ex. 1108), Eglit (Ex. 1110) and

Wilkie (Ex. 1106) 20. The television receiver of claim 1, wherein the signal output circuit comprises:

(Ex. 1113, Hashemi Dec. ¶ 99.) See, e.g., Ex. 1104, Favrat, as cited in section VI.A.1 above, with respect to claim 1.

a first serializer circuit coupled to receive the digital output signals from the signal processor and convert the digital output signals to a serial digital data stream;

(Ex. 1113, Hashemi Dec. ¶ 100-102.)

Ex. 1110, Eglit, Fig. 6; id. at claim 4 (“… a processor, coupled to said computer data bus, for retrieving said compressed motion video data from said memory, and serializing said compressed motion video data to produce serialized compressed motion video data …”).

a first driver circuit comprising a differential output driver for driving the

(Ex. 1113, Hashemi Dec. ¶ 103.)

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serial digital data stream from the first serializer onto a first output terminal and a second output terminal;

(Ex. 1106, Wilkie, Fig. 11B); see also Ex. 1106, Wilkie at Abstract (“An apparatus for transmitting an analog image signal representing an image over a bus including a driver circuit which receives a single ended analog image signal from a media source and provides a differential analog image signal and a switch circuit which selectively provides the differential analog image signal to the bus in response to control information”).

a first digital-to-analog converter coupled to receive digital output signals from the signal processor encoding audio information and convert the digital output signals to analog output signals; and

(Ex. 1113, Hashemi Dec. ¶ 104.)

Ex. 1108, Oku, Fig. 2; Ex. 1108 at Figures 2 and 4.

a second driver circuit for driving the analog output signals from the first digital-to-analog converter onto a third output terminal,

(Ex. 1113, Hashemi Dec. ¶ 105.)

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Ex. 1108, Oku, Fig. 2; Ex. 1108 at Figures 2 and 4.

wherein the first and second output terminals provide differential output signals indicative of video and audio information encoded in the input RF signal when the input RF signal has a digital television signal format and

(Ex. 1113, Hashemi Dec. ¶ 106-7.) See, e.g., Ex. 1104, Favrat, as described in section VI.C.2 above, with respect to claim 7, see also, e.g., Ex. 1104, Favrat, as cited in section VI.A.7 above, with respect to claim 9. See also Ex. 1104 at 4:53-54 (“DSP 64 processes the digital signals according to the television standard to which the input RF signal is encoded.”), 5:49-52 5:59-62.

provide differential output signal indicative of video information when the input RF signal has an analog television signal format; and

(Ex. 1113, Hashemi Dec. ¶ 106-7.) See, e.g., Ex. 1104, Favrat, as cited in section VI.A.4 above, with respect to claim 4.

the third output terminal provides signals indicative of audio information encoded in the input RF signal when the input RF signal has an analog television signal format.

(Ex. 1113, Hashemi Dec. ¶ 106-7.) See, e.g., Ex. 1104, Favrat, as cited in section VI.A.4 above, with respect to claim 4. See also Ex. 1106, Wilkie at Abstract (“An apparatus for transmitting an analog image signal representing an image over a bus including a driver circuit which receives a single ended analog image signal from a media source and provides a differential analog image signal and a switch circuit which selectively provides the differential analog image signal to the bus in response to control information”); id. at FIG. 11B.)

‘792 Patent - Claim 21 (Ex. 1101) Favrat (Ex. 1104), Oku (Ex. 1108),

Eglit (Ex. 1110) and Wilkie (Ex. 1106)

49



the first, second and third output terminals of the signal output circuit are coupled to a demodulator-decoder circuit, the demodulator-decoder circuit demodulating the serial digital data stream when the data stream corresponds to a digital television format:

(Ex. 1113, Hashemi Dec. ¶ 109.) See above discussion of ‘792 patent, claim 8; see also 1104 at 5:49-52 (“… demodulators 66 include a demodulator for analog television signals 66 a, a demodulator for digital television signals 66 b and a demodulator 66 c for digital data channels.”); 6:6-7 , 6:6-10, 5:45-58, 1:55-57 .

the demodulator-decoder circuit decoding the serial digital data stream when the data stream corresponds to an analog television format:


‘792 Patent - Claim 22 (Ex. 1101)


Wilkie (Ex. 1106) 22. The television receiver of claim 20, wherein the signal output circuit further comprises:


a second digital-to-analog converter coupled to receive the digital output signals from the signal processor and convert the digital output signals to analog output signal; and

(Ex. 1113, Hashemi Dec. ¶ 112.)

Ex. 1108, Oku, Fig. 2; Ex. 1108 at Figures 1, 4, 6-7, 9-17; id. at 2:59-63 (“An object of the present invention is to solve the above problems, facilitate provisions to broadcasted variety of picture formats and realize

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simultaneous reception of an analog broadcast.).

a third driver circuit for driving the analog output signals from the second digital-to-analog converter onto a fourth output terminal,

(Ex. 1113, Hashemi Dec. ¶ 113.)

x. 1108 at Figures 2 and 4.

wherein the fourth output terminal provides signals indicative of video information encoded in the input RF signal when the input RF signal has an analog television signal format.

(Ex. 1113, Hashemi Dec. ¶ 114.) See, e.g., Ex. 1104, Favrat, as cited in section VI.A.4 above, with respect to claim 4; see also Ex. 1104 at 5:49-52 (… “demodulators 66 include a demodulator for analog television signals 66 a …”), 5:59-62 (“Analog demodulator 66a provides three output signals: a Composite Video Baseband Signal (CVBS) containing the video information, and audio 1 and audio 2 containing the audio information.”)

‘792 Patent - Claim 23 (Ex. 1101)


Wilkie (Ex. 1106) 23. The television receiver of claim 20, wherein the signal output circuit further comprises:


a second serializer circuit coupled to receive the digital output signals from the signal processor and convert the digital output signals to a serial digital data stream; and

(Ex. 1113, Hashemi Dec. ¶ 116.)

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Ex. 1110, Eglit, Fig. 6; id. at Figure 6 (portion below); id. at claim 4 (“… a processor, coupled to said computer data bus, for retrieving said compressed motion video data from said memory, and serializing said compressed motion video data to produce serialized compressed motion video data …”).

a third driver circuit comprising a differential output driver for driving the serial digital data stream from the second serializer onto a fourth output terminal and a fifth output terminal,

(Ex. 1113, Hashemi Dec. ¶ 117.)

Ex. 1106, Wilkie, Fig. 11B; Ex. 1106, Wilkie at Abstract (“An apparatus for transmitting an analog image signal representing an image over a bus including a driver circuit which receives a single ended analog image signal from a media source and provides a differential analog image signal and a switch circuit which selectively provides the differential analog image signal to the bus in response to control information”); id. at FIG. 11B; Ex. 1108 at Figures 2 and 4.

wherein the first and second driver circuits drive the serial digital data stream corresponding to a digital television format and the fourth and fifth driver circuits drive the serial digital data stream corresponding to an analog television format.

(Ex. 1113, Hashemi Dec. ¶ 118.) See, e.g., Ex. 1104, Favrat, as cited in section VI.A.2 above, with respect to claim 2. See also Ex. 1104 at claims 1 and 2; Ex. 1108 at Figures 2 and 4.

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VI. CONCLUSION

For the reasons set forth above, Peititioner has established a reasonable

likelihood that the challenged claims are invalid. Favrat anticipates all of the

elements of challenged claims 1, 2, 4, 5, 11 and 24-29. The combination of Favrat

and Arambepola renders claim 3 obvious. The combination of Favrat and Yang

renders claim 6 obvious. The combination of Favrat and Wilkie renders claims 7,

8, 9 and 12 obvious. The combination of Favrat and Vorenkamp renders claim 10

obvious. The combination of Favrat and Oku renders claims 13-15, 18 and 22

obvious. The combination of Favrat, Oku and Gray renders claims 16, 17 and 19

obvious. The combination of Favrat, Oku, Eglit and Wilkie renders claims 20-23

obvious. Petitioner therefore requests institution of an inter partes review to cancel

claims 1–29 of the ’792 patent.

Dated: January 28, 2015

Respectfully submitted, /Thomas J. Wimbiscus/ Thomas J. Wimbiscus Registration No. 36,059 McAndrews, Held & Malloy, Ltd. 500 West Madison Street, 34th Floor Chicago, Illinois 60661 Office: (312) 775-8000 Fax: (312) 775-8100

[email protected] Lead Counsel for Patent Owner

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CERTIFICATE OF SERVICE

I hereby certify that, on January 28, 2015, a true and correct copy of the

following materials:

PETITION FOR INTER PARTES REVIEW OF 7,265,792 UNDER

35 U.S.C. § 312 AND 37 C.F.R. § 42.104 Exhibits 1101–1139 Table of Exhibits Fee Authorization Power of Attorney

was served via Federal Express on the following attorneys of record as listed on

PAIR:

Law Office of Andrei D. Popovici, P.C.ATTN: Andrei Popovici 4030 Moorpark Ave., Suite 108 San Jose, CA 95117

Genevieve Vose Wallace Floyd G. Short Parker C. Folse Susman Godfrey LLP 1201 Third Avenue, Suite 3800 Seattle, Washington 98101

MCANDREWS HELD & MALLOY /Thomas J. Wimbiscus/ Thomas J. Wimbiscus

Telephone: 312-775-8000 Registration No. 36,059 Facsimile: 312-775-8100 CUSTOMER NUMBER: 23446 Date: January 28, 2015

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