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UNIT-II

VHDL MODELLING

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1. Explain the VLSI Circuit Design Process steps

Ans) It involves the following steps.

1. System specification 2. Functional design 3. Logic design 4. Circuit design 5. Physical design 6. Design verification 7. Fabrication 8. Packaging, testing, and debugging

The design process, at various levels, is usually evolutionary in nature. It starts with a given set of requirements. Initial design is to be developed and test impact analyst must be considered. The Y-chart (first introduced by D. Gajski) is shown in below figure 2.1 illustrates a design flow for most logic chips, using design activities on the three different axes (domains). Y chart of

three major domains, they are: Figure 2.1 VLSI circuit design process

Behavioral domain: It specifies the software implementation of systems

functionality. Structural domain: It specifies the how modules are connected together to effect the

prescribed behavior. Geometrical layout domain: It is physical design. It specifies the layout used to build

the system according to architectures idea. 2). Explain various steps involved in design process of Digital System?

Ans) A system is set of interdependent modules

(subsystem) forming integrated package. The main characteristics of a system are

Sturcture: Defined by parts and their interconnectivity Behaviour: It involves inputs, processing, outputs and their response. Interconnectivity: Functional as well as structural relationship in between them.

♠ Simple systems can be designed by one person using ad hoc methods Real-world systems are design by teams

♠ require a systematic modular design Figure 2.2: Y- Chart methodology decompose system to define components to be designed

♠ define information needed and produced

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♠ define relationships between components dependencies, sequences ♠ EDA tools use

The following Figure 2.3 shows the Digital system design process steps

Figure 2.3 Digital system design process steps

Figure 2.3 Example of Digital System

3) Explain the various steps involved in the design process of IC? Ans) Product requirement: First step in this level is to understand the market/client

requirement. Whether the chip that is going to design is to be used for specific purpose or

for generic purpose. This decides the features and c omponents of the chip.

Simulation at system level: Block diagram explanation of the chip is done in this step, i.e it

involves the architecture of the IC. This step decides which processor has to be used, the interfaces

to be included,sensors,cameras and their compatibility to each other etc. But it is not accurate.

Simulation at RTL level: Here coding of all the blocks is done in higher definition language like

VHDL or Verilog. It is very accurate funcionally and limitation is only functional level.

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Figure 2.4 IC Design process.

Simulation at Gate-level: Synthesizing the RTL using synopsys design compiler or cadence tool to

give out a net list. In this technology library of gates are used. It has the advantage of actual physical

design and drawback is time consuming.

Placement, Floor planning and Routing: Gate net list is taken as input to do physical design.

Every chip has a floor plan consists plan of where to place all input/output, memory elements and

all other components in the circuit on IC. Magna and cadence tools are used for layouting. The

circuit is again re-Synthesized. This is called physical synthesize.

Post layout Simulation: It is very important step. Again formal verification done at this stage that

whether the circuit is performing at specified frequency and it follows the required specification

standards or not. Once verification (Post layout Simulation) completed chip is sent for

manufacturing.

Tape out: After manufacturing chip is tested immediately after putting on PCBs, if there are any

faulty parts are there they are discarded.

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4) Define Simulation? Explain the purpose of simulation in design process? (Or) Define

simulation? Explain about Gate-level simulation, Behavioral simulation and Functional

simulation. Ans)

Simulation: It is a part of ‘verification’. The purpose is

to verify that the circuit works as desired. i.e it

describes the behavior of the circuit in terms of i/p and

o/p signals. The operation of digital circuits can be

verified fastly and accurately using logic simulation. We

have two types of verification techniques Functional

and Timing.

When all functions of circuit are verified then it

is referred as Functional simulation.

When there is involvement of timing behavior of

the circuit by including estimated delays, it is Figure 2.5 Simulation

referred as Timing simulation.

Simulation detects functional errors in the design without actually constructing the circuit.

If the errors are detected then they can be corrected by modifying the vHDL code. So

without fabricating hardware, the design is finalized.

5) Explain different stages of Simulation in Chip development cycle? (or) Explain about

Simulation modes in detailed.

Ans) In chip development cycle Simulation is carried out in different stages as follows

a) Behavioural Simulation: This simulation models the subsystems of a system as black box with

input and output. Here VHDL or Verilog is used to model.

b) Functional Simulation: Here some fixed value delay is set and simulation is done. Once

simulation assumed or predicted that the system will work correctly then actual timing

performance is checked.

c) Gate level Simulation: This simulation is also used to check timing performance.

d) Switch level Simulation: In this simulation transistors are modeled as ON or OFF switches. This

provides accurate timing.

e) Transistor level Simulation: This simulation level is most accurate but complex process. These

simulators take care of voltages, currents, resistances and electrical behavior of various parts of the

circuit.

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Figure 2.6 Simulation Modes

6) How many types of simulation methods are in VHDL? Explain them with suitable

examples

Ans) Simulation Types: There are two types of simulations are available

o Oblivious Simulation

o Event driven Simulation

Oblivious Simulation:

Simulation program converts the input circuit description to machine readable tabular

form.

Need a tabular netlist for Oblivious simulation.

Simulate fixed time intervals

Update table values at each level. Example

Figure 2.7 Oblivious Simulation

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Event driven Simulation

It is more complex but effective method of simulation.

It evaluates circuit only when events are occur.

It offers a faster simulation for digital systems.

VHDL is an event driven simulation

Example:

Figure 2.8 Event-driven Simulation

7) Explain Logic Synthesis process with neat diagrams.

Ans)

Figure 2.9 Logic Synthesis process

Synthesis is a method of converting higher level of abstraction to lower level of abstraction

The tool (Design compiler is RTL Synthesis tool bye synopsys) converts Register Transfer

Level (RTL) Description to gate level net lists.

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RTL Source: The input to synthesis process is RTL VHDL Description.

Technology Libraries: These libraries hold all information necessary for synthesis tool to

create netlist. They contain

Local function of an ASIC cell

Area of the cell

Input to Output timing of the cell

Constraints

Timing checks

Graphical symbol of the cell

Constraints: These are used to control the

output of optimization and mapping process.

The constraints include area, timing, power

and testability. There are several constraints

are present. They are Timing constraints, Clock

constraints, Attributes, Load, Drive and Arrival

time Figure 2.10 Constraints

Timing constraints: Typical uses for timing constraints are to specify maximum delays for

particular paths in a design. For instance, a typical timing constraint is the required time for

an output port. The timing constraints guides the optimization and mapping to produce a

netlist that meets the timing constraint. A typical delay constraint is given by

set_attribute-port data_out-name required_time-value 31

Clock constraints: To add a required time constraint to every flipflop input with the value of

a clock cycle. The resulting design would be optimized to meet the one cycle timing

constraint.

A typical Clock constraint is given by set_attribute-port clk-name clock_cycle-value 31, it

sets the clock cycle constraint on port clk with a value 31 library units.

Attributes: Attributes are used to specify the design environment. For instance, attributes

specify the loading that the output devices have to drive. All of this information is taken into

account by the static timing analyzer to calculate the timing through the circuit paths.

Load: Each output can specify a drive capability that determines how many loads can be

driven within a particular time. Each input can have a load value specified that determines

how much it will slow a particular driver. The load attribute specifies how much capacitive

load exists on a particular output signal. A typical Load constraint is given by set_attribute-

port xbus-name input_load-value 31, it specifies that signal xbus will load the driver of

this signal with 31 library units of load.

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Drive: The drive attribute specifies the resistance of the driver, which controls how much

current it can source and also specifies in the units of technology library. A typical Drive

constraint is given by set_attribute-port ybus-name output_drive-value 31, it specifies

that signal ybus has 31 library units of drive capability.

Arrival time: Some synthesis tools uses static timing analyzer during synthesis process to

check that the logic being created matches the timing constraints the user has specified. For

large designs if test vectors are available then static timing analysis is used. static timing

analyzer traces each path in the design and keeps of timing from a clock edge or an input. A

designer can be verify all the critical paths that are with in the required specifications are

not. If they are with in the required specifications then static timing analyzer shows entire

path to the designer to fix the problem.

Netlist: Logic synthesis produces a database with instructions on how to fabricate a

physical piece of digital hardware. Netlist is list of components and their interconnections

derived from digital system model described in VHDL.

8) Explain the blocks present inside a Logic Synthesizer.

Ans) Once behavioural HDL model is complete, two items are required to process

1. Logic Synthesizer (software and documentation): It performs translation, logic minimization &

optimization, and mapping to gate functions.

2. Cell library or target Library: contains logic cells such as NAND gate etc.

A) TRANSLATION:

The RTL description is translated to an Unoptimized boolean description consists of

premitive gates such as AND,OR,FLIPFLOPS and LATCHES.

All IF,CASE,LOOP statements,signal assignments are converted into their boolean

equivqlents.

B) LOGIC MINIMIZATION & OPTIMIZATION:

Logic minimization involves reduced number of literals which saves silicon area, it can be

understood by karnaugh map.

Logic optimization process converts an unoptimized boolean description into an optimized

one.

For simplification it uses a series of FLATTERING, FACTORING, SUBSTITUTION and

ELEMINATION steps.

FLATTERING:

It is the process of converting the unoptimized boolean description to a PLA format.

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It creates a flat signal representation of only two levels as AND level, OR level by removing

intermediate states.

PLA has simple structure and well known algorithms to perform boolean optimization.

Flattering designs are very big and slower Design

Example:

Original equations

a=b and c;

b= x or (y and z);

c=q or w;

After Flattering

a=(x and q)or(q and y and z)or(w and x)or

(w and y and z)

FACTORING:

It is the process of adding intermediate terms to add structure to a description. It is

opposite of Flattering.

It produces delays by adding of logic structure. It is smaller and slower than Flattering

Example:

Original equations

x= a and b or a and d;

y= z or b or d;

After Factering

x=a and q;

y=z or q;

q=b or d;

C) MAPPING:

Mapping process takes the logically optimized boolean description created by optimization

step and uses logical and timing information from a technology library to build a netlist.

Netlist is targeted to the user’s needs for area and speed.

Many netlists are functionally same but vary widely in speed and area.

9) Write short notes on following A) Functional Gate-Level Verification B) Place and Route C) Post Layout Timing Simulation D) Static Timing E) Major Netlist Formats

Ans) A) Functional Gate-Level Verification:

A designer must do quick check on output of a synthesis tool to check the design produced by synthesis tool is functionally correct or not..

If design matches, then synthesis tool did not produce logic mismatches, if it is not matches then designer needs to debug VHDL RTL description to see what is in description.

If design has been successfully verified then it passed to PLACE and ROUTE tools to implement the design.

B) Place and Route: These tools are used to implement the design in target technology device by taking design

netlist.

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Some tools are allow to specify the placement of large parts of design which is called Floor planning.

After placing and routing all the cells, By the output of these tools data can be used to implement the chip.

Figure 2.11 Place and Route tools

C) Post Layout Timing Simulation:

After place and route process completion, again functional and timing verification is done. If design is properly structured then same vectors used for RTL simulation are used for

Post layout simulation. D) Static Timing:

For large designs if test vectors are available then static timing analysis is used.

static timing analyzer traces each path in the design and keeps of timing from a clock edge

or an input.

A designer can be verify all the critical paths that are with in the required specifications are

not. If they are with in the required specifications then static timing analyzer shows entire

path to the designer to fix the problem.

E) Major Netlist Formats:

Verilog

VHDL

EDIF(Electronic Design Interchange Format): EDIF (Electronic Design Interchange

Format) is a vendor-neutral format in which to store Electronic netlists and schematics. It was

one of the first attempts to establish a neutral data exchange format for the electronic design

automation(EDA) industry. The goal was to establish a common format from which the

proprietary formats of the EDA systems could be derived. When customers needed to transfer

data from one system to another, it was necessary to write translators from one format to other.

As the number of formats (N) multiplied, the translator issue became an N-squared problem.

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The expectation was that with EDIF the number of translators could be reduced to the number

of involved systems.

DEF(Design Exchange Format): A specification for representing logical connectivity

and physical layout of and integrated circuit in ASCII format. A DEF file is used to

describe all the physical aspects of a design, including Die size, Connectivity , Physical

location of cells and macros on the chip. It contains floor-planning information such as

Standard cell rows, groups Placement and routing blockages, Placement constraints,

Power domain boundaries. It also contains the physical representation for pins, signal

routing, and power routing, including rings and stripes.

SPICE(Simulation Program with IC Emphasis): SPICE is a general-purpose, open

source analog electronic circuit simulator. It is a program used in integrated circuit and

board-level design to check the integrity of circuit designs and to

predict circuit behavior.

SDF(Standard Delay Format): Standard Delay Format (SDF) is an IEEE standard for

the representation and interpretation of timing data for use at any stage of an electronic

design process. It finds wide applicability in design flows, and forms an efficient bridge

between Dynamic timing verification and Static timing analysis. It was originally

developed as an OVI standard, and later modified into the IEEE format. Technically only

the SDF version 4.0 onwards are IEEE formats. It is an ASCII format that is represented

in a tool and language independent way and includes path delays, timing constraint

values, interconnect delays and high level technology parameters. It has usually two

sections: one for interconnect delays and the other for cell delays. SDF format can be

used for back-annotation as well as forward-annotation.

10. What is the importance of constraints in VHDL? Explain various constraints? Ans)

Constraints: These are used to control the output of optimization and mapping process.

The constraints include area, timing, power and testability. There are several constraints

are present. They are Timing constraints, Clock constraints, Attributes, Load, Drive and

Arrival time

Timing constraints: Typical uses for timing constraints are to specify maximum delays for

particular paths in a design. For instance, a typical timing constraint is the required time for

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an output port. The timing constraints guides the optimization and mapping to produce a

netlist that meets the timing constraint. A typical delay constraint is given by

set_attribute-port data_out-name required_time-value 31

Clock constraints: To add a required time constraint to every flipflop input with the value of

a clock cycle. The resulting design would be optimized to meet the one cycle timing

constraint.

A typical Clock constraint is given by set_attribute-port clk-name clock_cycle-value 31, it

sets the clock cycle constraint on port clk with a value 31 library units.

Attributes: Attributes are used to specify the design environment. For instance, attributes

specify the loading that the output devices have to drive. All of this information is taken into

account by the static timing analyzer to calculate the timing through the circuit paths.

Load: Each output can specify a drive capability that determines how many loads can be

driven within a particular time. Each input can have a load value specified that determines

how much it will slow a particular driver. The load attribute specifies how much capacitive

load exists on a particular output signal. A typical Load constraint is given by set_attribute-

port xbus-name input_load-value 31, it specifies that signal xbus will load the driver of

this signal with 31 library units of load.

Drive: The drive attribute specifies the resistance of the driver, which controls how much

current it can source and also specifies in the units of technology library. A typical Drive

constraint is given by set_attribute-port ybus-name output_drive-value 31, it specifies

that signal ybus has 31 library units of drive capability.

Arrival time: Some synthesis tools uses static timing analyzer during synthesis process to

check that the logic being created matches the timing constraints the user has specified. For

large designs if test vectors are available then static timing analysis is used. static timing

analyzer traces each path in the design and

keeps of timing from a clock edge or an input. A

designer can be verify all the critical paths that

are within the required specifications are not. If

they are within the required specifications then

static timing analyzer shows entire path to the

designer to fix the problem.

Figure 2.12 Constraints

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11. Discuss synthesis information from entity with examples.[8M] Ans) Synthesis: It is task of designing a digital system that implements a desired functional

behavior. Simply it is the process of generating a logic diagram from a truth table. For performing

this process automatically CAD tools are available. HDL program is input to the synthesis compiler.

When HDL code passed through initial synthesis tool a lower level description of the circuit is

generated as output. The task of synthesis tool to manipulate user’s design to produce equivalent or

better circuit automatically called logic synthesis or logic optimization. In this process a list of

components and their interconnections is derived from model of digital system described by HDL ,

is called netlist.

Figure 2.13 Relation between Simulation and synthesis

Once behavioural HDL model is complete, two items are required to process

1. Logic Synthesizer (software and documentation): It performs translation, logic minimization &

optimization, and mapping to gate functions.

2. Cell library or target Library: contains logic cells such as NAND gate etc.

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A) TRANSLATION: The RTL description is translated to an Unoptimized boolean description

consists of premitive gates such as AND,OR,FLIPFLOPS and LATCHES. All IF,CASE,LOOP

statements,signal assignments are converted into their boolean equivqlents.

B) LOGIC MINIMIZATION & OPTIMIZATION: Logic minimization involves reduced number of

literals which saves silicon area, it can be understood by karnaugh map. Logic optimization process

converts an unoptimized boolean description into an optimized one. For simplification it uses a

series of FLATTERING, FACTORING, SUBSTITUTION and ELEMINATION steps.

FLATTERING: It is the process of converting the unoptimized boolean description to a PLA

format. It creates a flat signal representation of only two levels as AND level, OR level by

removing intermediate states. PLA has simple structure and well known algorithms to

perform boolean optimization. Flattering designs are very big and slower Design

Example:

Original equations

a=b and c;

b= x or (y and z);

c=q or w;

After Flattering

a=(x and q)or(q and y and z)or(w and x)or (w and y and z)

FACTORING: It is the process of adding intermediate terms to add structure to a

description. It is opposite of Flattering. It produces delays by adding of logic structure. It is

smaller and slower than Flattering

Example:

Original equations

x= a and b or a and d;

y= z or b or d;

After Factering

x=a and q;

y=z or q;

q=b or d;

C) MAPPING: Mapping process takes the logically optimized boolean description created by

optimization step and uses logical and timing information from a technology library to build a

netlist. Netlist is targeted to the user’s needs for area and speed. Many netlists are functionally same

but vary widely in speed and area.