UNIT – 5 PULSE CIRCUITS CLIPPERS -...

UNIT – 5

PULSE CIRCUITS

CLIPPERS

A circuit which removes the peak of a waveform is known as a clipper. A negative clipper is shown in Figure below. This schematic diagram was produced with Xcircuit schematic capture program. Xcircuit produced the SPICE net list Figure below, except for the second, and next to last pair of lines which were inserted with a text editor.

*SPICE 03437.eps * A K ModelName D1 0 2 diode R1 2 1 1.0k V1 1 0 SIN(0 5 1k) .model diode d .tran .05m 3m .end

Clipper: clips negative peak at -0.7 V.

During the positive half cycle of the 5 V peak input, the diode is reversed biased. The diode does not conduct. It is as if the diode were not there. The positive half cycle is unchanged at the output V(2) in Figure below. Since the output positive peaks actually overlays the input sinewave V(1), the input has been shifted upward in the plot for clarity. In Nutmeg, the SPICE display module, the command “plot v(1)+1)” accomplishes this.

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V(1)+1 is actually V(1), a 5 Vptp sinewave, offset by 1 V for display clarity. V(2) output is clipped at -0.7 V, by diode D1.

During the negative half cycle of sinewave input of Figure above, the diode is forward biased, that is, conducting. The negative half cycle of the sinewave is shorted out. The negative half cycle of V(2) would be clipped at 0 V for an ideal diode. The waveform is clipped at -0.7 V due to the forward voltage drop of the silicon diode. The spice model defaults to 0.7 V unless parameters in the model statement specify otherwise. Germanium or Schottky diodes clip at lower voltages.

Closer examination of the negative clipped peak (Figure above) reveals that it follows the input for a slight period of time while the sinewave is moving toward -0.7 V. The clipping action is only effective after the input sinewave exceeds -0.7 V. The diode is not conducting for the complete half cycle, though, during most of it.

The addition of an anti-parallel diode to the existing diode in Figure above yields the symmetrical clipper in Figure below.



*SPICE 03438.eps D1 0 2 diode D2 2 0 diode R1 2 1 1.0k V1 1 0 SIN(0 5 1k) .model diode d .tran 0.05m 3m .end

Symmetrical clipper: Anti-parallel diodes clip both positive and negative peak, leaving a ± 0.7 V output.

Diode D1 clips the negative peak at -0.7 V as before. The additional diode D2 conducts for positive half cycles of the sine wave as it exceeds 0.7 V, the forward diode drop. The remainder of the voltage drops across the series resistor. Thus, both peaks of the input sinewave are clipped in Figure below. The net list is in Figure above

Diode D1 clips at -0.7 V as it conducts during negative peaks. D2 conducts for positive peaks, clipping at 0.7V.

The most general form of the diode clipper is shown in Figure below. For an ideal diode, the clipping occurs at the level of the clipping voltage, V1 and V2. However, the voltage sources have been adjusted to account for the 0.7 V forward drop of the real silicon diodes. D1 clips at



1.3V +0.7V=2.0V when the diode begins to conduct. D2 clips at -2.3V -0.7V=-3.0V when D2 conducts.

*SPICE 03439.eps V1 3 0 1.3 V2 4 0 -2.3 D1 2 3 diode D2 4 2 diode R1 2 1 1.0k V3 1 0 SIN(0 5 1k) .model diode d .tran 0.05m 3m

.end

D1 clips the input sinewave at 2V. D2 clips at -3V.

The clipper in Figure above does not have to clip both levels. To clip at one level with one diode and one voltage source, remove the other diode and source.

The net list is in Figure above. The waveforms in Figure below show the clipping of v(1) at output v(2).



D1 clips the sinewave at 2V. D2 clips at -3V.

There is also a zener diode clipper circuit in the “Zener diode” section. A zener diode replaces both the diode and the DC voltage source.

A practical application of a clipper is to prevent an amplified speech signal from overdriving a radio transmitter in Figure below. Over driving the transmitter generates spurious radio signals which causes interference with other stations. The clipper is a protective measure.

Clipper prevents over driving radio transmitter by voice peaks.

A sinewave may be squared up by overdriving a clipper. Another clipper application is the protection of exposed inputs of integrated circuits. The input of the IC is connected to a pair of diodes as at node “2” of Figure above . The voltage sources are replaced by the power supply rails of the IC. For example, CMOS IC's use 0V and +5 V. Analog amplifiers might use ±12V for the V1 and V2 sources.



REVIEW

A resistor and diode driven by an AC voltage source clips the signal observed across the diode.

A pair of anti-parallel Si diodes clip symmetrically at ±0.7V The grounded end of a clipper diode(s) can be disconnected and wired to a DC

voltage to clip at an arbitrary level. A clipper can serve as a protective measure, preventing a signal from exceeding

the clip limits.

Clamper circuits

The circuits in Figure below are known as clampers or DC restorers. The corresponding netlist is in Figure below. These circuits clamp a peak of a waveform to a specific DC level compared with a capacitively coupled signal which swings about its average DC level (usually 0V). If the diode is removed from the clamper, it defaults to a simple coupling capacitor– no clamping.

What is the clamp voltage? And, which peak gets clamped? In Figure below (a) the clamp voltage is 0 V ignoring diode drop, (more exactly 0.7 V with Si diode drop). In Figure below, the positive peak of V(1) is clamped to the 0 V (0.7 V) clamp level. Why is this? On the first positive half cycle, the diode conducts charging the capacitor left end to +5 V (4.3 V). This is -5 V (-4.3 V) on the right end at V(1,4). Note the polarity marked on the capacitor in Figure below (a). The right end of the capacitor is -5 V DC (-4.3 V) with respect to ground. It also has an AC 5 V peak sinewave coupled across it from source V(4) to node 1. The sum of the two is a 5 V peak sine riding on a - 5 V DC (-4.3 V) level. The diode only conducts on successive positive excursions of source V(4) if the peak V(4) exceeds the charge on the capacitor. This only happens if the charge on the capacitor drained off due to a load, not shown. The charge on the capacitor is equal to the positive peak of V(4) (less 0.7 diode drop). The AC riding on the negative end, right end, is shifted down. The positive peak of the waveform is clamped to 0 V (0.7 V) because the diode conducts on the positive peak.



Clampers: (a) Positive peak clamped to 0 V. (b) Negative peak clamped to 0 V. (c) Negative peak clamped to 5 V.

*SPICE 03443.eps V1 6 0 5 D1 6 3 diode C1 4 3 1000p D2 0 2 diode C2 4 2 1000p C3 4 1 1000p D3 1 0 diode V2 4 0 SIN(0 5 1k) .model diode d .tran 0.01m 5m .end

V(4) source voltage 5 V peak used in all clampers. V(1) clamper output from Figure above (a). V(1,4) DC voltage on capacitor in Figure (a). V(2) clamper output from Figure (b). V(3) clamper output from Figure (c).

Suppose the polarity of the diode is reversed as in Figure above (b)? The diode conducts on the negative peak of source V(4). The negative peak is clamped to 0 V (-0.7 V). See V(2) in Figure above.



The most general realization of the clamper is shown in Figure above (c) with the diode connected to a DC reference. The capacitor still charges during the negative peak of the source. Note that the polarities of the AC source and the DC reference are series aiding. Thus, the capacitor charges to the sum to the two, 10 V DC (9.3 V). Coupling the 5 V peak sinewave across the capacitor yields Figure above V(3), the sum of the charge on the capacitor and the sinewave. The negative peak appears to be clamped to 5 V DC (4.3V), the value of the DC clamp reference (less diode drop).

Describe the waveform if the DC clamp reference is changed from 5 V to 10 V. The clamped waveform will shift up. The negative peak will be clamped to 10 V (9.3). Suppose that the amplitude of the sine wave source is increased from 5 V to 7 V? The negative peak clamp level will remain unchanged. Though, the amplitude of the sinewave output will increase.

An application of the clamper circuit is as a “DC restorer” in “composite video” circuitry in both television transmitters and receivers. An NTSC (US video standard) video signal “white level” corresponds to minimum (12.5%) transmitted power. The video “black level” corresponds to a high level (75% of transmitter power. There is a “blacker than black level” corresponding to 100% transmitted power assigned to synchronization signals. The NTSC signal contains both video and synchronization pulses. The problem with the composite video is that its average DC level varies with the scene, dark vs light. The video itself is supposed to vary. However, the sync must always peak at 100%. To prevent the sync signals from drifting with changing scenes, a “DC restorer” clamps the top of the sync pulses to a voltage corresponding to 100% transmitter modulation.

Clippers:

Clipping circuits are used to select that part of the input wave which lies above or below some reference level.



In this clipper circuit

Vo = Vi if Vi<VR

Vo = VR if Vi>VR

In this clipper circuit

Vo = Vi if Vi>VR

Vo = VR if Vi<VR



considering third approximation

Now,

Vo = Vi if Vi<(VR+Vr)

When Vi>(VR+Vr) diode D conducts and the equivalent circuit becomes



y=mx+c

The current i in the circuit is given by



When Vi < (VR-Vr), D condcuts and the equivalent circuit becomes

Therefore



Clipping at two independent levels

VR1 < VR2



Clamper Circuits:

Claming is a process of introducing d.c. level into a signal . Example. If the input voltage swings from -10 V and +10 V a positive d.c. clamper will produce the output that swings ideally from 0 V to + 20 V. The complete waveform is lifted up by +10 V so as to just touch the horizontal axis.

Negative Diode clamper:



During first positive half cycle as Vi rises from 0 to 10 V, the diode conducts. Assuming an ideal diode, its voltage, which is also the output must be zero during the time from 0 to t1. Howver, the capacitor charges during this period to 10 V. With the polarity shown. At the same time (t1). Vi starts to drop which means the anode of D is negative relative to cathode, (VD = Vi - Vc) thus reverse biasing the diode and preventing the capacitor from discharging. fig 26 . Since the capacitor is holding its charge it behaves as a D.C. voltage source while the diode appears as an open circuit the equivalent circuit becomes like as shown in fig .27

\



Positive Clamper:

Thus circuit behaves as if a 10 V dc. Source had been placed in series with ac. generate, this shift

every voltage by -10 V.



To clamp the input signal other than 0 V, d.c. source is required. Fig. 30. The d.c. source is reverse biasing the diode. In the negative half cycle when the voltage exceed 5V then D conduct. During -5 V to 10 V, the capacitor charges to 5 V with the polarity shown. After that D becomes reverse biased. ( VD = V i - 5 V - 5 V ), and open circuited. Then complete a.c. signal is shifted upward by 5 V.



REVIEW:

A coactively coupled signal alternates about its average DC level (0 V). The signal out of a clamper appears the have one peak clamped to a DC voltage.

Example: The negative peak is clamped to 0 VDC, the waveform appears to be shifted upward. The polarity of the diode determines which peak is clamped.

An application of a clamper, or DC restorer, is in clamping the sync pulses of composite video to a voltage corresponding to 100% of transmitter power.

MULTIVIBRATORS

ASTABLE MULTIVIBRATOR

Introduction

Now that we have seen the bistable multivibrator and then modified it to form a monostable multivibrator, the next question is, Can we modify it further to use capacitor coupling on both sides? And what would happen if we did?

Well, of course we can do this; the further question would be, Do we want to? And that depends on what happens when we build the circuit this way.

Since the use of one capacitor prevents the circuit from remaining stable in one of its two possible states, it seems likely that with both sides coupled this way the circuit will be unable to remain stable in either state. That is in fact the case, and in this experiment we will construct and demonstrate this circuit.



Schematic Diagram

As shown in the schematic diagram here, the astable multivibrator simply extends the modification that converted the bistable multivibrator to a monostable version of the circuit. Now, both transistors are coupled to each other through capacitors. Whichever transistor is off at any moment cannot remain off indefinitely; its base will become forward biased as that capacitor charges towards +5 volts. Once that happens, that transistor will turn on, thereby turning the other one off.

If we pick a moment when Q1 has just turned off and Q2 is on, then the left end of C2 is at -5 volts. This negative voltage decreases as C2 charges through R2 towards +5 volts. However, the moment C2 charges enough to provide forward bias to the base of Q1, Q1 turns on and the 5 volt drop in Q1's collector voltage is coupled through C1 to the base of Q2. This turns Q2 off at once. As we saw in the previous experiment, the time that Q1 remains on and Q2 remains off is 0.693RC, which for the component values shown here is about 1 second.

Now Q2 is held off while C1 charges through R1, until Q2's base becomes forward biased. At that point the transistors switch states again and the whole thing starts over. There is no stable state where the circuit can come to rest, so this circuit is known as an astable multivibrator.

The time Q2 remains off is set by R1 and C1, just as the time Q1 remains off is set by R2 and C2. For our circuit, the components are of the same values on each side, so the timing will be the same on each half of the cycle. This is not required; the two halves of the circuit can have totally different time intervals. They actually operate independently of each other, even though they work together.



Since this particular circuit will spend about 1 second on each half cycle, the total cycle time, or period, is about 2 seconds. The operating frequency of the circuit is the reciprocal of the period, or 0.5 Hz.

Discussion

You should have found that this circuit does indeed oscillate between its two states, neither of which is stable. That's why this circuit is known as an astable multivibrator. With these component values, each LED remained on for just about 1 second before the circuit switched states. This continued for as long as you left power on.

With smaller capacitors to increase the frequency of oscillation, this type of circuit is sometimes used as a clock generator for sequential digital circuits that don't need to operate at some precise frequency.

When you have completed this experiment, make sure power to your experimental circuit is turned off. Remove the experimental components from your breadboard socket and put them aside for the next experiment.

MONOSTABLE MULTIVIBRATOR

Introduction

In the previous experiment, you activated the R and S inputs to the latch circuit by turning a switch on, then off again. While this works, sometimes it would be nice to accomplish the same purpose with a single input action. That is, we'd like to be able to use a single input action to cause a digital pulse to be generated.

The circuit you'll demonstrate in this experiment is a variation in the bistable multivibrator circuit you have already seen in action. The difference is that we're going to modify the circuit so that once switched to the Set state, it will delay, then reset itself with no further intervention. This will give us the behavior we need.

For the circuit to behave this way, it needs to have one stable state (Reset), while the other state is not permanently stable. In practice, the Set state is quasi-stable in that it can be retained for a set period before the circuit reverts back to its stable state. In this experiment, we'll find out just how this can be accomplished.



Schematic Diagram

As you can see in the schematic diagram to the right, the monostable multivibrator is very similar in design to the bistable multivibrator you have already demonstrated. The primary difference is the use of a capacitor (C in the schematic) as one of the cross-coupling elements. The resistor is still present (R in the schematic), but now connects the base of Q2 to +5 volts instead of to the collector of Q1.

Of course, the capacitor will take a certain amount of time to charge, but once it does so it will carry no current, and Q2 will be turned on by the current through its 15K base resistor. This in turn holds the Q output at logic 0. This output is also applied as before, holding Q1 off. Assuming the T (Trigger) input is also quiescent at logic 0, Q3 is also off and the circuit will remain indefinitely in this state.

At this point, C is charged to just about +5 volts (less VBE of Q2), with the Q1 collector connection being positive. The circuit will remain in this state until a logic 1 signal is applied to the T input.

When an input signal is received at T, Q3 turns on and pulls the left end of capacitor C down to ground. Since the capacitor voltage cannot change instantaneously, this forces the right end of C to -5 volts, immediately turning Q2 off. This in turn applies a logic 1 to Q1's input, turning Q1 on. At this point, the input to T can be discontinued; the Q output is logic 1 and Q1 will remain on.

Under these circumstances, the left end of C remains locked to ground through Q1's collector. But the right end gradually charges through R, Q2's base resistor, towards +5 volts. However, it never gets there; as soon as this voltage allows Q2's



base to become forward biased, Q2 turns on and turns Q1 off again. This returns the circuit to its quiescent state.

Thus, this circuit cannot maintain a logic 1 output indefinitely; this is not really a stable state for this circuit. The circuit has only one stable state (Q = 0). It is therefore known as a monostable multivibrator.

The duration of the quasi-stable state (Q = 1) is determined by the two components R and C. Because the capacitor only charges to half the total range (from -5 volts to 0, while charging towards +5 volts), the duration of the output pulse is 0.693RC, where 0.693 is the natural logarithm of 2, R is in ohms, and C is in farads. For the component values shown here, the timing interval is 0.693 × 15,000 × 0.0001 = 1.04 seconds. So this circuit will produce a 1-second pulse each time it is triggered.

If the T input has already returned to logic 0, C will rapidly recharge through the 1K collector resistor and be ready for another input trigger signal. If T remains at logic 1, C will remain discharged until T drops again to logic 0. Then C will fully recharge in about 0.5 second and be ready for another trigger signal.

Discussion



When you first turned power on, capacitor C was fully discharged. Since its voltage cannot change instantaneously, it had the effect of holding Q2 off initially. Therefore L0 turned on briefly when you first applied power to this circuit. However, the capacitor rapidly charged enough to allow Q2 to turn on, whereupon L0 turned off. Capacitor C then continued to charge through Q1's 1K collector resistor and Q2's emitter-base junction until C was charged to nearly 5 volts. Once this had occurred, the circuit was ready to be triggered.

When you applied a logic 1 to the T input using S0, the collector voltage of Q1 and Q3 dropped immediately to nearly ground potential. However, capacitor C still has a 5 volt charge on it. Since its left end has been essentially grounded, its right end is now at a voltage of nearly -5 volts. This immediately turns Q2 off, which in turn turns Q1 on. L0 turned on, and remained on when you returned S0 to its logic 0 position.

The time that the circuit remained in this state was set by the values of capacitor C and resistor R. C charges through R towards +5 volts, a process that normally should require 5 times the R × C time constant. However, once the capacitor is charged sufficiently to allow Q2's base to become forward biased, Q2 will turn on. This will turn Q1 off again, and will also turn L0 off. This only required about 69% of one time constant (ln 2 = 0.693...). Thus, you should have found that L0 turned on for about 1 second each time you applied a logic 1 via S0. The exact timing interval depends on the component tolerances of R and C.

When you turned S0 on and left it on, you noticed no difference in circuit behavior. Q2 still turned on at the end of the same timing interval, turning L0 off. The difference was that Q3 remained on, thus preventing capacitor C from charging. However, when



you set S0 to logic 0, C rapidly recharged so that setting S0 to logic 1 after a delay caused the same behavior as before.

When you set S0 to logic 0 and then immediately back to logic 1, you were trying to retrigger the circuit before C had time to recharge. However, unless you were very fast, you probably didn't notice any variation. C recharges through the 1K collector resistor for Q1 and Q3, so it recharges 15 times as fast as it charges while L0 is on. This is long enough to prevent contact bounce in the switch from being a problem, but not long enough to exercise manual control of the circuit timing.

Basically, each time you triggered this circuit, L0 remained on for about 1 second, then turned off. You could not extend this interval, nor could you shorten it. Thus, this circuit generates a single, fixed-duration output pulse each time it is triggered, and then waits for the next trigger pulse.

Since the duration of the pulse produced by this circuit (the "pulse width") is controlled by R and C, we can set the pulse width by modifying these components. Of course, R must have a value suitable for the correct biasing of Q2. Therefore, the value of C is selected to get the pulse width as close as possible to the desired value, and then R is adjusted to "fine tune" the pulse width. If exact timing is critical, a potentiometer is used for R.

When you have completed this experiment, make sure power to your experimental circuit is turned off. Remove all experimental components from your breadboard socket and set them aside for use in later experiments.

BI STABLE MULTIVIBRATOR

Introduction

We've looked at a number of gates, constructed using different technologies. Now it's time to combine gates into more interesting circuits, and see what can be done with such combinations.

As a start, we'll take two basic RTL inverters and cross-couple them, so that each has its input connected to the output of the other. At first thought this may seem pointless, since such a circuit would seem to be locked forever into one condition, or state. One transistor would be turned on while the other would be turned off, and each would continue to enforce the state of the other.

In fact, this is exactly what we want. Either transistor can be on while the other is off, and the circuit will retain its state until it is changed by an external signal or power



is turned off. Thus, this circuit represents the simplest possible binary memory. In this experiment, you will construct and demonstrate such a circuit.

Schematic Diagram

As shown here, the circuit we're looking at really is nothing more than two basic inverters, each taking its input from the other's output. If, when power is first applied, Q1 turns on, its output will be a logic 0. This will be applied to Q2's input resistor, keeping Q2 turned off so that its output will be a logic 1. This logic 1 will be applied back to Q1's input resistor, keeping Q1 turned on and holding the entire circuit locked into this stable state.

On the other hand, if Q1 stays off at power-up, it will apply a logic 1 to Q2's input, thus turning Q2 on. The resulting logic 0 output from Q2 will in turn hold Q1 off. The circuit will then remain in this stable state indefinitely.

Because this circuit has two possible logical states, it is known technically as a multivibrator. Because it has two possible stable states, it is a bistable multivibrator. It is also the most basic possible binary latch circuit. In the next few experiments we'll look at ways to expand this circuit and modify its behavior. But first, we'll examine the operation of this basic circuit.

Discussion

When you first turned on power, either L0 or L1 turned on and stayed on. In nearly every case, turning power off long enough to discharge the reservoir capacitor and then turning it back on again made no difference; the two transistors are not identical and one turned on faster than the other. That transistor kept its LED off, while the other transistor remained turned off and therefore turned its connected LED on to indicate a logic one at that collector.



Grounding the collector of the transistor whose LED was off had no effect on the circuit. That transistor was already turned on, so its collector was already essentially grounded. Grounding it harder won't change anything. However, when you grounded the collector of the transistor whose LED was currently on had the effect of turning it off and turning the other LED on instead. Removing the ground made no difference; the circuit had already changed state and was completely stable in its new state.

With the experimental circuit now in the opposite state, the same basic rules still apply to its behavior. Grounding the collector of the transistor whose LED was currently off had no effect, while grounding the collector of the transistor whose LED was on caused the circuit two switch back to its previous state. Both states are completely stable, meaning that only the application of an external signal (your grounding jumper) can cause this circuit to change states. It will not spontaneously changes states so long as the circuit is powered.

When you have completed this experiment, make sure power to your experimental circuit is turned off. Do not remove any of your experimental components; you will use this circuit in your next experiment.

SCHMITT TRIGGER

Introduction

Sometimes an input signal to a digital circuit doesn't directly fit the description of a digital signal. For various reasons it may have slow rise and/or fall times, or may have acquired some noise that could be sensed by further circuitry. It may even be an analog signal whose frequency we want to measure. All of these conditions, and many others, require a specialized circuit that will "clean up" a signal and force it to true digital shape.

The required circuit is called a Schmitt Trigger. It has two possible states just like other multivibrators. However, the trigger for this circuit to change states is the input voltage level, rather than a digital pulse. That is, the output state depends on the input level, and will change only as the input crosses a pre-defined threshold.

In this experiment, we will look at the theory of this circuit's operation, and then build one to demonstrate its real-world operation.

Schematic Diagram



Unlike the other multivibrators you have built and demonstrated, the Schmitt Trigger makes its feedback connection through the emitters of the transistors as shown in the schematic diagram to the right. This makes for some useful possibilities, as we will see during our discussion of the operating theory of this circuit.

To understand how this circuit works, assume that the input starts at ground, or 0 volts. Transistor Q1 is necessarily turned off, and has no effect on this circuit. Therefore, RC1, R1, and R2 form a voltage divider across the 5 volt power supply to set the base voltage of Q2 to a value of (5 × R2)/(RC1 + R1 + R2). If we assume that the two transistors are essentially identical, then as long as the input voltage remains significantly less than the base voltage of Q2, Q1 will remain off and the circuit operation will not change.

Note: Classical analyses of this circuit include the forward current gain, hFE, of the two transistors. This was important in the early days of transistors when a signal transistor was doing well to have a current gain of 30. Modern transistors have a much higher gain (160 for the 2N3904/2N3906, 200 for the 2N4124/2N4126), so they don't have the same limitations as older transistors. We can ignore the effects of transistor base current, although we do still need to account for VBE for the two transistors.

While Q1 is off, Q2 is on. Its emitter and collector current are essentially the same, and are set by the value of RE and the emitter voltage, which will be less than the Q2 base voltage by VBE. If Q2 is in saturation under these circumstances, the output voltage will be within a fraction of the threshold voltage set by RC1, R1, and R2. It is important to note that the output voltage of this circuit cannot drop to zero volts, and generally not to a valid logic 0. We can deal with that, but we must recognize this fact.



Now, suppose that the input voltage rises, and continues to rise until it approaches the threshold voltage on Q2's base. At this point, Q1 begins to conduct. Since it now carries some collector current, the current through RC1 increases and the voltage at the collector of Q1 decreases. But this also affects our voltage divider, reducing the base voltage on Q2. But since Q1 is now conducting it carries some of the current flowing through RE, and the voltage across RE doesn't change as rapidly. Therefore, Q2 turns off and the output voltage rises to +5 volts. The circuit has just changed states.

If the input voltage rises further, it will simply keep Q1 turned on and Q2 turned off. However, if the input voltage starts to fall back towards zero, there must clearly be a point at which this circuit will reset itself. The question is, What is the falling threshold voltage? It will be the voltage at which Q1's base becomes more negative than Q2's base, so that Q2 will begin conducting again. However, it isn't the same as the rising threshold voltage, since Q1 is currently affecting the behavior of the voltage divider.

We won't go through all of the derivation here, but when VIN becomes equal to Q2's base voltage, Q2's base voltage will be:

As VIN approaches this value, Q2 begins to conduct, taking emitter current away from Q1. This reduces the current through RC1 which raises Q2's base voltage further, increasing Q2's forward bias and decreasing Q1's forward bias. This in turn will turn off Q1, and the circuit will switch back to its original state.

Three factors must be recognized in the Schmitt Trigger. First, the circuit will change states as VIN approaches VB2, not when the two voltages are equal. Therefore VB2 is very close to the threshold voltage, but is not precisely equal to it. For example,



for the component values shown above, VB2 will be 2.54 volts when Q1 is held off, and 2.06 volts as VIN is falling towards this value.

Second, since the common emitter connection is part of the feedback system in this circuit, RE must be large enough to provide the requisite amount of feedback, without becoming so large as to starve the circuit of needed current. If RE is out of range, the circuit will not operate properly, and may not operate as anything more than a high-gain amplifier over a narrow input voltage range, instead of switching states.

The third factor is the fact that the output voltage cannot switch over logic levels, because the transistor emitters are not grounded. If a logic-level output is required, which is usually the case, we can use a circuit such as the one shown here to correct this problem. This circuit is basically two RTL inverters, except that one uses a PNP transistor. This works because when Q2 above is turned off, it will hold a PNP inverter off, but when it is on, its output will turn the PNP transistor on. The NPN transistor here is a second inverter to re-invert the signal and to restore it to active pull-down in common with all of our other logic circuits.

The circuit you will construct for this experiment includes both of the circuits shown here, so that you can monitor the response of the Schmitt trigger with L0.

UJT Relaxation Oscillator



UJT is an uni-junction device. This single pn junction device consists of a lightly doped n-type silicon bar. The p- type impurity is diffused into the base producing the pn junction. The above figure shows the equivalent circuit of UJT. The resistance of the silicon bar is called inter base resistance RBB represented by the two resistors in series viz. Rb1 and Rb2. The pn junction is represented in the emitter by a diode D. The operation of UJT may be explained in three different modes.

a. With no voltage applied to the UJT, the inter base resistance is given by

Rbb=Rb1 + Rb2

b. If a voltage Vbb is applied between the bases with emitter open, the voltage will divide up across Rb1 and Rb2.

Voltage across Rb1,

Or



The ratio is called the intrinsic stand-off ratio represented by h . Thus

. The value of h lies between 0.51 and 0.82. The voltage across Rb1 is which reverse biases the diode. Hence emitter current is zero.

c. If a progressively rising positive voltage is applied to the emitter the diode will become forward biased when input voltage exceeds h Vbb by Vd, the forward voltage drop across the silicon diode. Now the emitter current increases regeneratively until it is limited by the emitter power supply. Here we can define the peak point voltage of the UJT,

Thus when input positive voltage to the emitter is less then Vp, the pn-junction remains reverse biased and the emitter current is practically zero. When the input voltage exceeds Vp, the diode is forward biased and the emitter current reaches a saturation value limited by Rb1and the forward resistance of pn-junction.

UJT Relaxation Oscillator circuit, mainly used for triggering purposes is shown above. This circuit is ideally suited for triggering an SCR – since UJT is capable of generating sharp, high powered pulses of short duration whose peak and average power don’t exceed the power



capabilities of the SCR gate for which they are intended. When power is applied to the given circuit, capacitor C starts charging exponentially through R to the applied voltage VCC. The voltage across C is the voltage-Ve applied to the emitter of UJT. When C is charged to Vp, then UJT turns ON. This greatly reduces the effective resistance between emitter and base1 of UJT. A sharp pulse of current flows from base1 to emitter, discharging C through Rb1. When the capacitor voltage drops below Vp, UJT is brought back to the previous state and the capacitor again begins to charge towards Vbb. This produces a sawtooth wave.

In the circuit diagram shown above Rb1 and Rb2 are used to protect UJT from overheating. This inturn provides sharp pulses across them: Rb1 produces a positive spike and Rb2 produces a negative spike.

Design: -

Oscillator frequency

Intrinsic stand-off ratio h =0.4 to 0.6

h =0.5 (we take)

substituting the value of h in (1)



Capacitor C is charged through R towards supply voltage VBB. As long as capacitor voltage VE is below a stand-off voltage VP set by the voltage across B1-B2 and the transistor stand-off ratio h .

Sweep Amplitude = VP-VV

from design specification

Design of R

At peak point emitter voltage VE=VP and current through R is given by

At valley point



Design of Capacitor

Design of RB1 and RB2

At the point where the capacitor voltage is equal to VP assuming IE=0A, the network of fig 4 results. VP is the voltage required to turn on the UJT.

But the intrinsic stand-off ratio h is given by the equation

Also



Substituting (a) and (b) in equation (10) we get

RB2 is chosen as a low value resistor. Let it be 100W .

Hence the above equation becomes

The output waveform may be observed in the waveform viewer.



UNIT – 5 PULSE CIRCUITS CLIPPERS -...

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