UNIT-4 The Shift RegisterUCA15E51 DLF UNIT-4 Page 1 UNIT-4 The Shift Register The Shift Register is...

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UNIT-4

The Shift Register

The Shift Register is another type of sequential logic circuit that can be used for the storage or

the transfer of binary data

This sequential device loads the data present on its inputs and then moves or “shifts” it to its

output once every clock cycle, hence the name Shift Register.

A shift register basically consists of several single bit “D-Type Data Latches”, one for each data

bit, either a logic “0” or a “1”, connected together in a serial arrangement so that the output

from one data latch becomes the input of the next latch and so on.

Data bits may be fed in or out of a shift register serially, that is one after the other from either the

left or the right direction, or all together at the same time in a parallel configuration.

The number of individual data latches required to make up a single Shift Register device is

usually determined by the number of bits to be stored with the most common being 8-bits (one

byte) wide constructed from eight individual data latches.

Shift Registers are used for data storage or for the movement of data and are therefore

commonly used inside calculators or computers to store data such as two binary numbers

before they are added together, or to convert the data from either a serial to parallel or

parallel to serial format.

The individual data latches that make up a single shift register are all driven by a common clock

( Clk ) signal making them synchronous devices.

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Generally, shift registers operate in one of four different modes

1. Serial-in to Parallel-out (SIPO) - the register is loaded with serial data, one bit at a

time, with the stored data being available at the output in parallel form.

2. Serial-in to Serial-out (SISO) - the data is shifted serially “IN” and “OUT” of

the register, one bit at a time in either a left or right direction under clock

control.

3. Parallel-in to Serial-out (PISO) - the parallel data is loaded into the register

simultaneously and is shifted out of the register serially one bit at a time under

clock control.

4. Parallel-in to Parallel-out (PIPO) - the parallel data is loaded simultaneously

into the register, and transferred together to their respective outputs by the same

clock pulse.

The effect of data movement from left to right through a shift register can be presented

graphically as:

1. Serial-in to Parallel-out (SIPO) Shift Register

4-bit Serial-in to Parallel-out Shift Register

The operation is as follows. Let us assume that all the flip-flops ( FFA to FFD ) have just been

RESET ( CLEAR input ) and that all the outputs QA to QD are at logic level “0” ie, no parallel

data output.

If a logic “1” is connected to the DATA input pin of FFA then on the first clock pulse the output

of FFA and therefore the resulting QA will be set HIGH to logic “1” with all the other outputs

still remaining LOW at logic “0”. Assume now that the DATA input pin of FFA has returned

LOW again to logic “0” giving us one data pulse or 0-1-0.

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The second clock pulse will change the output of FFA to logic “0” and the output of FFB

and QB HIGH to logic “1” as its input D has the logic “1” level on it from QA. The logic “1” has

now moved or been “shifted” one place along the register to the right as it is now at QA.

When the third clock pulse arrives this logic “1” value moves to the output of FFC ( QC ) and so

on until the arrival of the fifth clock pulse which sets all the outputs QA to QD back again to logic

level “0” because the input to FFA has remained constant at logic level “0”.

The effect of each clock pulse is to shift the data contents of each stage one place to the right,

and this is shown in the following table until the complete data value of 0-0-0-1 is stored in the

register. This data value can now be read directly from the outputs of QA to QD.

Then the data has been converted from a serial data input signal to a parallel data output. The

truth table and following waveforms show the propagation of the logic “1” through the register

from left to right as follows.

Basic Data Movement Through A Shift Register

Clock Pulse No QA QB QC QD

0 0 0 0 0

1 1 0 0 0

2 0 1 0 0

3 0 0 1 0

4 0 0 0 1

5 0 0 0 0

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2. Serial-in to Serial-out (SISO) Shift Register

This shift register is very similar to the SIPO above, except were before the data was read

directly in a parallel form from the outputs QA to QD, this time the data is allowed to flow

straight through the register and out of the other end. Since there is only one output,

the DATA leaves the shift register one bit at a time in a serial pattern, hence the name Serial-in

to Serial-Out Shift Register or SISO.

The SISO shift register is one of the simplest of the four configurations as it has only three

connections, the serial input (SI) which determines what enters the left hand flip-flop, the serial

output (SO) which is taken from the output of the right hand flip-flop and the sequencing clock

signal (Clk). The logic circuit diagram below shows a generalized serial-in serial-out shift

register.

4-bit Serial-in to Serial-out Shift Register

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This type of Shift Register also acts as a temporary storage device or it can act as a time delay

device for the data, with the amount of time delay being controlled by the number of stages in

the register, 4, 8, 16 etc or by varying the application of the clock pulses.

Parallel-in to Serial-out (PISO) Shift Register

The Parallel-in to Serial-out shift register acts in the opposite way to the serial-in to parallel-out

one above. The data is loaded into the register in a parallel format in which all the data bits enter

their inputs simultaneously, to the parallel input pins PA to PD of the register. The data is then

read out sequentially in the normal shift-right mode from the register at Q representing the data

present at PA to PD.

This data is outputted one bit at a time on each clock cycle in a serial format. It is important to

note that with this type of data register a clock pulse is not required to parallel load the register as

it is already present, but four clock pulses are required to unload the data.

4-bit Parallel-in to Serial-out Shift Register

As this type of shift register converts parallel data, such as an 8-bit data word into serial format,

it can be used to multiplex many different input lines into a single serial DATA stream which

can be sent directly to a computer or transmitted over a communications line.

Parallel-in to Parallel-out (PIPO) Shift Register

The final mode of operation is the Parallel-in to Parallel-out Shift Register. This type of shift

register also acts as a temporary storage device or as a time delay device similar to the SISO

configuration above. The data is presented in a parallel format to the parallel input

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pins PA to PD and then transferred together directly to their respective output pins QA to QA by

the same clock pulse. Then one clock pulse loads and unloads the register. This arrangement for

parallel loading and unloading is shown below.

4-bit Parallel-in to Parallel-out Shift Register

The PIPO shift register is the simplest of the four configurations as it has only three connections,

the parallel input (PI) which determines what enters the flip-flop, the parallel output (PO) and the

sequencing clock signal (Clk).

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Shift Registers

A register is a device which is used to store information. Flip flops are often used to make a

register. Each flip flop can store 1-bit of information and therefore for storing a n-bit word n-flip-

flops are required in the register for example a computer employing 16-bit word length requires

16 flip-flops to hold the number before it is manipulated.

The input to a register or output from it may be either in serial or parallel form depending upon

the requirement.

Shift Register

A shift register is a storage device that used to store binary data. When a number of flip flop are

connected in series it is called a register. A single flip flop is supposed to stay in one of the two

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stable states 1 or 0 or in other words the flip flop contains a number 1 or 0 depending upon the

state in which it is. A register will thus contain a series of bits which can be termed as a word or

a byte.

If in these registers the connection is done in such a way that the output of one of the flip flop

forms in input to other, it is known as a shift register. The data in a shift register is moved

serially (one bit at a time).

The shift register can be built using RS, JK or D flip-flops various types of shift registers are

available some of them are given as under.

1. Shift Left Register

2. Shift Right Register

3. Shift Around Register

4. Bi-directional Shift Register

Shift Left Register

A four stage shift-left register is shown in figure 1. The individual stages are JK flip-flops.

Notice that the date input consists of opposite binary signals, the reference data signal going to

the J input and the opposite data signal going to the K input. For the D-type stage the single data

input line is connected as the D-input.

The shift pulse is applied to each stage operating each simultaneously. When the shift pulse

occurs the data input is shifted in to that stage. Each stage is set or reset corresponding to the

input data at the time the shift pulse occurs. Thus the input data bit is shift in to stage A by the

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first shift pulse. At the same time the data of stage A is shifted into the stage B and so on for the

following stages. At each shift pulse data stored in the register stages shifts left by one stage.

New data shifted into stage A, whereas the data present in stage D is shifted out to the left for use

by some other shift register or computer unit.

For example consider starting with all stages reset all Q-outputs to logical 0 and applying steady

logical 1 input as data input stage A. Table 1 shows the data in each stage after each of four shift

pulses.

Shift Right Register

Sometimes it is necessary to shift the least significant digit first, as when addition is to be carried

out serially. In that case a shift right register is used as in Figure input data is applied to stage D

and shifted right. The shift operation is the same as discussed in Shift Left Register except that

data transfers to the right. Table 4 shows the action of shifting all logical 1 inputs into an initially

reset shift register.

In addition to shifting data register, data into a register data is also of a register. Table 5 shows

register operation for an initial value of 1101. Notice that the output from stage A contains the

binary number each bit (starting initially with LSB) appearing at the output of each shift step. In

the present example it was assumed that logical 0 was shifted as input data so that after four shift

pulses have occurred the data has passed through the register and the stages are left reset after the

fourth shift pulse.

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COUNTERS

Counter - A counter is a sequential logic circuit consisting of a set of flip-flops which can go

through a sequence of states.

Counters are formed by connecting flip-flops together

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Types of counter are

1. Asynchronous Also known as ripple counter

The first flip-flop is driven by external clock while the successive flip-flops by the output of

preceding flip-flop

2. Synchronous: All flip-flops are simultaneously driven by common clock

Asynchronous counter

Also known as ripple counter. Ripple counters are the simplest type of binary counters

because they require the fewest components to produce a given counting operation.

Each FF output drives the CLK input of the next FF.

FFs do not change states in exact synchronism with the applied clock pulses.

There is delay between the responses of successive FFs.

It is also often referred to as a ripple counter due to the way the FFs respond one after another

in a kind of rippling effect.

Ripple Counter/Asynchronous Counter

A ripple counter is an asynchronous counter where only the first flip-flop is clocked by an

external clock. All subsequent flip-flops are clocked by the output of the preceding flip-flop.

Asynchronous counters are also called ripple-counters because of the way the clock pulse

ripples it way through the flip-flops.

The MOD of the ripple counter or asynchronous counter is 2n if n flip-flops are used. For a

4-bit counter, the range of the count is 0000 to 1111 (24-1). A counter may count up or count

down or count up and down depending on the input control.

Binary Ripple Counter

A binary ripple counter consists of a series connection of complementing flip-flops (T or JK

type), with the output of each flip-flop connected to the CP input of the next higher-order flip-

flop.

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The diagram of a 4-bit binary ripple counter is shown in Fig. All J and K inputs are equal to l.

The small circle in the CP input indicates that the flip-flop complements during a negative-going

transition or when the output to which it is connected goes from 1 to 0.

To understand the operation of the binary counter, refer to its count sequence given in Table 7 -

4. It is obvious that the lowest-order bit A1 must be complemented with each count pulse.

Every time A1 goes from 1 to 0, it complements A2.

Every time A2 goes from 1 to 0, it complements A3, and so on.

For example, take the transition from count 0111 to 1000.

The arrows in the table emphasize the transitions in this case.

A1 is complemented with the count pulse. S

ince A1 goes from 1 to 0, it triggers A2, and complements it.

As a result, A3, goes from 1 to 0, which in turn complements A3.

A3 now goes from 1 to 0, which complements A4

TABLE

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SYNCHRONOUS COUNTERS

Synchronous counters are distinguished from ripple counters in that clock pulses are

applied to the CP inputs of all flip-flops. The common pulse triggers all the flip-flops

simultaneously, rather than one at a time in succession as in a ripple counter

Binary Counter

The design of synchronous binary counters is so simple that there is no need to go through a

rigorous sequential-logic design process.

In a synchronous binary counter, the flip-flop in the lowest-order position is complemented with

every pulse. This means that its J and K inputs must be maintained at logic-1.

A flip-flop in any other position is complemented with a pulse provided all the bits in the lower-

order positions are equal to I, because the lower-order bits (when all 1's) will change to 0's on the

next count pulse. The binary count dictates that the next higher-order bit be complemented. For

example, if the present state of a 4-bit counter is A4A3A2A1 = 0011, the next count will be 0100.

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A1 is always complemented. A2 is complemented because the present state of A1 = 1. A3 is

complemented because the present state of A2A1=11. But A4 is not complemented because the

present state of A3A2A1 = 011, which does not give an all 1's condition.

Synchronous binary counters have a regular pattern and can easily be constructed with

complementing flip-flops and gates. The regular pattern can be clearly seen from the 4-bit

counter depicted in Fig. 7-17. The CP terminals of all flip-flops are connected to a common

clock-pulse source. The first stage A1 has its J and K equal to 1 if the counter is enabled. The

other J and K inputs are equal to 1 if all previous low-order bits are equal to 1 and the count is

enabled. The chain of AND gates generates the required logic for the J and K inputs in each

stage. The counter can be extended to any number of stages, with each stage having an additional

flip-flop and an AND gate that gives an output of 1 if all previous flip-flop outputs are 1's.

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Binary Up-Down Counter

BCD Counter

In a synchronous count-down binary counter, the flip-flop in the lowest-order position is

complemented with every pulse. A flip-flop in any other position is complemented with a pulse

provided all the lower-order bits are equal to 0. For example, if the present state of a 4-bit count-

down binary counter is A4A3A2A1 = 1100, the next count will be l0ll. A1 is always

complemented. A, is complemented because the present state of A1 = 0. A, is complemented

because the present state of A2A1 = 00. But A3 is not complemented because the present state of

A3A2A1 = 100, which is not an all-0's condition.

A count-down binary counter can be constructed as shown in Fig. 7-17, except that the inputs to

the AND gates must come from the complement outputs Q' and not from the normal outputs Q of

the previous flip-flops. The two operations can be combined in one circuit. A binary counter

capable of counting either up or down is shown in Fig. 7-18. The T flip-flops employed in this

circuit may be considered as JK flip-flops with the J and K terminals tied together. When the up

input control is 1, the circuit counts up, since the T inputs receive their signals from the values of

the previous normal outputs of the flip-flops. When the down input control is 1 and the up input

is 0, the circuit counts down, since the complemented outputs of the previous flip-flops are

applied to the T inputs. When the up and down inputs are both 0, the circuit does not change

state but remains in the same count. When the up and down inputs are both 1, the circuit counts

up. This ensures that only one operation is performed at any given time.

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BCD Counter

A BCD counter counts in binary-coded decimal from 0000 to 1001 and back to 0000. Because of

the return to 0 after a count of 9, a BCD counter does not have a regular pattern as in a straight

binary count. The excitation table of a BCD counter is given in Table 7-5. The excitation for the

T flip-flops is obtained from the present and next state conditions. An output y is also shown in

the table. This output is equal to I when the counter present state is 1001. In this way, y can

enable the count of the next-higher-order decade while the same pulse switches the present

decade from 1001 to 0000.

The flip-flop input functions from the excitation table can be simplified by means of maps. The

unused states for minterms 10 to 15 are taken as don't-care terms. The simplified functions are

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DESIGN OF COUNTERS

Counter Design Procedure

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Describe a general sequential circuit in terms of its basic parts and its input and outputs.

Develop a state diagram for a given sequence.

Develop a next-state table for a specific counter sequence.

Create a FF transition table.

Use K-map to derive the logic equations.

Implement a counter to produce a specified sequence of states.

EXAMPLES

1. Design of a Synchronous Decade Counter Using JK Flip- Flop

A synchronous decade counter will count from zero to nine and repeat the sequence. The state

diagram of this counter is shown in Fig. 9.9.

Since there are ten states, four JK flip-flops are required. The truth tables of present and next

state for the decade counter are shown in Fig. 9.10. Using the excitation table of JK flip-flop and

the outputs of J and K are filled.

The Karnaugh maps of the output J0, K0, J1, K1, J2, K2, J3, and K3 are shown in Fig. 9.11,

9.12, 9.13, and 9.14 respectively. The simplified results are at the bottom of the Karnaugh maps.

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Based on the results obtained from the Karnaugh maps, the circuit design of synchronous decade

counter is shown in Fig. 9.15.

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EXAMPLE 2

9.4.3 Design of a Synchronous Counter -0, 2, 3, 6, 5, and 1 and repeat the sequence Using SR

Flip-Flop

The modulus six counter will count 0, 2, 3, 6, 5, and 1 and repeat the sequence. This modulus six

counter requires three SR flip-flops for the design. The truth table of a modulus six counter is

shown in Fig. 9.17. From the excitation table of SR flip-flop shown in Fig. 9.8, the logic of

output S2, R2, S1, R1, S0, and R0 are filled and shown in Fig. 9.8.

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The Karnaugh maps of the output R0, S0, R1, S1, R2, and S2 are shown in Fig. 9.19, 9.20, and

9.21 respectively. The simplified results are at the bottom of the Karnaugh maps.

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With the known output logic functions, the logic design of the synchronous modulus six counter

is Shown ng Fig. 9.21.

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EXAMPLE 3:

Design a counter with the following binary sequence: 1, 2, 5, 7 and repeat. Use JK flip-flops.

Solution:

Step 1: Since it is a 3-bit counter, the number of flip-flops required is three.

Step 2: Let the type of flip-flops be RS flip-flops.

Step 3: Let the three flip-flops be A,B,C.

Step 4: The state table is as shown in Table 2.1.

Step 6: Now transfer the JK states of the flip-flop inputs from the excitation table to Karnaugh

maps in Tables 2.3–2.8 to derive a simplified Boolean expression for each flipflop

input.

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From the K-maps, the following expressions for the J and K inputs of each flip-flop are obtained:

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EXAMPLE 4:

Design a counter with the following repeated binary sequence: 0, 4, 2, 1, 6. Use T flipflops.

Solution:

Step 1: Since it is a 3-bit counter, the number of flip-flops required is three.

Step 2: Let the type of flip-flops be RS flip-flops.

Step 3: Let the three flip-flops be A, B and C.

Step 4: The state table is as shown in Table 3.1.

Table 3.1 State table

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Step 6: Now transfer the T states of the flip-flop inputs from the excitation table to Karnaugh

maps in Tables 3.3–3.5 to derive a simplified Boolean expression for each flipflop input

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From the K-maps, the following expressions for the T input of each flip-flop are obtained:

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