Unit 4 Chapter-1 Multitasking. The Task State Segment.
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Transcript of Unit 4 Chapter-1 Multitasking. The Task State Segment.
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Unit 4 Chapter-1
Multitasking
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Multitasking
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The Task State Segment
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• When task is created, LDT Selector (offset 60H) , PDBR (1CH), protection level stack ,T bit, I/O permission bit map are filled in.
• 20H to 5ch is change during task switching
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TSS Descriptor As with any segment, the TSS utilize a descriptor that defines the various characteristics the segment will exhibit
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Task Register
• TSS Descriptor may only be loaded into GDT
• The current TSS in use is accessed through the use of TR
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Task Gates
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• The Pentium provides task gates as an additional way to facilitate task switching
• Task gate may stored in LDT or IDT• It allows a single busy bit to be used for a
segment
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Task Switching
• Different ways1. The current task JMP’s or CALLs a TSS
Descriptor2. The current task JMP’s or CALLs a Task gate3. The current task executes an IRET when the
NT flag is set4. An interrupt or exception selects a task gate
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Task switching
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Nested task
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I/O Permission Bitmap
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Unit 4 Chapter-2
Virtual Mode
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Virtual Mode 8086
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Programmer’s model of Virtual mode
External Memory address space
I/o Address
space
00000H
0000 H
FFFFFH
FFFF H
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Virtual Mode instructions• Instructions supported are :1. LSS2. LFS3. LGS4. PUSHA5. POPA6. ENTER & LEAVE7. Single bit instruction8. Byte set on condition9. Double shift instruction10. Generalized multiply11. String I/O12. Bit scan
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Privilege & Protection
• CPL=3• Restricted instructions are:– HLT– CLTS– LGDT, LIDT, LLDT, LTR, LMSW, LAR, LSL– SLDT, STR– ARPL– Mov to/from control register– Mov to/from debus register– Mov to/from test register
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• VM 8086 program has a fixed privilege =3 & it is not able to change IOPL bits & so might be denied I/O permission, when its TSS is first created
• IOPL field & I/O Bitmap used in VM is different than protected mode
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• IOPL controls the following instruction only-– CLI– PUSHF– POPF– LOCK : assert bus lock signal– INT n : S/w interrupts– IRET(Sensitive instructions) which require VM86 monitor
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Entering & Leaving virtual-8086 mode
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Comparison between real, protected, virtual mode
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I/O Instructions
1. Register I/O instructions - e.g. IN AL, 30h
2. String I/O instructions- DS: ESI or ES: EDI registers
• I/O Handling in Pentium– I/O port addressing
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Unit - 4
Chapter – 3
Interrupt, Exception & IO
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Interrupt• Whenever the microprocessor is executing a
program, an if a user wants service to an I/O device then an external asynchronous i/p would inform the microprocessor that it should complete the execution of current instruction & then fetch a new routine that will service the requesting I/O device
• 3 Types of interrupt:1. Hardware interrupt2. Software interrupt3. Error condition(Exception or types)
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1. Hardware Interrupt- Physical pins are provided in the chip- This interrupts are generated by changing the logic levels on the interrupt pins
a) NMI (Non - maskable Interrupt)- compulsory execute- cannot be disabled- suitable for critical situations- when active type 2 interrupt is generated
b) Interrupt- maskable interrupt- enabled & disabled by …- level sensitive- priority mechanism
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2. Software Interrupt- generated by executing an instruction- The INT n instruction of the Pentium can be used to do one of the 256 interrupts (Type 0-255)
• Example: INT 0 instruction can be used to send execution to a divide by zero interrupt service routine
• With the help of these software interrupts we can call the routines from different programs in the system
• Example : BIOS
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3. Error Conditions (Exception or Types)• Divide by zero error
Interrupt Priority
Divide – error Highest
INT, INT 0 |
NMI |
INTR | V
Single - step Lowest
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Exception
• Exceptions(error codes) are generated by internal events
• While Interrupts are generated by external events
• Exceptions are divided into 3 groups depending on the way they are reported, & whether or not restart of the instruction causing an exception is supported
1) Faults2) Traps3) Aborts
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1) Faults: These are exceptions that are detected & serviced
before the execution of the faulting instruction Eg.: Faults in virtual memory system
2) Traps: These are exceptions that are reported
immediately after the execution of the instruction that caused the problem
Eg.: User defined interrupts
3) Aborts: Used to report severe errors such as a h/w error,
or illegal values in the system table
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IVT for real mode Exception Handling• Pentium supports total 256 types of interrupts
• Each of which reserve 4 bytes i.e. double word pointer
• Higher addressed word : New CS base address
• Lower addressed word: New IP– procedure’s offset from the beginning of the segment
• New CS: NEW IP – New physical address
• As each type, 4ytes(2 for CS & 2 for IP) are required , therefore it will occupy 1kb of low memory
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• The microprocessor receives NEW CS & NEW IP value from vector table, after calling ISR
• TYPE=4 location reserved- multiply the type with 4 that will give you address of that type
• Then 0CH/0DH location will provide OFFSET IP(NEW IP) and )EH/0FH will provide base address of the segment (New CS)