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Unit 3

Memories and memory

subsystem

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INTRODUCTION

Memory subsystemthe place within an

embedded system where instructions and

data are stored.

Major concern in design is the execution

time. This is taken care by the memory

management (static/ dynamic allocation of

memory)

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Classification of memory

MEMORY

RAM ROM

DRAM SRAM

SDRAM

PROM EPROM

EEPROM FLASH

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Random Access Memory (RAM)

It is the main memory in most

computers. One can read and over-write

data in RAM.

Can be classified as:

SRAM

DRAM

Both static and dynamicRAM are consideredvolat i le , as their state is lostor reset when power isremoved from the system.

In SRAM,a bit of datais storedusing the state of a flip-flop.

It is more expensiveto produce,

but is generally faster andrequires less power than DRAM.

In modern computers, SRAM isoften used as cache memory forthe CPU.

DRAM stores a bit of datausing a

transistor and capacitor pair,which together comprise amemory cell.

The capacitor holds a high or lowcharge (1 or 0, respectively), andthe transistor acts as a switchthat lets the control circuitry onthe chip read the capacitor's stateof charge or change it.

As this form of memory is lessexpensiveto produce than staticRAM, it is the predominant formof computer memory used in

modern computers.

http://en.wikipedia.org/wiki/Bithttp://en.wikipedia.org/wiki/Flip-flop_(electronics)http://en.wikipedia.org/wiki/Central_processing_unithttp://en.wikipedia.org/wiki/Central_processing_unithttp://en.wikipedia.org/wiki/Flip-flop_(electronics)http://en.wikipedia.org/wiki/Flip-flop_(electronics)http://en.wikipedia.org/wiki/Flip-flop_(electronics)http://en.wikipedia.org/wiki/Bit

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Read Only Memory (ROM) Stores data by permanently

enabling or disabling selectedtransistors, such that the

memory cannot be altered. Classified as:

Mask ROM

PROM

EPROM

EEPROM

FLASH

In mask ROM, the data isphysically encoded in thecircuit, so it can only beprogrammed duringfabrication

-

- PROM,invented in 1956,allowed users to program itscontents exactly once byphysically altering its structure

with the application of high-voltage pulses.

- The 1971 invention of EPROMessentially solved problemwith PROM, since EPROM canbe repeatedly reset to itsunprogrammed state by

exposure to strong ultravioletlight (typically for 10 minutesor longer).

- Repeated exposure to UV lightwill eventually wear out anEPROM, but the enduranceofmost EPROM chips exceeds

1000 cycles of erasing andreprogramming

-

http://en.wikipedia.org/wiki/Programmable_read-only_memoryhttp://en.wikipedia.org/wiki/EPROMhttp://en.wikipedia.org/wiki/Read-only_memoryhttp://en.wikipedia.org/wiki/File:EPROM_Intel_C1702A.jpghttp://en.wikipedia.org/wiki/File:EPROM_Intel_C1702A.jpghttp://en.wikipedia.org/wiki/Read-only_memoryhttp://en.wikipedia.org/wiki/EPROMhttp://en.wikipedia.org/wiki/Programmable_read-only_memory

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Read Only Memory (ROM)

EEPROM, invented in 1983,can be programmed in-placeif the containingdevice provides a meansto receive the programcontents from an externalsource (for example, a

personal computer via aserial cable).

- Writing is a very slowprocess and again needshigher voltage (usually

around 12 V)

Flash memory,invented at Toshiba

in the mid-1980s,and commercializedin the early 1990s, isa form of EEPROMthat makes very

efficient use of chiparea and can beerased andreprogrammedthousands of timeswithout damage.

http://en.wikipedia.org/wiki/EEPROMhttp://en.wikipedia.org/wiki/In-place_programmablehttp://en.wikipedia.org/wiki/In-place_programmablehttp://en.wikipedia.org/wiki/Serial_cablehttp://en.wikipedia.org/wiki/Volthttp://en.wikipedia.org/wiki/Flash_memoryhttp://en.wikipedia.org/wiki/Toshibahttp://en.wikipedia.org/wiki/Toshibahttp://en.wikipedia.org/wiki/Flash_memoryhttp://en.wikipedia.org/wiki/Volthttp://en.wikipedia.org/wiki/Serial_cablehttp://en.wikipedia.org/wiki/In-place_programmablehttp://en.wikipedia.org/wiki/In-place_programmablehttp://en.wikipedia.org/wiki/In-place_programmablehttp://en.wikipedia.org/wiki/EEPROM

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General memory interface The first level model of

memory can be viewed as

an ARRAY.

Each location in an array

will have an index no.

(address)

Read access

the binary

encoded address (index

value) can be decoded

and returns the stored

value. Write access-stores a

new value in the binary

encoded address (index

value)

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Common memory control signals CS-enables a memory

device for read/writeoperation.

OE-output control of amemory device.

R- indicates READoperation on the memorydevice.

W-indicates WRITEoperation on the memorydevice.

RAS-Indicates that theaddress inputs represents

a row address in thememory device.

CAS-Indicates that theaddress inputs representsa column address in the

memory device.

CONTROL

SIGNAL

MEANING

__

CS

Chip Select

___

OE

Output Enable

R Read

__

W

Write

____

RAS

Row Address Strobe

____

CAS

Column Address

Strobe

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Chip organization

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ROM timing diagram

Only READ operation

is possible. User has to give the

address.

When the CS is made

low, the data can be

read after a certain

processing time (tread)

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SRAM timing diagram

READ/WRITE both

are possible.

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SRAM CELL A typical SRAM cell is made up

of six MOSFETs.

Each bitin an SRAM is stored

on four transistors(M1, M2, M3,M4) that form two cross-coupled inverters.

This storage cell has twostable states which are used todenote 0 and 1.

Two additionalaccess

transistors serve to control theaccess to a storage cell duringread and write operations.

Access to the cell is enabledby the word line (WL in figure)which controls the two accesstransistors M5 and M6 which,in turn, control whether the cellshould be connected to the bitlines: BL and BL. They areused to transfer data for bothread and write operations.

http://en.wikipedia.org/wiki/MOSFEThttp://en.wikipedia.org/wiki/Bithttp://en.wikipedia.org/wiki/Transistorhttp://en.wikipedia.org/wiki/Transistorhttp://en.wikipedia.org/wiki/Bithttp://en.wikipedia.org/wiki/MOSFET

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SRAM cell

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DRAM Timing Diagram

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DRAM Cell

T i l

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Terminology Access time

Time to access a word inmemory.

Time taken for read/writeoperation.

Cycle time Time interval from the start

of one read/write operationuntil the start of the next.

It is the measure of howquickly the memory can berepeatedly accessed.

Memory bandwidth The measure of word

transmission rate to andfrom the memory by thebus.

Blocks large quantities of data are

transferred within a systemin blocks.

block sizeis the no. ofwords in a block.

Latency

Time required to computethe address of a sequenceof words and then locate itsfirst block in the memory.

Block Access Time

Time required to find the 0

th

word of the block and thentransfer the entire block.

Page Collection of blocks.

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Access time and cycle time

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The Primary physical memory map0xFFFF

0xE5FF

0x68FF

0x4FF

0x3FF

0x0

Memory mapped I/O

and DMA

Firmware

Volatile RAM

Non- Volatile

RAM(SRAM/DRAM)

Stack space

System memory

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Memory subsystem architecture It is comprised of a number of

memory components of differentkinds/sizes/speeds arranged in

hierarchical manner and designedto cooperate with each other.

Purpose of building a memorysystem is the reduce the memoryaccess timedepending upon the

application. Cache memory

Smallest

Fastest

Most expensive

Main/primary memory

SRAM/DRAM

Secondary memory

Slowest

Largest

Least expensive

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Need for Cachememory High speed memories are expensive and complex to design.

Also, the support circuitry for high speed memory device

will be complex and expensive.

Two main goalsof a good design of ES are:

To reduce the no. of memory accesses.

To reduce the latency of each memory access.

The cache is a smaller, faster memory which temporarily

stores copies of the block data and program instructions

from main memorylocations.

As long as most memory accesses are cached, the average

latencyof memory accesses will be very nominal.

Most modern desktop and server CPUs have independent caches for:

instruction cache (icache) to speed up executable instruction fetch

a data cache (dcache) to speed up data fetch

S ti l L lit f f

http://en.wikipedia.org/wiki/Main_memoryhttp://en.wikipedia.org/wiki/RAM_latencyhttp://en.wikipedia.org/wiki/RAM_latencyhttp://en.wikipedia.org/wiki/Main_memory

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Sequential Locality of reference 85% of the embedded software is

written in Embedded C.

IBM analyzed the flow of theseprograms and came out with aphenomenon called sequential localityof reference.

It states that actual execution

generally happens within a smallwindowthat moves forward throughthe program. These instructions canbe kept in a fast memory.

Thus execution speed is increased(asthe memory access time is reduced) ata reduced cost. (no need of high endsupport for high speed memories)

This concept failsif there are largeloops or repeated branches outsidethe window.

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Cache system architecture