Unit-1 Introduction Final

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1MC9224 – System SoftwareDepartment of Computer Applications

ADHIPARASAKTHI ENGINEERING COLLEGE

OmSakthi

Melmaruvathur-603 319

2MC9224- System SoftwareDepartment of Computer Applications


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Outline

Introduction

System Software and Machine Architecture

The Simplified Instructional Computer (SIC)

SIC Machine Architecture

SIC/XE Machine Architecture

SIC Programming Examples

1.1. Introduction



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System Software consists of a variety of programs that

support the operation of a computer.

The software makes it possible for the users to focus

on an application or other problem to be solved,

without needing to know the details of how the

machine works internally.

Example

operating system, compiler, assembler, macro processor,

loader or linker, debugger, text editor, database

management systems, software engineering tools, ….

1.1. Introduction



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Systems software can be classified in two groups based on

working environment:

1. Software to create a program development environment

Text editor

Compiler

AssemblerLinker

Debugger(low-level)

2. Software to create a run-time environment

Operating system

LoaderDynamic Linker

Program libraries

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1.1. Introduction



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Systems Software: Program Development Environment

Text editor: Software that permits the creation and editing of

text (i.e. application programs).

Compiler: Translates programs written in a high level

language to object code or machine code.

Assembler: Translates programs written in assembly language to

object code or machine code.

Static Linker: Combines and resolves references between object

programs and creates the executable code.

Debugger It is used to debug executable programs and their

(low-level) related object code and source program.

1.1. Introduction



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Systems Software: Run-Time Environment

Loader:

Loads an executable code and starts its execution

Libraries:

Precompiled programs the creates a set of functions for use by other

programs.

Dynamic Linker:

Loads and links shared libraries at run-time

Operating system:

An event driven program that make an abstraction of the computer system.

The operating system handles all resources efficiently, creates an

environment for application programs to run, and creates a friendly interface

between the user and the computer system.

1.1. Introduction



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A compiler

Compiler

source program

target program

Target Programinput output

Running a Target Program

-Language Processors 1.1. Introduction



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An interpreter

Much slower program execution

Better error diagnostics

Interpretersource program

inputoutput

-Language Processors

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1.1. Introduction



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-Language Processors

A hybrid compiler, e.g. Java

Virtual

Machineinput

output

Translator

source program

intermediate program

1.1. Introduction



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-Language Processing System

Compiler

source program

target machine code

Preprocessor

Assembler

Linker/Loader

modified source program

target assembly program

relocatable machine code

library files

relocatable object files

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-Traditional Compilation



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Machine dependency of system software

System programs are intended to support the operation

and use of the computer itself, rather than any particular

application.

Machine architecture differs in: Machine code

Instruction formats

Addressing mode

Registers

Machine independency of system software

General design and logic is basically the same: Code optimization

Subprogram linking

1.2. System software and MachineArchitecture

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1.2. System software and MachineArchitecture



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People

Application Program Utility Program (Library)

Debugging Aids Macro Processor Text Editor

Compiler Assembler Loader and Linker

OS

Memory Processor Device Information

Management and Process Management Management

Management

Bare Machine (Computer)

SP

1.3. The Simplified Instructional Computer



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SIC is a hypothetical computer that includes the

hardware features most often found on real machines,

while avoiding unusual or irrelevant complexities

Like many other products, SIC comes in two versions

The standard model (SIC)

An XE version (SIC/XE)

“extra equipments”, “extra expensive”

The two versions has been designed to be upward

compatible

1.3. 1. SIC Machine Architecture



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Memory

Memory consists of 8-bit bytes, 15-bit addresses

Any 3 consecutive bytes form a word (24 bits)

Total of 32768 (215) bytes in the computer memory

Registers

Five registers, each is 24 bits in length

Mnemonic Number Special use

A 0 Accumulator

X 1 Index register

L 2 Linkage register

PC 8 Program counter

SW 9 Status word



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Data Formats

Integers are stored as 24-bit binary number

2’s complement representation for negative

values

Characters are stored using 8-bit ASCII codes

No floating-point hardware on the standard

version of SIC

+3=00000011

-3 =11111100+1=11111101


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Instruction format

24-bit format

The flag bit x is used to indicate indexed-

addressing mode

8 1 15

opcode x address




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Addressing Modes

There are two addressing modes available

Indicated by x bit in the instruction

(X) represents the contents of reg. X

Mode Indication Target address calculation

Direct x=0 TA=address

Indexed x=1 TA=address+(X)




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Instruction Set Load and store registers

LDA, LDX, STA, STX, etc.

Integer arithmetic operations ADD, SUB, MUL, DIV

All arithmetic operations involve register A and a wordin memory, with the result being left in A

COMPCOMP compares the value in register A with a word in memory, this instruction sets a condition code CC to indicate the result




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Instruction Set

Conditional jump instructions JLT, JEQ, JGT

Subroutine linkage JSUB, RSUB

I/O transferring 1 byte at a time to/from the rightmost 8

bits of register A

Each device is assigned with 8-bit unique code Test Device instruction (TD) [ < ready and = not ready]

Read Data (RD)

Write Data (WD)


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1.3. 2. SIC/XE Machine Architecture



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Memory1 megabytes (1024 KB) in memory – 220 bytes memory

More Registers

3 additional registers, 24 bits in length

B 3 Base register; used for addressing

S 4 General working register

T 5 General working registers

1 additional register, 48 bits in length

F 6 Floating-point Accumulator (48 bits)




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Data format

24-bit binary number for integer, 2’s complement for

negative values

48-bit floating-point data type

The exponent is between 0 and 2047

f*2(e-1024)

0: set all bits to 0

1 11 36

s exponent fraction




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Format 1

op(8)

Format 2

op(8) r1(4) r2(4)

Format 3 e=0

op(6) n i x b p e disp(12)

Format 4 e=1

op(6) n i x b p e address (20)

Instruction format

larger memory -> extend addressing capacity

Formats 1 and 2 do not reference memory at all

Bit e distinguishes between format 3 and 4




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Addressing Modes

Mode Indication Target Address Calculation

Base Relative b=1, p=0 TA=(B)+disp (0<=disp<=4095)

Program Counter Relative

b=0, p=1 TA=(PC) +disp (-2048 <= disp <=2047)

Direct b=0,p=0 TA = disp (format 3) or address (format 4)

Indexed x=1 TA = TA + (X)

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Addressing Modes How the target address is used?

Note: Indexing cannot be used with immediate or indirect addressing

modes

Mode Indication Target Address Calculation

Immediate Addressing n=0, i=1 TA

Indirect Addressing n=1, i=0 (TA)

Simple Addressingn=0,i=0

SIC instruction (all end with 00) TA=bpe+disp, opcode=opcode+n+i

n=1, i=1 SIC/XE instruction, TA=disp




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Benefits of Addressing Modes Register-to-register instructions

Shorter than register-to-memory instructions No memory reference

Immediate addressing mode No memory reference. The operand is already

present as part of the instruction

Indirect addressing mode Avoids the needs for another instruction

Relative addressing mode Shorten than the extended instruction Easy program relocation




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Addressing Modes




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Extended format: +op m

Indirect addressing: op @m

Immediate addressing: op #c

Index addressing: op m,X

Relative addressing: op m 1st choice: PC relative (arbitrarily chosen)

2nd choice: base relative (if displacement isinvalid in PC relative mode)

3rd choice: error message (if displacement isinvalid in both relative modes)

How Assembler recognizes Addressing Modes?

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Instruction Set new registers: LDB, STB, etc. floating-point arithmetic: ADDF, SUBF, MULF, DIVF register move: RMO register-register arithmetic: ADDR, SUBR, MULR,

DIVR supervisor call: SVC

generates an interrupt for OS (Chap 6)

Input/Output SIO, TIO, HIO: start, test, halt the operation of I/O

device (Chap 6)




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data movement

immediate addressing for SIC/XE

arithmetic

Looping (TIXR)

(X)=(X)+1

compare with register specified

set CC




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Instruction set Format 1, 2, 3, or 4

Load and store registers (LDB, STB, etc.)

Floating-point arithmetic operations (ADDF, SUBF, MULF,

DIVF)

Register Move instruction (RMO)

Register-to-register arithmetic operations (ADDR, SUBR,

MULR, DIVR)

A special supervisor call instruction (SVC) is provided

I/O 1 byte at a time, TD, RD, and WD

SIO, TIO, and HIO are used to start, test, and halt the

operation of I/O channels.

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1.3. 3. SIC and SIC/XE Programming Examples



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1. Data movement (SIC)

Alpha=5 and C1 = ‘Z’

LDA FIVE load 5 into A

STA ALPHA store in ALPHA

LDCH CHARZ load ‘Z’ into A

STCH C1 store in C1

.

.

.

ALPHA RESW 1 reserve one word space

FIVE WORD 5 one word holding 5

CHARZ BYTE C’Z’ one-byte constant

C1 RESB 1 one-byte variable



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1. Data movement

Alpha=5 and C1 = ‘Z’

LDA #5

STA ALPHA

LDCH #90

STCH C1

.

.

.

ALPHA RESW 1

C1 RESB 1

LDA FIVE

STA ALPHA

LDCH CHARZ

STCH C1

.

.

.

ALPHA RESW 1

FIVE WORD 5

CHARZ BYTE C’Z’

C1 RESB 1

SIC version SIC/XE version



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2. Arithmetic Operations (SIC)BETA= ALPHA+INCR-1 and DELTA=GAMMA+INCR + 1

LDA ALPHA

ADD INCR

SUB ONE

STA BETA

LDA GAMMA

ADD INCR

ADD ONE

STA DELTA

...

ONE WORD 1 one-word constant

ALPHA RESW 1 one-word variables

BETA RESW 1

GAMMA RESW 1

DELTA RESW 1

INCR RESW 1

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2. Arithmetic Operations (SIC/XE)BETA= ALPHA+INCR-1 and DELTA=GAMMA+INCR=1

LDS INCR

LDA ALPHA for BETA=ALPHA+INCR-1

ADDR S,A

SUB #1

STA BETA

LDA GAMMA for DELTA=GAMMA+INCR + 1

ADDR S,A

ADD #1

STA DELTA

...

...

ALPHA RESW 1 one-word variables

BETA RESW 1

GAMMA RESW 1

DELTA RESW 1

INCR RESW 1



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3. Looping & Indexing : copying string(SIC)

STR2=STR1 where STR1=‘TEST STRING’

LDX ZERO initialize index register to 0MOVECH LDCH STR1,X load char from STR1 to reg A

STCH STR2,X

TIX ELEVEN add 1 to index, compare to 11JLT MOVECH loop if “less than”.

.

.

STR1 BYTE C’TEST STRING’

STR2 RESB 11

ZERO WORD 0

ELEVEN WORD 11



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3. Looping & Indexing : copying string(SIC/XE)

STR2=STR1 where STR1=‘TEST STRING’

LDT #11 initialize register T to 11LDX #0 initialize index register to 0

MOVECH LDCH STR1,X load char from STR1 to reg ASTCH STR2,X store char into STR2TIXR T add 1 to index, compare to 11JLT MOVECH loop if “less than” 11.

.

.

STR1 BYTE C’TEST STRING’

STR2 RESB 11



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3. Looping & Indexing : adding 2 arrays (SIC)GAMMA[i] = ALPHA[i] + BETA[i]

LDA ZERO initialize index value to 0STA INDEX

ADDLP LDX INDEX load index value to reg XLDA ALPHA,X load word from ALPHA into reg AADD BETA,XSTA GAMMA,X store the result in a word in GAMMALDA INDEXADD THREE add 3 to index valueSTA INDEXCOMP K300 compare new index value to 300JLT ADDLP loop if less than 300......

INDEX RESW 1ALPHA RESW 100 array variables—100 words eachBETA RESW 100GAMMA RESW 100ZERO WORD 0 one-word constantsTHREE WORD 3K300 WORD 300

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3. Looping & Indexing : adding 2 arrays (SIC/XE)

GAMMA[i] = ALPHA[i] + BETA[i]

LDS #3

LDT #300

LDX #0

ADDLP LDA ALPHA,X load from ALPHA to reg AADD BETA,X

STA GAMMA,X store in a word in GAMMAADDR S,X add 3 to index valueCOMPR X,T compare to 300JLT ADDLP loop if less than 300...

...

ALPHA RESW 100 array variables—100 words eachBETA RESW 100

GAMMA RESW 100



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4. I/O Operation (SIC)INLOOP TD INDEV test input device

JEQ INLOOP loop until device is readyRD INDEV read one byte into register ASTCH DATA

.

.

OUTLP TD OUTDEV test output deviceJEQ OUTLP loop until device is readyLDCH DATA

WD OUTDEV write one byte to output device.

.

INDEV BYTE X’F1’ input device numberOUTDEV BYTE X’05’ output device numberDATA RESB 1



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4. I/O Operation (SIC/XE)INLOOP TD INDEV test input device

JEQ INLOOP loop until device is readyRD INDEV read one byte into register ASTCH DATA

.

.

OUTLP TD OUTDEV test output deviceJEQ OUTLP loop until device is readyLDCH DATA

WD OUTDEV write one byte to output device.

.

INDEV BYTE X’F1’ input device numberOUTDEV BYTE X’05’ output device numberDATA RESB 1



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5. Subroutine Call and record input Operation (SIC)

JSUB READ call READ Subroutine

.

.

READ LDX ZERO Initialize control register to 0

RLOOP TD INDEV Test Input Device

JEQ RLOOP Loop if Device is busy

RD INDEV Read 1 byte into register A

STCH RECORD,X Store read byte into record

TIX K100 Add 1 to Index and Compare to 100

JLT RLOOP Loop if index is < 100

RSUB Return from Subroutine

.

.

INDEV BYTE X’F1’ Input Device Number

RECORD RESB 100 100 byte Buffer for Input Record

. One word constants

ZERO WORD 0

K100 WORD 100

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5. Subroutine Call and record input Operation (SIC/XE)

JSUB READ call READ Subroutine

.

.

READ LDX #0 Initialize control register to 0

#100 Initialize register T to 100

RLOOP TD INDEV Test Input Device

JEQ RLOOP Loop if Device is busy

RD INDEV Read 1 byte into register A

STCH RECORD,X Store read byte into record

TIXR T Add 1 to Index and Compare to 100

JLT RLOOP Loop if index is < 100

RSUB Return from Subroutine

.

.

INDEV BYTE X’F1’ Input Device Number

RECORD RESB 100 100 byte Buffer for Input Record

Exercises



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Solve Exercises from 1 to 13 from the Text Book page numbered 40-41.

Unit-1 Introduction Final

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