Unified Patents Inc. v. Advanced Silicon Technologies, LLC, IPR2016-01060, Paper 3 (May 19, 2016)

8/16/2019 Unified Patents Inc. v. Advanced Silicon Technologies, LLC, IPR2016-01060, Paper 3 (May 19, 2016)

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IPR2016-01060 Petition

Patent 8,933,945

DOCKET NO.: 2211726-00125

Filed on behalf of Unified Patents Inc.

By: David L. Cavanaugh, Reg. No. 36,476

Daniel V. Williams 45,221

Wilmer Cutler Pickering Hale and Dorr LLP1875 Pennsylvania Ave., NW

Washington, DC 20006

Tel: (202) 663-6000

Email: [email protected]

Jonathan Stroud, Reg. No. 72,518

Unified Patents Inc.

1875 Connecticut Ave. NW, Floor 10

Washington, DC, 20009

Tel: (202) 805-8931Email: [email protected]

UNITED STATES PATENT AND TRADEMARK OFFICE

____________________________________________

BEFORE THE PATENT TRIAL AND APPEAL BOARD

____________________________________________

UNIFIED PATENTS INC.

Petitioner

v.

ADVANCED SILICON TECHNOLOGIES, LLC

Patent Owner

IPR2016-01060

Patent 8,933,945

PETITION FOR INTER PARTES REVIEW OF

US PATENT NO. 8,933,945

CHALLENGING CLAIMS 1-3, 9, 10, AND 21

UNDER 35 U.S.C. § 312 AND 37 C.F.R. § 42.104


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TABLE OF CONTENTS

Page

I. MANDATORY NOTICES ............................................................................. 1

A. Real Party-in-Interest ............................................................................ 1

B. Related Matters ...................................................................................... 1

C. Counsel .................................................................................................. 2

D. Service Information, Email, Hand Delivery and Postal ........................ 2

II. CERTIFICATION OF GROUNDS FOR STANDING .................................. 2

III. OVERVIEW OF CHALLENGE AND RELIEF REQUESTED .................... 2

A.

Prior Art Patents and Printed Publications ............................................ 3

1. European Patent Application No. 1 195 717 (filed on August

21, 2001 based on priority date of October 4, 2000;

published on April 10, 2002) (“Seiler ” (EX1002)), which is

prior art under 35 U.S.C. § 102(a) .............................................. 3

2. US Pat. 6,864,896 (filed on May 15, 2001; published on

November 21, 2002) (“ Perego” (EX1003)), which is prior

art under 35 U.S.C. § 102(e) ....................................................... 3

3. US Pat. 5,757,385 (filed on January 30, 1996, claiming

priority to July 21, 1994; published on May 26, 1998)(“ Narayanaswami” (EX1004)), which is prior art under 35

U.S.C. § 102(b) ........................................................................... 3

B. Grounds for Challenge .......................................................................... 3

IV. TECHNOLOGY BACKGROUND ................................................................. 4

V. OVERVIEW OF THE ’945 PATENT ............................................................ 8

A.

Summary of the Alleged Invention ....................................................... 8 B. Level of Ordinary Skill in the Art ....................................................... 12

C. Prosecution History ............................................................................. 12

VI. CLAIM CONSTRUCTION .......................................................................... 18

A. “graphics pipeline” .............................................................................. 19


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VII. SPECIFIC GROUNDS FOR PETITION ...................................................... 20

A. Ground I: Claims 1-3, 9, 10, and 21 are rendered obvious by Seiler in

view of Perego .................................................................................... 20

1. Overview of Seiler .................................................................... 20

2. Overview of Perego .................................................................. 29

3. Motivation to combine Seiler and Perego ................................ 32

4. Claim 1 is obvious in view of Seiler and Perego ..................... 34


6. Claim 3 obvious in view of Seiler and Perego ......................... 49


8. Claim 10 is obvious in view of Seiler and Perego ................... 50

9. Claim 21 is obvious in view of Seiler and Perego ................... 51

B. Ground II: Claims 1, 9, 10, and 21 are rendered obvious by

Narayanaswami in view of Seiler........................................................ 54

1. Overview of Seiler .................................................................... 54

2. Overview of Narayanaswami ................................................... 54

3. Motivation to combine Narayanaswami and Seiler ................. 58

4. Claim 1 is obvious in view of Narayanaswami and Seiler ....... 60

5. Claim 9 is obvious in view of Narayanaswami and Seiler ....... 75

6. Claim 10 is obvious in view of Narayanaswami and Seiler ..... 75

7.

Claim 21 is obvious in view of Narayanaswami and Seiler ..... 76

VIII. CONCLUSION .............................................................................................. 80


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I.

MANDATORY NOTICES

A.

Real Party-in-Interest

Pursuant to 37 C.F.R. § 42.8(b)(1), Unified Patents Inc. (“Unified” or

“Petitioner”) certifies that Unified is the real party-in-interest, and further certifies

that no other party exercised control or could exercise control over Unified’s

participation in this proceeding, the filing of this petition, or the conduct of any

ensuing trial. In this regard, Unified has submitted voluntary discovery. See

EX1015 (Petitioner’s Voluntary Interrogatory Responses).

B.

Related Matters

US Pat. No. 8,933,945 (“’945 Patent” (EX1001)) is owned by Advanced

Silicon Technologies, LLC (“AST” or “Patent Owner”). On December 21, 2015,

AST filed lawsuits in the US District Court for the District of Delaware against

multiple companies, claiming that these companies’ products and/or services

infringe the ’945 Patent. AST also filed a Section 337 Action in the International

Trade Commission on December 27, 2015 against multiple companies, seeking to

exclude from importation certain components and products incorporating

computing and graphics systems that allegedly infringe the ’945 Patent.


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C.

Counsel

David L. Cavanaugh (Reg. No. 36,476) will act as lead counsel; Jonathan

Stroud (Reg. No. 72,518) and Daniel Williams (Reg. No. 45,221) will act as back-

up counsel.

D.

Service Information, Email, Hand Delivery and Postal

Unified consents to electronic service at [email protected]

and [email protected]. Petitioner can be reached at Wilmer Cutler

Pickering Hale and Dorr, LLP, 1875 Pennsylvania Ave., NW, Washington, DC

20006, Tel: (202) 663-6000, Fax: (202) 663-6363, and Unified Patents Inc., 1875

Connecticut Ave. NW, Floor 10, Washington, DC 20009, (650) 999-0899.

II.

CERTIFICATION OF GROUNDS FOR STANDING

Petitioner certifies pursuant to Rule 42.104(a) that the patent for which

review is sought is available for inter partes review and that Petitioner is not

barred or estopped from requesting an inter partes review challenging the patent

claims on the grounds identified in this Petition.

III.

OVERVIEW OF CHALLENGE AND RELIEF REQUESTED

Pursuant to Rules 42.22(a)(1) and 42.104(b)(1)–(2), Petitioner challenges

claims 1-3, 9, 10, and 21 of the ’945 Patent.


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A.

Prior Art Patents and Printed Publications

The following references are pertinent to the grounds of unpatentability

explained below:1

1. European Patent Application No. 1 195 717 (filed on August

21, 2001 based on priority date of October 4, 2000; published

on April 10, 2002) (“Seiler ” (EX1002)), which is prior art

under 35 U.S.C. § 102(a)

2.

US Pat. 6,864,896 (filed on May 15, 2001; published on

November 21, 2002) (“ Perego” (EX1003)), which is prior artunder 35 U.S.C. § 102(e)

3.

US Pat. 5,757,385 (filed on January 30, 1996, claiming priority

to July 21, 1994; published on May 26, 1998)

(“ Narayanaswami” (EX1004)), which is prior art under 35

U.S.C. § 102(b)

B.

Grounds for Challenge

This Petition, supported by the declaration of Professor Sudhakar

Yalamanchili (“Yalamanchili Declaration” or “Yalamanchili” (EX1005)), requests

cancellation of challenged claims 1-3, 9, 10, and 21 as unpatentable under 35

U.S.C. § 103. See 35 U.S.C. § 314(a).

1 The ’945 patent issued from a patent application filed prior to enactment of the

America Invents Act (“AIA”). Accordingly, pre-AIA statutory framework applies.


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IV.

TECHNOLOGY BACKGROUND

When the ’945 patent was filed, computer graphics systems often included a

host processor or central processing unit (CPU), graphics processing circuitry, and

memory. Such systems relied on peripheral processors and dedicated peripheral

memory units to perform various processing operations. For example, peripheral

graphics processors may have been used to render graphics images.

It was known to provide memory in separate units, such as main memory

and a dedicated graphics memory. The main memory provides fast access to data

for the CPU. Dedicated graphics memory provides fast access to graphics data for

the graphics processor or graphics processing circuitry. CPUs and graphics

processors are typically connected to their memory through a memory controller.

The high cost of using multiple memory units drove many systems to use a single

unified memory system that can be shared by multiple processors in the system

without transferring data between multiple dedicated memory units. (Yalamanchili

¶ 12 (EX1005)). A frame buffer, which is a form of memory, is typically a portion

of RAM containing information that is driven to a video display. The information

in the frame buffer may include, for example, color values for pixels on the screen.

( Id. ¶ 12 (EX1005)).

In 2000, a graphics accelerator called KRYO was released and described in a

“Product Overview.” (KYRO at p. 1 (EX1006)). As shown below in a figure from


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the product overview, KYRO discloses a “single chip” device having “twin high-

performance texturing pipeline” for processing image data. (KYRO at 3

(EX1006)). The graphics accelerator is a “single chip” device. (KYRO at 3

(EX1006)).

Graphics information rendered by the twin pipelines is sent through a memory

controller, i.e., SDRAM/SGRAM Interface, to a frame buffer. (KYRO at 3

(EX1006)). The frame buffer is a “single memory.” (KYRO at 1 (EX1006)). The

KYRO device is described as performing processing steps, including tak[ing] a


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whole scene of data to be rendered” and “partition[ing] the data into screen

tiles….” (KYRO at 5 (EX1006)).

Moreover, well before the alleged November 2002 effective filing date of

the ’945 patent, it was known to process data in a tiled format and to use multiple

graphics pipelines or rendering engines. (Yalamanchili ¶ 15 (EX1005)). For

example, U.S. Pat. No. 6,781,588 (“Margittai”), filed in September 2001, discloses

to use multiple pipelines that share a common memory. Margittai further teaches

to balance graphics processing operations between the pipelines to improve

efficiency.

U.S. Pat No. 6,657,635, filed in August 2000 based on a provisional

application filed in September 1999, discloses to place a rendering engine on the

same chip as a memory controller for processing image data in a tile format. U.S.

Pat. No. 6,801,202, filed in June 2001 based on a provisional application filed in

June 2000, discloses to use multiple graphics rendering unit on a single chip. U.S.

Pat. No. 6,819,321, filed in March 2000, discloses to use multiple rendering

engines on a single chip for processing data in tiled format. U.S. Pat. No.

6,952,214 (“Naegle”), filed in July 2002, also discloses to use multiple rendering

pipelines on the same chip to process data. Naegle further discloses to organize

data into an array of spatial bins that define a rectangular window in a virtual

screen space and perform texturing on the resultant visible pixels.


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Multiple papers also make clear that it was well known to perform graphics

processing using tiling and mapping of tiles to rendering engines based on screen

area. For example Fuchs2 describes the partitioning of screen area in to square

patches that are allocated to distinct rendering engines operating in parallel (Fuchs,

Figure 1) and sharing a common frame buffer (Fuchs at Figure 2). (Yalamanchili ¶

17 (EX1005)). Similarly Crockett3 describes an overview of parallel rendering

algorithms as having “been applied to virtually every image generation technique

used in computer graphics….” (Crocket at 820). (Yalamanchili ¶ 17 (EX1005)).

He goes on to provide the advantages of using square regions of the image (tiles)

for image parallel algorithms (Crockett at Figure 6). (Yalamanchili ¶ 17

(EX1005)). Foley4 is a seminal text on computer graphics. Figure 18.17 of Foley

explicitly discloses the mapping of square regions (tiles) in the frame buffer to

2 Fuchs, Henry et al.; Pixel-Planes 5: A Heterogeneous Multiprocessor Graphics

System Using Processor-Enhanced Memories; Computer Graphics; vol. 23, No. 3;

Jul. 1989; pp. 79-88.

3 Crockett, Thomas W.; An introduction to parallel rendering; Elsevier Science

B.V.; 1997; pp. 819-843.

4 Foley, James et al.; Computer Graphics, Principles and Practice; Addison-Wesley

Publishing Company; 1990; pp. 873-899.


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rendering engines. ( Id. ¶ 17 (EX1005)). These references reveal that partitioning

the image space into tiles as discussed in the ’945 patent and mapping tiles to

parallel rendering engines (equivalently graphics pipelines) was well known in the

prior art. ( Id. ¶ 17 (EX1005)).

V.

OVERVIEW OF THE ’945 PATENT

A.

Summary of the Alleged Invention

The ’945 patent is directed to dividing work among multiple graphics

pipelines. (’945 patent at 4:5-15 (EX1001)). These pipelines are shown below in

Figure 2, which has color added, as elements 101 and 102. (’945 patent at 4:5-15

(EX1001)); (Yalamanchili ¶ 18 (EX1005)). The pipelines are part of a “graphics

processing circuit 34.” (’945 patent at 4:5-13 (EX1001)). The pipelines are

described as operating independently of one another to process data for sets of tiles

that correspond to screen locations on a display device. ( Id. at 4:5-13, 5:66-6:5

(EX1001)). A memory 48 is provided to store pixel data corresponding to the tiles.

( Id. at 5:46-53 (EX1001)). A memory controller 46 controls the flow of data to the

memory 48. ( Id. at 5:4-7, Figure 2 (EX1001)). The memory 48 may be a “frame

buffer.” ( Id. at 6:15-16, 10:14-15 (EX1001)).


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The ’945 patent acknowledges that it was known to use multiple pipelines

for processing data corresponding to different regions of a display. (’945 patent at

2:5-13 (EX1001)); (Yalamanchili ¶ 19 (EX1005)). For example, Figure 1 of ’945

patent, reproduced below, provides a “display device 10, having a screen 12

partitioned into a series of vertical strips 13-18.” (’945 patent at 1:44-45

(EX1001)).


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The ’945 patent explains that “the frame buffer of conventional graphics

processing systems is partitioned into a series of vertical strips having the same

screen space width.” ( Id. at 1:46-49 (EX1001)). The ’945 patent also discloses

that it was known to partition a buffer for corresponding screen locations into a

series of horizontal strips. ( Id. at 1:49-51 (EX1001)); (Yalamanchili ¶ 20

(EX1005)).

The alleged invention of the ’945 patent is to partition the screen into a tiled

format, instead of strips, as shown below in Figure 3. (’945 patent at 5:66-6:9

(EX1001)); (Yalamanchili ¶ 21 (EX1005)). The respective pipelines 101 and 102,


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shown in Figure 2, are responsible for processing data for the tiles. (’945 patent at

5:66-6:5 (EX1001)).

Although claim 1 includes limitations such “on a same chip” and “memory

[that is] shared”, these features are not directly related to the purported inventive

advancement, i.e., the tiling feature, and (2) the “same chip” and shared memory

features were well-known in the art, as discussed below in more detail.

(Yalamanchili ¶ 22 (EX1005)). The shared memory aspect was vigorously argued

during prosecution as not being taught or suggested by the prior art. However, the

’945 patent does not provided details on how this “shared memory” advances the

purported invention. ( Id. ¶ 22 (EX1005)). In fact, the term “shared memory” or


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even “shared” is not found in the detailed description of the ’945 patent. ( Id. ¶ 22

(EX1005)).

B.

Level of Ordinary Skill in the Art

A person of ordinary skill in the art at the time of filing the provisional

application for the ’945 patent, i.e., November 27, 2002, would be familiar with

computer graphics and have at least the equivalent of a Bachelor of Science degree

in electrical or computer engineering, with multiple years of experience in the field

of computer hardware architecture design, development, or evaluation.

(Yalamanchili ¶ 34 (EX1005)). A higher level of education may make up for less

experience. ( Id. ¶ 34 (EX1005)).

C.

Prosecution History

The ’945 Patent issued from US Pat. Appl. No. 10/459,797, which was filed

on June 12, 2003 (File History, Application (6/12/03) (EX1007)), and allegedly

claims priority to November 27, 2002 based on Provisional application No.

60/429,641. (’945 Patent at 1:5–9 (EX1001)). Ten Office Actions on the merits

were issued during prosecution of the ’945 Patent. Salient portions of the file

history are discussed below in detail.

In an Office Action dated August 28, 2007, the Examiner set forth a new

ground of rejection using Perego to show that the claimed tiling feature was

known.


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“As per Claims 1 and 25, Perego teaches graphics

processing circuit (300, Fig. 3; Col. 3, ll. 61-63) having at

least two graphics pipelines (312) operative to process

data in corresponding set of tiles of repeating tile pattern

corresponding to screen locations, respective one of at

least two graphics pipelines operative to process data in a

dedicated tile (c. 5, ll. 19-27, 38-44)….”

(File History, Non-Final Office Action at 4 (8/28/2007 (EX1008)).

In an effort to distinguish over Perego, Applicants amended claims 1 and 25

to require that the “at least two graphics pipelines” are “on the same chip,” as

shown below in the image reproductions from the file history. Claim 1 further

required that the “memory controller” also be “on the chip.”


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(File History, Amendment at 3, 8 (11/28/07) (EX1009). To support the

amendment, Applicants argued as follows.

“ Perego does not describe multi-graphics pipeline

circuitry on a same chip nor a memory controller on the

same chip but instead describes discrete memory

modules having separate and single graphics engines

thereon. In addition, the memory controller described in

Perego is not on a same chip nor is it part of the memory

module as described in Perego. As such, the Perego

reference does not anticipate Applicants’ claimed subject

matter.”

( Id. at 10 (11/28/2007 (emphasis added) (EX1009)).

The Examiner was not convinced and issued a new grounds or rejection

relying on Perego and two secondary references, U.S. Pat. No. 6,778,177


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(“Furtner”) and U.S. Pat. No. 6,570,579 (“MacInnis”). Furtner and MacInnis were

applied for cumulatively teaching that it was known to place multiple graphics

pipelines on the same chip as a memory controller. (File History, Final Office

Action at 3, 4 (2/4/08) (EX1010)). Multiple Requests for Continued Examination

were filed without the claims being allowed.

In July 2009, the claims remained rejected, but instead of the Examiner

relying on the combination of Perego, Furtner and MacInnis, the Examiner applied

a combination of only MacInnis and Perego against the independent application

claims 1 and 25. (File History, Non-Final Office Action at 6, 7 (7/23/09)

(EX1011)). Perego was still applied for disclosing the claimed tile related

features. ( Id. at 7 (7/23/09) (EX1011)).

In response, on January 25, 2010, Applicants amended independent

application claims 1 and 25 to require a “memory shared among the at least two

graphics pipelines” and argued that these features were not taught by the prior art.

(File History, Amendment at 2, 7, 9-11 (1/25/10) (EX1012)). To support the

amendments, Applicants argued as follows

“Applicants have amended claims to indicate what is

believed to be inherent subject matter, that the memory

controller that is on chip with the at least two graphics

pipelines transfers pixel data between each of the first


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and second pipelines and a memory that is shared among

the at least two on chip pipelines.”

( Id. at 9 (1/25/10) (emphasis added) (EX1012)). Applicants further argued that

“MacInnis is a conventional graphics processing circuit that includes a single

pipeline and corresponding memory controller on chip.” ( Id. (1/25/10) (EX1012)).

The claims were not amended further after the January 25, 2010 Amendment.

Applicants filed a Notice of Appeal on July 22, 2010.

Applicants argued that the graphics pipelines of Perego, which are shown as

rendering engines, do not “access the same memory” and instead each have

“separate, dedicated memory.” (File History, Appeal Brief at 18 (EX1013).

Applicants conceded that the memory in Perego is shared, but argued that there is

no explicit disclosure of the rendering engines sharing memory. Instead,

Applicants argued that the memory is shared between a CPU and a single graphics

pipeline. ( Id. at 17 (EX1013) (“[t]he Perego teachings instead describe main

memory of a CPU that is shared with a single graphics pipeline. Multiple pipelines


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in Perego do not share the same graphics memory.”))5 The Applicants maintained

the same position in its Reply Brief. (File History, Reply Brief at 1-2 (EX1014)).

The only dispositive issue set for by the Patent Trial and Appeal Board

(“Board”) with respect to application claims 1 and 25 was “Did the Examiner err in

finding that the combination of MacInnis and Perego teach a memory shared

among the graphics pipelines?” (File History, Decision on Appeal at 3 (6/26/2014)

(EX1015)). The Board reversed the Examiner based on the shared memory

limitation, resulting in application claims 1 and 25 being allowed. ( Id. at 4-6

(6/26/2014) (EX1015)).

The Board’s decision was necessitated in part by MacInnis’s disclosure

being limited to a single rendering engine. In particular, the Board noted that

“[t]he Examiner has not found that MacInnis teaches this feature,” i.e., memory

that is shared between individual rendering engines. ( Id. at 4 (6/26/2014)

(EX1015)). The Board further asserted that “[t]he Examiner has not found that

Kelleher, Furtner, Kent, or Hamburg teaches the shared memory as recited in

independent application claims 1 [and 25]. Accordingly, we similarly will not

5 One of ordinary skilled in the art would have considered the individual rendering

engines of Perego to each be a single “graphics pipeline,” which is consistent with

Applicants’ explicit comments in the Appeal Brief.


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sustain the Examiner's rejection ….” ( Id. at 5 (emphasis added) (6/26/2014)

(EX1015)). The Notice of Allowability issued on September 4, 2014 with no

statement regarding the reasons for allowance. Application claim 25 issued as

independent claim 21. However, the use of multiple graphics pipelines that share

memory was well known in the art before the priority date of the ’945 patent.

(Yalamanchili ¶ 33 (EX1005)). Further, it was well known to put these features

onto a single chip, as discussed below in more detail. ( Id. ¶ 33 (EX1005)).

Unfortunately, the Examiner and the Board did not have possession of this prior art

during prosecution.

VI.

CLAIM CONSTRUCTION

Claim terms of an unexpired patent in inter partes review are given the

“broadest reasonable construction in light of the specification.” 37 C.F.R. §

42.100(b); In re Cuozzo Speed Techs., LLC 778 F.3d 1271, 1279–81 (Fed. Cir.

2015). Any claim term that lacks a definition in the specification is therefore given

a broad interpretation.6 In re ICON Health & Fitness, Inc., 496 F.3d 1374, 1379

(Fed. Cir. 2007). Under the broadest reasonable interpretation standard, claim

6 Petitioner applies the “broadest reasonable construction” standard as required by

the governing regulations. 37 C.F.R. § 42.100(b). Petitioner reserves the right to

pursue different constructions in a district court, where a different standard is

applicable.


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terms are given their ordinary and customary meaning, as they would be

understood by one of ordinary skill in the art, in the context of the disclosure. In re

Translogic Tech., Inc., 504 F.3d 1249, 1257 (Fed. Cir. 2007). Any special

definition for a claim term must be set forth in the specification with “reasonable

clarity, deliberateness, and precision.” In re Paulsen, 30 F.3d 1475, 1480 (Fed.

Cir. 1994).

The following proposes a construction and offers support for that

construction. Any claim terms not included should be given their broadest

reasonable interpretation in light of the specification, as commonly understood by

those of ordinary skill in the art. Should the Patent Owner, to avoid the prior art,

contend that a claim term has a construction different from its broadest reasonable

interpretation, the appropriate course is for the Patent Owner to seek to amend the

claim to expressly correspond to its contentions in this proceeding. See 77 Fed.

Reg. 48764 (Aug. 14, 2012).

A. “graphics pipeline”

The claims recite the term “graphics pipeline.” In the context of the ’945

patent, a person of ordinary skill in the art would have understood this term to

mean “hardware including one or more circuits that process graphics data in a

pipelined manner.” (Yalamanchili ¶ 43 (EX1005)). The ’945 patent’s

specification discloses that the claimed graphics pipeline includes one or more


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circuits. ( Id. ¶ 43 (EX1005)). Further, the preambles of independent claims 1 and

21 describe a “graphics processing circuit.” (’945 patent at 9:65, 12:22-36

(EX1001)); (Yalamanchili ¶ 43 (EX1005)).

VII. SPECIFIC GROUNDS FOR PETITION

Pursuant to Rule 42.104(b)(4)–(5), the following sections (as confirmed in

the Yalamanchili Declaration ¶¶ 44–167 (EX1005)) detail the grounds of

unpatentability, the limitations of the challenged claims of the ’945 Patent, and

how these claims were therefore obvious in view of the prior art.

A.

Ground I: Claims 1-3, 9, 10, and 21 are rendered obvious by

Seiler in view of Perego

Seiler is not of record in the ’945 patent. Perego was applied by the

Examiner during prosecution of the ’945 patent, but is hereby being applied in a

new light.

1.

Overview of Seiler

Seiler claims priority to U.S. Application No. 09/679,315, which was filed

on October 4, 2000. Seiler is directed to an integrated circuit for rendering graphic

data with multiple parallel graphics pipelines. (Seiler at ¶¶ 2, 14 (EX1002));

(Yalamanchili ¶ 42 (EX1005)). As shown below in annotated Figure 1, the

integrated circuit includes a rendering subsystem 200 having rendering pipelines

240, a memory interface 210, and rendering memory 160. (Seiler at ¶ 14


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(EX1002)). Seiler discloses that “[a]s an advantage, the rendering subsystem is

fabricated as a single [application specific integrated circuit] ASIC.” (Seiler at ¶

14 (EX1002)); (Yalamanchili ¶ 42 (EX1005)). One of ordinary skill in the art

would have understood that an “integrated circuit” is a single chip configuration.

(Yalamanchili ¶ 42 (EX1005)).

Seiler discloses that the memory interface 210 “implements all accesses to

the rendering memory 160, arbitrates the requests of the bus logic 220 and the

controller 400, and distributes array data across the modules and the rendering

memory 160 for high bandwidth access and operation.” (Seiler at ¶ 16 (EX1002)).

Seiler further discloses that “[t]he memory interface 210 controls eight double data


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rate (DDR) synchronous DRAM channels that comprise an off-chip rendering

memory 160.” (Seiler at ¶ 16 (emphasis added) (EX1002)). Thus, the memory

interface is a memory controller. (Yalamanchili ¶ 46 (EX1005)).

The memory controller 210 controls lines of communication between the

graphics pipelines 240 and the memory 160. (Seiler at ¶ 16 (EX1002) (“The

memory interface 210 controls eight double data rate (DDR) synchronous DRAM

channels that comprise an off-chip rendering memory 160.”)); (Yalamanchili ¶ 47

(EX1005)). One of ordinary skill in the art would understand that the multiple

channels are used to increase the bandwidth between the memory 160 and the

memory controller 210. ( Id. ¶ 47 (EX1005)).

The rendering memory 160 is disclosed as being “off-chip” and providing “a

unified storage for all data 211 needed for rendering volumes, i.e., voxels, pixels,

depth values, look-up tables, and command queues.” (Seiler at ¶ 16 (EX1002)).

Thus, one of ordinary skill in the art would have understood that the rendering

memory 160 is shared by all of the pipelines 240. (Yalamanchili ¶ 48 (EX1005)).

One of ordinary skill in the art would have understood that a “rendering” pipeline

would have also been called a graphics pipeline. ( Id.

¶ 48 (EX1005)).

Figure 2 of Seiler is reproduced below, with annotations, to show the

graphics pipelines in more detail. The pipelines (A, B, C, and D) operate

independent of each other and form the core of the rendering engine. (Seiler at ¶


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15 (EX1002)). The term “rendering engine” covers embodiments including

multiple graphics pipelines, as shown in Seiler, and covers embodiments including

a single graphics pipeline. (Yalamanchili ¶ 49 (EX1005)). A pipeline controller

400 receives image data from memory 160. ( Id. ¶ 49 (EX1005)). The controller

400 also sends control information to the individual graphics pipelines and receives

output data and status about the rendering operations. (Seiler at ¶ 19 (EX1002)).

Similar to the ’945 patent, the memory controller 210 is position between the

memory 160 and the pipelines. (Yalamanchili ¶ 50 (EX1005)). The pipeline

controller 400 determines what data to fetch from the memory 160 and dispatches

that data to the four pipelines. (Seiler at ¶ 19 (EX1002)). The rendering memory

160 is shared by the pipelines and is called “a unified storage for all data 211


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needed for rendering….” (Seiler at ¶ 16 (EX1002)); (Yalamanchili ¶ 50

(EX1005)). In use, the memory controller 210 passes information back and forth

between the shared memory 160 and the pipelines. (Seiler at ¶ 33, 35 (EX1002));


Figure 3 of Seiler is reproduced below with annotations to show how data

and rendering operations are distributed among the four pipelines. (Seiler at ¶ 25

(EX1002)). Each pipeline includes multiple stages 301-304 for rendering graphics

using the data. (Seiler at ¶ 25 (EX1002)); (Yalamanchili ¶ 51 (EX1005)). The

graphics are rendered using volumetric information called “voxels.”



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(Seiler at Figure 3 (EX1002)). One of ordinary skill in the art would understand

that a voxel represents a sample, or data point, on a three-dimensional grid.

(Yalamanchili ¶ 52 (EX1005)). It is the three-dimensional analogue of a pixel and

may be referred to as a volumetric pixel. ( Id. ¶ 52 (EX1005)). A voxel may

include a numerical quantity representing, for example, a color. ( Id. ¶ 52

(EX1005)). Voxels are used to compute pixel values for creating a displayed two-

dimensional image. ( Id. ¶ 52 (EX1005)). Seiler provides the following definition

for the term “voxel.”

“A voxel represents one or more values related to a

particular location in the object or model. For a given

prior art volume, the values contained in a voxel can be

one or more of a number of different parameters, such as,

density, tissue type, elasticity, or velocity. During

rendering, the voxel values are converted to color and

opacity (RGBa) values in a process called classification.

These RGBa values can be blended and then projected

onto a two-dimensional image plane for viewing.”

(Seiler at ¶ 5 (EX1002)).

The following steps in Seiler are used to convert the voxel information into

pixel data. The controller 400 receives the voxel data from the rendering memory


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160. (Seiler at ¶ 25 (EX1002)); (Yalamanchili ¶ 53 (EX1005)). The voxels are

read from the rendering memory 160 as “miniblocks,” which are cubic arrays of

2x2x2 voxels. (Seiler at ¶ 26 (EX1002)). Each miniblock is then decomposed into

four 1x2x2 arrays called “pairs” of voxels that are respectively feed to the pipelines

A-D. ( Id. at ¶ 27 (EX1002)).

Figure 3 of Seiler , reproduced above, shows a “miniblock” of voxels 310.

Figure 3 also shows the miniblock 310 being decomposed into the four pairs of

voxels 320 that are feed to the pipelines. ( Id. at ¶ 27, Figure 3 (EX1002)). For

example, the pair of voxels 320 shown as “A” and is feed to the first pipeline.

(Yalamanchili ¶ 54 (EX1005)). The next pair of voxels 320, shown as “B,” is feed

to the second pipeline, etc. (Yalamanchili ¶ 54 (EX1005)).

The pipelines include the following four stages: gradient estimation stage

301, classifier-interpolator stage 302, illuminator stage 303, and compositor stage

304. (Seiler at ¶¶ 28-33, Figure 3 (EX1002)). First, each of the voxel pairs 320 is

passed through the gradient estimation stage 301 to obtain gradient values. ( Id. at

¶ 28 (EX1002)). From the gradient estimation stage 301, the voxels and gradients

are passed to the classifier-interpolator stage 302 where they are converted to

RGBα values. (Seiler at ¶ 29 (EX1002)); (Yalamanchili ¶ 55 (EX1005)).

The classifier-interpolator stage 302 outputs an array of RGBα values and

gradients to form a “stamp.” (Seiler at ¶ 30 (EX1002)); (Yalamanchili ¶ 56


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(EX1005)). The stamp of RGBα values and gradients is next passed to the

illuminator stage 303 to apply lighting attributes. (Seiler at ¶ 32 (EX1002)). The

output of the illuminator stage 303 is an illuminated RGBα value representing the

color contribution of its sample point. (Seiler at 33 X (EX1002)); (Yalamanchili ¶

56 (EX1005)).

The RGBα values from the four pipelines are then independently passed to

the compositor stage 304. (Seiler at ¶ 33 (EX1002)). In the compositor stage 304,

a compositor accumulates the RGBα values into an on-chip buffer. ( Id. at ¶ 33

(EX1002)). When the pipelines have finished rendering an entire a section of the

image, the RGBα values are stored in the rendering memory 160 as pixel values

for display. (Seiler at ¶ 33 (EX1002)); (Yalamanchili ¶ 57 (EX1005)). Selier

defines the term “section” as “a rectangular region on the image plane that includes

up to, e.g., 24x24 pixels. (Seiler at ¶ 44 (EX1002)); (Yalamanchili ¶ 57

(EX1005)).

Similar to the ’945 patent, Selier therefore discloses to use multiple graphics

pipelines to distribute the workload of processing image data, where each pipeline

contributes to providing image data on a section-by-section basis. (Yalamanchili ¶

58 (EX1005)). For example, the pixel information generated from a first pipeline

is placed adjacent to pixel information generated from a second pipeline. (Seiler at

¶ 27, 33 (EX1002)); (Yalamanchili ¶ 58 (EX1005)). The four pipelines


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cumulatively provide this information until a section is complete. (Seiler at ¶ 122,

123, 125 (EX1002)); (Yalamanchili ¶ 58 (EX1005)). As shown below in Figure

14, after a first section is complete, the process moves to providing data for a

second section until all 16 sections are processed. (Seiler at Figure 14 (EX1002));


Figure 1 of Seiler and Figure 2 of the ’945 patent are reproduced below to

shown how they include the same structural features. (Yalamanchili ¶ 59

(EX1005)). Both Seiler and the ’945 patent disclose (1) graphics processing

circuitry on a chip (2) graphics pipelines, (3) a memory controller , and (4) graphics

memory. ( Id. ¶ 59 (EX1005)).


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2.

Overview of Perego

Similar to the purported inventive aspect of the ’945 patent, Perego is

directed to using multiple graphics pipelines to process data in a corresponding set

of tiles that have a repeating pattern. (Yalamanchili ¶ 60 (EX1005)). Perego

discloses graphics pipelines in the form of rendering engines 312. ( Perego at 3:67-

4:1, 4:28-30 (EX1003)); (Yalamanchili ¶ 60 (EX1005)). Each rendering engine

312 may also be referred to as a “compute engine” or a “computing engine” and

can perform various data processing functions. ( Perego at 4:7-8, 4:29-30

(EX1003)). One of ordinary skill in the art would understand that the rendering

engines of Perego may also be called “graphics pipelines.” (Yalamanchili ¶ 60


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(EX1005)). This understanding is consistent with Applicants’ comments during

prosecution. (File History, Appeal Brief at 17 (EX1013); (Yalamanchili ¶ 60

(EX1005)).

Figure 3 of Perego is reproduced below to shown the multiple rendering

engines 312. ( Perego at 4:26-9 (EX1003)). The rendering engines 312

communicate with a memory controller 310. In use, the memory controller 310

distributes graphical processing tasks to the different rendering engines. ( Perego

at 4:36-39 (EX1003)).


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Figure 5 of Perego shows a graphical rendering surface divided into sixteen

different tiles. ( Id. at 3:37-38, 5:29-31 (EX1003)). The graphical rendering surface

“may be stored in, for example, an image buffer or displayed on a display device.”

( Id. at 5:32-33 (EX1003)). The memory controller 310 of Perego divides the

processing tasks into different portions that correspond to tiles. ( Id. at 5:35-37

(EX1003)). For example, Perego discloses the following:

“For example, four of the sixteen tiles of the

surface are assigned to a first rendering engine (labeled

"RE0") on a first memory module. Another four tiles of

the surface are assigned to a different rendering engine

(labeled "RE1), and so on. This arrangement allows the

four different rendering engines (RE0, RE1, RE2, and

RE3) to process different regions of the surface

simultaneously.”

( Id. at 5:38-44 (EX1003)). Figure 5 of Perego is reproduced below to visually

show tiles that are processed by two different pipelines RE0 and RE1.

(Yalamanchili ¶ 63 (EX1005)). Figure 4 of the ’945 patent is also reproduced

below show tiles that are processed by two different pipelines A0 and B0. ( Id. ¶ 63

(EX1005)). The top rows of these figures are annotated and have color added to

emphasize the resemblance. ( Id. ¶ 63 (EX1005)). The direct relationship between

these two figures is clear – both Perego and the ’945 patent disclose to assign

graphics pipelines to process data for different tiles. ( Id. ¶ 63 (EX1005)).


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The number of tiles shown in Perego is exemplary and different divisions of

the rendering surface may be used. ( Perego at 5:38-67 (EX1003)). Thus, going to

the heart of the ’945 patent, Perego discloses that the “rendering surface is

generally divided into multiple rectangular regions of pixels (or picture elements),

referred to as ‘tiles’ or ‘chunks.’” (Yalamanchili ¶ 64 (EX1005)). Since the tiles

generally do not overlap spatially, the rendering of the tiles can be partitioned

among multiple rendering engines.” ( Perego at 5:23-27 (EX1003)).

3.

Motivation to combine Seiler and Perego

Seiler and Perego are each directed to graphics rendering systems.

(Yalamanchili ¶ 65 (EX1005)). Seiler discloses to use multiple graphics pipelines


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that operate in parallel. ( Id. ¶ 65 (EX1005)). Similarly, Perego discloses to use

multiple graphics pipelines, referred to as rendering engines that operate in

parallel. ( Id. ¶ 65 (EX1005)). They are both directed to using different pipelines

for different portions of a displayed image. ( Id. ¶ 65 (EX1005)). The end result in

the same, i.e., rendered pixel data that is used to display an image. ( Id. ¶ 65

(EX1005)).

Perego advantageously discloses to increase efficiency by using the

individual pipelines to process data for a corresponding set of tiles. ( Perego at

5:41-46 (EX1003)); (Yalamanchili ¶ 66 (EX1005)). The tiles are respectively

formed from rectangular regions of pixels. ( Perego at 5:23-25 (EX1003));


Seiler discloses a shared rendering memory 160 that stores “pixel values”

used to render an image. (Seiler at ¶ 33 (EX1002)); (Yalamanchili ¶ 67

(EX1005)). Perego also discloses to store a graphical rendering surface including

pixel data. ( Perego at 5:32-33 (EX1003) (“The graphical rendering surface may be

stored in, for example, an image buffer or displayed on a display device”));


Moreover, Seiler explicitly discloses that it is advantageous to put multiple

graphics pipelines and a memory controller onto a single chip. (Yalamanchili ¶ 68

(EX1005)). In particular, Seiler discloses that “[a]s an advantage, the rendering


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subsystem is fabricated as a single ASIC.” (Seiler at ¶ 0014 (EX1002)). As one of

ordinary skill in the art would understand, an application specific integrated circuit

(ASIC) is a single chip design that affords many advantages. (Yalamanchili ¶ 68

(EX1005)). For example, an ASIC (1) allows for miniaturized size, therefore

requiring less space in the device using the chip, (2) can operate with increased

speed, and (3) needs less power to operate. ( Id. ¶ 68 (EX1005)).

Given the similarities in structure, objectives, and operation between Seiler

and Perego, one would have been motivated to implement the multi-pipeline tiling

aspects of Perego into the system of Seiler . ( Id. ¶ 69 (EX1005)). Seiler discloses

that it is advantageous to use a single chip, and Perego discloses advantages of

using individual graphics pipelines to process data for a corresponding tile of

pixels. ( Id. ¶ 69 (EX1005)). Doing so allows the different pipelines of Perego to

process data for the different tiled regions simultaneously. ( Perego at 3:33-36, 5:

Figure 4 (EX1003)); (Yalamanchili ¶ 69 (EX1005)).

Modifying Selier’s graphics processing chip to implement the tiling aspects

of Perego is well within the abilities of one of ordinary skill in the art and would

be accomplished with a reasonable chance of success. (Yalamanchili ¶ 70

(EX1005)).

4. Claim 1 is obvious in view of Seiler and Perego

a) “A graphics processing circuit”


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Seiler discloses a graphics processing circuit. (Seiler at ¶ 2, 14 Figure 2

(EX1002) (“[t]he present invention is related to the field of computer graphics, and

in particular to rendering graphic data with a parallel pipelined rendering

engine.”)). One of ordinary skill in the art would have understood that Seiler ’s

graphics processing ASIC is a circuit. Pergo also discloses a graphics processing

circuit. ( Perego at 3:61-63 (EX1003)); (Yalamanchili ¶ 71 (EX1005))..

b) “at least two graphics pipelines on a same chip

operative to process data in a corresponding set of tiles

of a repeating tile pattern corresponding to screen

locations”

The combination of Seiler and Perego teaches this limitation. (Yalamanchili

¶ 73 (EX1005)). Seiler discloses the claimed “at least two graphics pipelines on a

same chip.” ( Id. ¶ 73 (EX1005)). For example, Seiler discloses four graphics

pipelines A-D. (Seiler at ¶¶ 15, 25, Figure 2 (EX1002) (“As also shown in Figure

2, the principal modules of the rendering subsystem 200 are a memory interface

210, bus logic 220, a controller 400, and four parallel hardware pipelines 300.)).

The pipelines A-D are on the same chip because they are part of the same ASIC.

(Seiler at ¶ 14 (EX1002) (“[a]s an advantage, the rendering subsystem is fabricated

as a single ASIC.)); (Yalamanchili ¶ 73 (EX1005)). One of ordinary skill in the art

would have known that an ASIC is an “integrated circuit,” which is a single chip.

(Yalamanchili ¶ 73 (EX1005)). One of ordinary skill in the art would have


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understood that the pipelines of Seiler include hardware with one or more circuits

that process graphics data in a pipelined manner. ( Id. ¶ 73 (EX1005)). For

example, Seiler discloses that the pipelines are “hardware pipelines” and Figure 3

shows the pipeline process. (Seiler at ¶ 15, Figure 3 (EX1002)); (Yalamanchili ¶

73 (EX1005)).

Seiler discloses that each pipeline is responsible for processing data that will

correspond to different screen locations. (Yalamanchili ¶ 74 (EX1005)). As

shown below in Figure 3 from Seiler , an array of voxel data 310 is divided and

distributed to the pipelines A-D for processing. (Seiler at ¶ 26-27 (EX1002));



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(Seiler at ¶¶ 25-27, 30, 33 Figure 3 (EX1002)). The distributed voxel data is used

to create pixel data that corresponds to screen locations. (Seiler at ¶ 33 (EX1002));


Perego discloses at least two graphics pipelines that are operative to process

data in a corresponding set of tiles of a repeating tile pattern corresponding to

screen locations. ( Perego at 4:7-8, 5:35-47, Figure 3 (EX1003)); (Yalamanchili ¶

75 (EX1005)). As noted above, one of ordinary skill in the art would have

understood that the engines of Perego are graphics pipelines. (Yalamanchili ¶ 75

(EX1005)). One of ordinary skill in the art would have further understood that the


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engines include hardware with one or more circuits that process graphics data in a

pipelined manner. ( Perego at 4:29-30 (EX1003) (“Each rendering engine 312 is

capable of performing various data processing functions.”)); (Yalamanchili ¶ 75

(EX1005)).

Similar to the pipelines in Seiler , the respective pipelines of Perego are

“capable of performing various memory access and/or data processing functions.”

( Perego at 4:10-12 (EX1003)); (Yalamanchili ¶ 76 (EX1005)). Also, similar to

Selier, the pipelines of Perego access memory through a memory controller.

( Perego at 4:36-46 (EX1003)); (Yalamanchili ¶ 76 (EX1005)). Moreover, Perego

discloses to partition processing tasks into multiple portions and distribute the

portions respectively to the pipelines. ( Perego at 5:3-7 (EX1003)); (Yalamanchili

¶ 76 (EX1005)). This is analogous to the partitioning and distributing of

processing tasks to the pipelines of Seiler . (Seiler at ¶ 27 (EX1002));


Figure 5 of Perego is reproduced to show how the different pipelines RE0,

RE1, RE2, and RE3 correspond to the set of repeating tiles. ( Perego at 5:38-45



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Thus, Perego discloses at least two graphics pipelines operative to process

data in a corresponding set of tiles of a repeating tile pattern corresponding to

screen locations. (Yalamanchili ¶ 78 (EX1005)). Perego does not explicitly

disclose that the graphics processors are “on a same chip,” as recited in claim 1.

However, as noted above, Seiler discloses pipelines A-D that are on the same chip.

(Seiler at ¶ 14 (EX1002) (“[a]s an advantage, the rendering subsystem is fabricated

as a single ASIC.)); (Yalamanchili ¶ 78 (EX1005)).


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It would have been obvious to a person of ordinary skill in the art to

implement the multi-pipeline tiling aspects of Perego into the system of Seiler .

(Yalamanchili ¶ 79 (EX1005)). Seiler discloses that it is advantageous to use a

single chip, and Perego discloses advantages of using individual graphics pipelines

to process data for a corresponding tile of pixels. ( Id. ¶ 79 (EX1005)). Doing so

allows the different pipelines of Perego to process data for the different tiled

regions simultaneously. ( Perego at 3:33-36, 4:30-33; 5:42-45 Figure 4 (EX1003));


Modifying Selier’s graphics processing chip to implement the tiling aspects

of Perego is well within the abilities of one of ordinary skill in the art and would

be accomplished with a reasonable chance of success. (Yalamanchili ¶ 80

(EX1005)). Doing so would have only required minor hardware and/or software

modifications known to those of ordinary skill in the art. ( Id. ¶ 80 (EX1005)). The

combination would have been nothing more than combining prior art elements

according to known computer architecture methods to yield predictable and

desirable results. ( Id. ¶ 80 (EX1005)). This modification would permit one to

utilize the known advantages of a single chip and would take advantage of the

disclosed beneficial tile aspects of Perego. ( Id. ¶ 80 (EX1005)). As emphasized

by Applicants many times during prosecution, the claims were believed novel

because the applied prior art did not disclose the claimed structural features,


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including a single chip design having multiple graphics pipelines and a memory

controller. ( Id. ¶ 80 (EX1005)). This feature is clearly disclosed by Seiler , and

disclosed as being advantageous. (Seiler at ¶ 14 (EX1002)); (Yalamanchili ¶ 80

(EX1005)). Thus, due to Seiler ’s teachings and the multiple similarities between

Seiler and Perego, one would have been motivated to modify Seiler so that its

pipelines process data in a corresponding set of tiles of a repeating tile pattern

corresponding to screen locations, as disclosed by Perego. (Yalamanchili ¶ 80

(EX1005)).

While Perego discloses to provide a scalable system, this would not deter

one of ordinary skill in the art from implementing the tiling aspects of Perego in

the chip of Seiler . ( Perego at 3:30-32 (EX1003)); (Yalamanchili ¶ 81 (EX1005)).

Perego is being relied on for its teachings of using graphics pipelines to process

data for a corresponding set of tiles. (Yalamanchili ¶ 81 (EX1005)). The

scalability aspect of Perego does not deter from Perego’s explicit tiling disclosure.

( Id. ¶ 81 (EX1005)). Even Perego acknowledges that integrating a “number of

subsystems…into single device,” is a beneficially known objective. ( Perego at

1:34-36 (EX1003)); (Yalamanchili ¶ 81 (EX1005)).

Thus, the combination of Seiler and Perego teaches the recited “at least two

graphics pipelines on a same chip operative to process data in a corresponding set


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of tiles of a repeating tile pattern corresponding to screen locations,” as required by

element (b) of claim 1. (Yalamanchili ¶ 82 (EX1005)).

c)

“a respective one of the at least two graphics pipelinesoperative to process data in a dedicated tile; and”

Perego discloses “a respective one of the at least two graphics pipelines

operative to process data in a dedicated tile.” (Yalamanchili ¶ 84 (EX1005)).

Perego discloses that its pipelines RE0, RE1, RE2, and RE3 are “assigned” to

different tiles. ( Perego at 5:38-45 (EX1003)); (Yalamanchili ¶ 84 (EX1005)).

This feature is also shown in Figure 5 by the explicit labeling of the tiles with

names of the corresponding processors. ( Perego at 5:38-45, Figure 5 (EX1003));



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Thus, the combination of Seiler and Perego teaches each feature in

limitation (c). (Yalamanchili ¶ 85 (EX1005)).

d) “a memory controller on the chip in communication

with the at least two graphics pipelines, operative to

transfer pixel data between each of a first pipeline and

a second pipeline and a memory shared among the at

least two graphics pipelines”

Seiler discloses a memory controller on the chip in communication with the

at least two graphics pipelines. (Yalamanchili ¶ 87 (EX1005)). Figure 1 of Seiler


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is reproduced below with annotations to show the memory controller on the same

chip as the pipelines. ( Id. ¶ 87 (EX1005)).

Seiler discloses that the memory interface 210 “implements all accesses to

the rendering memory 160, arbitrates the requests of the bus logic 220 and the

controller 400, and distributes array data across the modules and the rendering

memory 160 for high bandwidth access and operation.” (Seiler at ¶ 16 (EX1002)).

Seiler further discloses that “[t]he memory interface 210 controls eight double data

rate (DDR) synchronous DRAM channels that comprise an off-chip rendering

memory 160.” (Seiler at ¶ 16 (emphasis added) (EX1002)). Thus, the memory

interface 210 shown in Figure 1 of Seiler is a memory controller. (Yalamanchili ¶


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88 (EX1005)). The memory controller 210 is on the same chip as the graphics

pipelines 240. (Seiler at ¶ 14, Figure 1 (EX1002)); (Yalamanchili ¶ 88 (EX1005)).

The memory controller of Seiler is operative to transfer pixel data between

each of a first pipeline and a second pipeline and a memory shared among the at

least two graphics pipelines. (Yalamanchili ¶ 89 (EX1005)). Figure 1 of Seiler

shows shared rendering memory 160. ( Id. ¶ 89 (EX1005)). Image data provided

by the group of pipelines in Seiler is stored “in the rendering memory 160 as, for

example, pixel values.” (Seiler at ¶ 33 (EX1002)). The rendering memory 160 is

disclosed as being “off-chip” and providing “a unified storage for all data 211

needed for rendering volumes, i.e., voxels, pixels, depth values, look-up tables, and

command queues.” (Seiler at ¶ 16 (emphasis added) (EX1002)); (Yalamanchili ¶

89 (EX1005)). Thus, one of ordinary skill in the art would understand that the

rendering memory is shared by all of the pipelines in Seiler . (Yalamanchili ¶ 89

(EX1005)).

It is noted that the term “shared,” with respect to the memory limitation is

not found in the detailed description of the ’945 patent. (Yalamanchili ¶ 90

(EX1005)). In fact, the only place where the term “shared” appears is in claims 1,

18, and 21. This term was added by amendment. (File History, Amendment at 2,

7 (1/25/10) (EX1015)). Thus, it is questionable whether proper written description

support exists for the shared memory limitation. Nevertheless, to the extent that


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the ’945 patent does provide proper support for this term, Seiler provides even

more support that it’s rendering memory 160 is shared. (Yalamanchili ¶ 90

(EX1005)). Seiler therefore discloses that its memory is operative to transfer pixel

data between each of a first pipeline and a second pipeline and a memory shared

among the at least two graphics pipelines. ( Id. ¶ 90 (EX1005)). Accordingly, the

combination of Seiler and Perego teaches limitation (d) of claim 1. ( Id. ¶ 90

(EX1005)).

e)

“wherein the repeating tile pattern includes a

horizontally and vertically repeating pattern of square

regions.”

Perego discloses that the tile pattern includes a horizontally and vertically

repeating pattern of square regions, as shown in Figure 5. ( Perego at 5:54-58

(EX1003) (“As shown in FIG. 5, the rendering surface is divided into two or more

horizontal pixel bands (also referred to as pixel rows) and divided into two or more

vertical pixel bands (also referred to as pixel columns)”)); (Yalamanchili ¶ 92

(EX1005)). Perego further discloses that “[t]he rendering surface is generally

divided into multiple rectangular regions of pixels (or picture elements), referred to

as “tiles” or “chunks.” ( Perego at 5:22-25 (EX1003)). One of ordinary skill in the

art would have understood that a rectangle is a quadrilateral with four right angles.

(Yalamanchili ¶ 92 (EX1005)). A rectangle with four sides of equal length is a

square. ( Id. ¶ 92 (EX1005)). Figure 5 of Perego represents one exemplary title


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pattern embodiment. ( Id. ¶ 92 (EX1005)). One of ordinary skill in the art would

have understood that the tile pattern in Figure 5, reproduced below, shows a

repeating pattern of square regions. Perego also discloses that the rendering

surface may be divided into quadrants. ( Perego at 5:63-67 (EX1003);

(Yalamanchili ¶ 92 (EX1005)). Thus, the combination of Seiler and Perego

teaches each limitation of claim 1. (Yalamanchili ¶ 92 (EX1005)).


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5.

Claim 2 is obvious in view of Seiler and Perego

a) “The graphics processing circuit of claim 1, wherein

the square regions comprise a two dimensional

partitioning of memory.”

Perego discloses that the square regions comprise a two dimensional

partitioning of memory. (Yalamanchili ¶ 94 (EX1005)). For example, Perego

discloses that Figure 5 “illustrates a graphical rendering surface divided into

sixteen different sections or “tiles” (four rows and four columns)” and that

“graphical rendering surface may be stored in, for example, an image buffer or

displayed on a display device.” ( Perego at 5:28-33 (emphasis added) (EX1003));

(Yalamanchili ¶ 94 (EX1005)). Figure 5 therefore represents a “graphical

rendering surface.” (Yalamanchili ¶ 94 (EX1005)). Figure 5 is shown as being

divided or partitioned in the horizontal and vertical directions. ( Id. ¶ 94

(EX1005)). Thus, since the graphics rendering surface of Figure 5 is stored in an

“image buffer” and is partitioned in the horizontal and vertical directions, Perego

discloses or at least suggests that the square regions comprise a two dimensional

partitioning of memory, as required by claim 2. ( Id. ¶ 94 (EX1005)). It would

have been obvious to one of ordinary skill in the art to provide the same

partitioning for the graphical rendering surface when modifying Seiler to use the

tiling features of Perego. ( Id. ¶ 94 (EX1005)). Thus, the combination of Seiler

and Perego teaches each limitation of claim 2. (Yalamanchili ¶ 94 (EX1005)).


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6.

Claim 3 obvious in view of Seiler and Perego


the memory is a frame buffer.”

As noted above with respect to claim 2, Perego discloses to save the

graphical rendering surface in an “image buffer.” ( Perego at 5:32-33 (EX1003));

(Yalamanchili ¶ 96 (EX1005)). One of ordinary skill in the art would understand

that an image buffer is a frame buffer. (Yalamanchili ¶ 96 (EX1005)). Further,

one ordinary skill in the art would understand that the rendering memory 160 of

Seiler functions as an image buffer. (Seiler at ¶ 33 (EX1002)); (Yalamanchili ¶ 96

(EX1005)). Thus, the combination of Seiler and Perego teaches each limitation of

claim 3. (Yalamanchili ¶ 96 (EX1005)).

7.



each tile of the set of tiles further comprises a 16×16 pixel array.”






(EX1005)).


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Perego further discloses that “[t]he specific example of FIG. 5 shows a

rendering surface divided into four horizontal pixel bands and four vertical pixel

bands. However, in alternate embodiments the rendering surface may be divided

into any number of horizontal pixel bands and any number of vertical pixel band s.”

( Perego at 5:58-63 (emphasis added (EX1003)). Thus, when starting with a finite

number of pixels, and dividing the horizontal and vertical bands as taught by

Perego, one would ultimately end up with the claimed 16x16 pixel array.

(Yalamanchili ¶ 99 (EX1005)). Further, it would have been merely an obvious

design choice to select the number of vertical and horizontal bands to obtain the

claimed 16x16 pixel array. ( Id. ¶ 99 (EX1005)). Thus, the combination of Seiler

and Perego teaches each limitation of claim 9. ( Id. ¶ 99 (EX1005)).

8. Claim 10 is obvious in view of Seiler and Perego

a) “The graphics processing circuit of claim 1, wherein a

second of the at least two graphics pipelines processes

the data only in a second set of tiles in the repeating tile

pattern.”

Perego discloses that a second of the at least two graphics pipelines

processes data only in a second set of tiles in the repeating tile pattern.

(Yalamanchili ¶ 101 (EX1005)). For example, as shown below in reproduced

Figure 5 of Perego, for example, RE1 processes data only in a second set of tiles to

which it is assigned. ( Perego at 5:38-45, Figure 5 (EX1003)); (Yalamanchili ¶ 101


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(EX1005)). Thus, the combination of Seiler and Perego teaches each limitation of

claim 10. (Yalamanchili ¶ 101 (EX1005)).

9.


a) “A graphics processing circuit, comprising:

As noted above in Section VII(A)(4), the combination of Seiler and Perego

teaches “[a] graphics processing circuit.” (Yalamanchili ¶ 102 (EX1005)).

b) at least two graphics pipelines on a chip operative to

process data in a corresponding set of tiles of a


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repeating tile pattern corresponding to screen

locations,”


teaches “at least two graphics pipelines on a chip operative to process data in a

corresponding set of tiles of a repeating tile pattern corresponding to screen

locations.” (Yalamanchili ¶ 104 (EX1005)).

c) “wherein the repeating tile pattern includes a

horizontally and vertically repeating pattern of

regions;”


teaches “wherein the repeating tile pattern includes a horizontally and vertically

repeating pattern of regions.” (Yalamanchili ¶ 106 (EX1005)).

d) “wherein the horizontally and vertically repeating

pattern of regions include N×M number of pixels; and”

In addition to the support noted in Section VII(A)(4), the combination of

Seiler and Perego teaches “wherein the horizontally and vertically repeating

pattern of regions include N×M number of pixels.” (Yalamanchili ¶ 108

(EX1005)). To the extent that Patent Owner argues that the limitation “N×M

number of pixels” requires a non-square region, this limitation is also taught by

Perego. ( Id. ¶ 108 (EX1005)).




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(EX1005)). Perego further discloses that “[t]he rendering surface is generally

divided into multiple rectangular regions of pixels (or picture elements), referred to

as “tiles” or “chunks.’” ( Perego at 5:22-25 (EX1003)). One of ordinary skill in

the art would have understood that a rectangle is a quadrilateral with four right

angles. (Yalamanchili ¶ 109 (EX1005)). A rectangle with four sides of equal

length is a square. ( Id. ¶ 109 (EX1005)). Perego’s disclosure of the tile pattern

including “rectangular regions” would have taught one of ordinary skill in the art

that the region could also have a non-square shape, e.g., a rectangle with two

opposing sides that are longer than the other two opposing sides. ( Id. ¶ 109

(EX1005)). Further, one of ordinary skill in the art would understand that pixels

are distributed in a uniform manner, such that if a tile has a rectangle shape, with

two opposing sides that are longer than the other two opposing sides, then those

regions would respectively have N×M number of pixels, where N and M are

different numbers. ( Id.

¶ 109 (EX1005)). Thus, the combination ofSeiler

and

Perego teaches limitation (d) of claim 21. ( Id. ¶ 109 (EX1005)).


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e) “a memory controller on the chip, coupled to the at

least two graphics pipelines on the chip and operative to

transfer pixel data between each of the two graphics

pipelines and a memory shared among the at least two

graphics pipelines.”

143. As noted above in Section VII(A)(4), the combination of Seiler and

Perego teaches “a memory controller on the chip, coupled to the at least two

graphics pipelines on the chip and operative to transfer pixel data between each of

the two graphics pipelines and a memory shared among the at least two graphics

pipelines.” (Yalamanchili ¶ 111 (EX1005)). Thus, the combination of Seiler and

Perego teaches each limitation of claim 21. (Yalamanchili ¶ 111 (EX1005)).

B.

Ground II: Claims 1, 9, 10, and 21 are rendered obvious by

Narayanaswami in view of Seiler

Neither Seiler nor Narayanaswami are of record in the ’945 patent file

history.

1. Overview of Seiler

The overview of Seiler is provided above in section VII(A)(1).

2. Overview of Narayanaswami

Narayanaswami is directed to managing graphical workloads such as

rendering across multiple processors by pixel locations corresponding to display

regions. ( Narayanaswami at 2:7-10 (EX1004)); (Yalamanchili ¶ 114 (EX1005)).

The processors render pixels by pixel location or display region or window based


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on various allocation techniques. ( Narayanaswami at 2:10-13, Figures 3A-3C


Figure 1 of Narayanaswami is reproduced below to show main processor(s)

110 coupled to a memory 120 and a hard disk 125 in computer box 105 with input

devices 130 and output devices 140 attached. ( Id. at 2:18-22 (EX1004)). The

main processors 110 are coupled to a graphics adapter 200. ( Id. at 2:39-41, Figure

1 (EX1004)). The graphics adapters 200 receive instructions regarding graphics

from main processors 110 on bus 160. ( Id. at 2:41-43 (EX1004)). The graphics

adapter 200 then executes those instructions with the graphics adapter processors

220 coupled to a graphics adapter memory 230 and updates frame buffer(s) 240.

( Id. at 2:43-47 (EX1004)).


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( Id. at Figure 1 (EX1004)).

The graphics processors 220 may be “a pipeline of processors in series, a set

of parallel processors, or some combination thereof, where each processor may

handle a portion of a task to be completed.” ( Id. at 2:47-51 (EX1004)). Graphic

processors 220 include specialized hardware for rendering specific types of image

information. ( Narayanaswami at 2:51-53 (EX1004)); (Yalamanchili ¶ 116

(EX1005)). Graphics memory 230 is used by the graphics processors 220 to store

information being processed, such as “received object data, intermediate calculated

data (such as a stencil buffer or partially rendered object data), and completed data

being loaded into the frame buffer 240.” ( Narayanaswami at 2:53-57 (EX1004)).

The frame buffer(s) 240 include data for every pixel to be displayed on the

graphics output device. ( Id. at 2:57-59 (EX1004)). A RAMDAC (random access

memory digital-to-analog converter) 250 converts digital data stored in the frame

buffer(s) 240 into RGB signals to be provided to a graphics display 150 thereby

rendering the desired graphics output from the main processor. ( Id. at 2:59-63

(EX1004)).

Narayanaswami discloses a tile based screen partitioning technique, as well

as other techniques for partitioning a display screen into regions or blocks of

pixels, which allocates graphics processing associated with those regions or blocks

to different graphics processors. ( Narayanaswami at 2:10-18, 4:55-5:43, Figures


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3A-3C (EX1004)); (Yalamanchili ¶ 117 (EX1005)). Narayanaswami discloses

that these techniques allow “for greater flexibility in managing the graphical

workload across multiple processors.” ( Narayanaswami at 2:16-18 (EX1004));

(Yalamanchili ¶ 117 (EX1005)). Figures 3A-3C show different ways for

distributing a graphical workload to different processors by pixel location.

( Narayanaswami at 4:54-55, Figures 3A-3C (EX1004)); (Yalamanchili ¶ 117

(EX1005)). Each of Figures 3A-3C shows a window or display where certain

regions are allocated to various processors for rendering pixels in those regions.

( Narayanaswami at 4:56-59, Figures 3A-3C (EX1004)); (Yalamanchili ¶ 117

(EX1005)).

Figure 3A, reproduced below, shows a tile-based screen partitioning that

uses a round robin approach for distributing the graphical workload.

( Narayanaswami at 4:59-62 (EX1004)); (Yalamanchili ¶ 118 (EX1005)). Figure

3A shows sixteen regions and three processors P0, P1 and P2 that are respectively

assigned to those regions. ( Narayanaswami at 4:62-64 (EX1004)); (Yalamanchili

¶ 118 (EX1005)).


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Narayanaswami discloses all features in independent claims 1 and 21 except

for (1) explicitly disclosing to place the pipelines and memory controller on the

same chip and (2) explicitly labeling an element as a memory controller.


3.

Motivation to combine Narayanaswami and Seiler

Narayanaswami and Seiler are each directed to graphics rendering systems.

Seiler discloses to use multiple graphics pipelines that operate in parallel.

(Yalamanchili ¶ 120 (EX1005)). Similarly, Narayanaswami discloses to use

multiple graphics pipelines, referred to as processors that operate in parallel.

( Narayanaswami at 2:47-53 (EX1004)); (Yalamanchili ¶ 120 (EX1005)). They are

both directed to using different pipelines to perform similar operations, but for

different portions of a displayed image. ( Narayanaswami at 4:54-5:18, Figure 3A-


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chip structure Seiler . (Yalamanchili ¶ 123 (EX1005)). One of ordinary skill in the

art would understand that Narayanaswami’s graphics adapter memory 230 and

frame buffer 240 are memories that are respectively shared by the graphics

processors 220 and are used for storing pixel data. ( Narayanaswami at 2:57-59

(EX1004)); (Yalamanchili ¶ 123 (EX1005)). Seiler similarly teaches shared

memory for storing pixel data. (Seiler at ¶ 33 (EX1002)); (Yalamanchili ¶ 123

(EX1005)). Implementing the functionality of Narayanaswami on a single chip

configuration, as taught by Selier, is well within the abilities of one of ordinary

skill in the art and would be a

Unified Patents Inc. v. Advanced Silicon Technologies, LLC, IPR2016-01060, Paper 3 (May 19, 2016)

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Transcript of Unified Patents Inc. v. Advanced Silicon Technologies, LLC, IPR2016-01060, Paper 3 (May 19, 2016)