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Ultralow-Power Reconfigurable Computing with ComplementaryNano-Electromechanical Carbon Nanotube Switches

Swarup Bhunia, Massood Tabib-Azar, and Daniel SaabElectrical Engineering and Computer Science, Case Western Reserve University, USA

Email: [skb2l, tabib-azar, dgs3]@cwru.edu

AbstractIn recent years, several alternative devices have beenproposed to deal with inherent limitation of conventionalCMOS devices in terms of scalability at nanometer scalegeometry. The fabrication and integration cost of thesedevices, however, have been prohibitive and/or the devices donot allow smooth transition from the conventional designparadigm. To address some of these limitations, we havedeveloped a new family of devices called "ComplementaryNano Electro-Mechanical Switches" (CNEMS) using carbonnanotubes as active switching/latching elements. The basicstructure of these devices consists of three co-planar carbonnanotubes arranged so that the central nanotube can touch thetwo side carbon nanotubes upon application of a voltage pulsebetween them. Owing to the unique properties of carbonnanotubes, these devices have very low leakage current, lowoperation voltages, and have built-in energy storage to reducecomputation power, resulting in very low overall powerdissipation. CNEMS have stable on-off state and latchingmechanism for non-volatile memory-mode operation. Besides,the devices can be readily integrated in the same substrate asCMOS transistors with high integration densities - thus,allowing easy manufacturability and hybridization withconventional CMOS devices. In this paper, we present theproperties of these devices and based on our analysis, wepropose a reconfigurable computation framework using thesedevices. For the first time, we demonstrate that these devicesare promising in dynamically reconfigurable instant-on systemdevelopment with about 25X lower power dissipation.

1. INTRODUCTIONWhile CMOS technology has served the semiconductor

industry marvelously for the past four decades (by allowingnearly exponential increase in computational power and deviceintegration density), it is predicted to meet the end of roadmapin near future due to the intrinsic physical limitations of thedevice in terms of scalability. At nanometer scale, CMOSdevices suffer from increasing short channel effect [12] thatresults in high leakage current. High dynamic power andpower density have also emerged as major barriers togigascale integration. On the other hand, drain to sourcevoltage (VDS) reduces with scaling, while the series resistanceincreases, giving rise to reduced saturation current and ION/1oFFratio. Variations in manufacturing process parameters, such aslength (L), width (W), threshold voltage (VTH) have increasedalarmingly with continued miniaturization of device geometryand supply/threshold voltage scaling. Hence, manufacturingyield and robustness of operation under severe processvariations have manifested as major design concerns.

To address some of these issues, there has been multitudeof research efforts to develop alternative devices with

promising characteristics in terms of performance and/orintegration density. Most of these emerging devices eitherdemand prohibitive manufacturing costs or introduce acompletely new paradigm of computing. However, to achievea smooth transition from conventional MOSFET devices to aviable alternative at the end its roadmap, it is beneficial tohave a potent technology, which allows system manufacturingby extending the existing CMOS fabrication and enablesutilization of the rich repository of existing CAD tools.

In this paper, we present a new device calledComplementary Nano Electro-Mechanical Switch (CNEMS)that uses carbon nanotube (CNT) [1-5, 10-11] as activeelement. Acting as a mechanical relay, the switch can betoggled between two complementary configurations byapplication of an electric field between two of its terminals.Once configured in a certain way, the switch remains in thesame state until an opposite electric field is applied toreconfigure the switch. Due to this latching mechanism, eachswitch works as a non-volatile memory element. In a CNEMS,electron transport between two connected terminals is ballistic.Due to the electro-mechanical nature of the switch, there isvirtually no leakage current between two terminals when theyare not connected. Another important feature of the device isthat, once it is programmed, certain amount of elastic energyremains internally stored in the carbon nanotubes, so that allsubsequent reconfigurations of the switch require less electricfield and thus less energy for transition. This feature ofinternal energy storage [6-9] helps to reduce the active powerof the switch considerably.

Due to the unique properties of carbon nanotubes, thesedevices have very stable on-off states and low operationvoltage. Since the CNEMS has low leakage, it has extremelyhigh data retention capability. The device is also completelyimmune to soft error (e.g. memory failures due toalpha/neutron particle hit) [14], unlike CMOS based memory.Therefore, CNEMS is a good candidate for memoryimplementation and can potentially replace conventionalcharge-based CMOS static and dynamic RAM. Unlike theconventional CMOS logic circuits, which evaluates logicfunction based on charge stored in a node [12] (defined by thediffusion and or gate capacitances of the devices), theproposed CNEMS based logic evaluates in two steps: a)configure and then b) propagate logic value. In the "configure"step, the switch is programmed to select one of the two inputsand in the following "propagate" step, the switch propagatesthe right input to the output. We propose a reconfigurablecomputing framework using these devices. Since eachCNEMS switch can be treated as a non-volatile memoryelement, we can use them in realizing lookup table (LUT)based logic circuits [13]. Compared to the conventional FPGAarchitecture, the proposed framework has the following

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advantages. a) The CNEMS switches used to build the lookuptable can be configured as register banks or latches for storingdata. It can be particularly helpful to improve performance ingeneral purpose or digital signal processing, where an array oflookup tables can be used to configure either certain datapathelement (e.g. an image encoder in a streaming application) or

register banks (in a data-intensive application). b) The systemdeveloped with CNEMS, will be instant-on (due to non-

volatile nature of the switches) unlike SRAM-based FPGA[13] and dynamically reconfigurable (due to fast transition ofthe states in the switches). c) The system can achieve ultra lowpower operation and reconfiguration and d) due to less "ON"resistance and non-volatility of these switches, they can beused in developing efficient low-power programmableswitches.

2. DEVICE AND TECHNOLOGYIn this section, we present carbon nanotube [1-5] based

electro-mechanical switches with internal energy storage as

complementary or alternative to the existing CMOS switchesin certain applications. Devices with internal energy storagewere proposed by Feynman [6, 7] and Bennett [8, 9] forreduced power computation and bit processing. The main ideawas that if one uses a spring as the computation device, the"one" state may be achieved by compressing the spring andlatching it so that it does not spring back. Subsequently, intransitioning to the "zero" state, the stored energy in thecompressed spring can be retrieved and re-used to reduce theenergy per bit. With the discovery of carbon nanotubes andtheir applications in electronics [1-5, 10-11], we note thatCNTs with their large Young's modulus (1.3 TPa) [10] andvery small diameters (1-1OOnm), are ideal electronic device-grade "springs" for Feynman-Bennett type computationdevices. Hence we propose to develop a very unique categoryof electronic devices with internal energy storage capacity andother desirable characteristics such as very low leakage andhigh transition speeds. The basic structure of the proposedcomplementary nano electro-mechanical switch (CNEMS)consists of three co-planar carbon nanotubes arranged so thatthe central nanotube can touch the two side carbon nanotubesupon application of a voltage pulse between them. When thecentral CNT touches one of the side CNTs, the van der Waalsforce causes them to "stick" to each other resulting in latching.The CNTs are then "unstuck" by applying a voltage betweenthe central CNT and the third CNT on the opposite side.Certain amount of energy is stored in the elastic deformationof the CNT when it is bent to make contact with a side CNT.This energy becomes available when the central CNT is

Figure 1. Complementary nano electro-mechanicalswitch (CNEMS). The central CNT (CNT1) is eithertouching the top (CNT2) or bottom (CNT3) one. Latchingis caused by the van der Waal force and the energystored in CNT1 is recovered when it is transitioned.

released and attracted to the opposite CNT. Noting that CNTshave very large Young's modulus of around 1.3 TPa, very fastCNEMS with sub-nanoseconds switching times can berealized provided that CNT lengths are kept below L<lOOnmthat in turn requires precise CNT-CNT distances of arounddc,11< 50nm. The proposed CNEMS have very large on-to-offconductance ratio (>1012), are radiation hard, and can befabricated on CMOS circuits.2.1. Device Characteristics

CNEMS characteristics critically depends on the kind ofcarbon nanotube we use, how close we place them near eachother and the bottom electrode, and how long the carbonnanotubes are. As discussed next, carbon nanotubes can besingle-walled (SWCNT) or multi-walled (MWCNT)depending on how they are grown and their growthtemperature. The MWCNTs are usually metallic whileSWCNTs can be both metallic and semiconducting. The gap

distance between CNTs and a bottom electrode can bedesigned to be between 20-lOOnm. Smaller gaps will result inunwanted van der Wall clamping of the CNTs to the bottomsurface while larger gaps will result in unacceptably larger"reset" voltage (Vr= reset voltage is the voltage needed to "un-stuck" all the CNTs from each other so that complete isolationcan be achieved between different parts of the circuit.) It isdesirable to have the CNT-CNT distance as small as possiblebecause then the threshold voltage (Vth= voltage needed toattract adjacent CNTs together) can be made very small andthe CNT length can be scaled down correspondinglyincreasing the transition speed (vt). We discuss theseparameters in detail below.2.2 Device Operation Principles

To calculate the turn-on, or the threshold, voltage we notethat the total energy of two adjacent CNTs is given by:

Et =EvdW + Eelastic + Eelectrostatic* The van der Waals

interaction between CNTs has been calculated by researchersand lower bound to the expected attractive energy can bedescribed using an empirical formula given byEVdW = (-0.053 + 0.086d)L eV, where "d' is the CNT

0

diameter expressed in A and L is the interaction length also0

in A. This empirical equation is only applicable when theCNTs are touching each other. When they are not, Leonard-Jones type of potentials that contain r-6 and r 12 CNT-CNTposition (r) dependences can be used to calculate EvdW as a

function of distance. The elastic energy can be calculatedusing beam mechanics model and is given by:

eastic 1.6 3 where Sis the displacement of CNT's

tip, E is the Young's modulus (-1.3 TPa for SWCNTs), and I

is the moment of inertia (= [d4 -d4 ], where di is the64

outer diameter of the CNT and d2 is its inner diameter). The

electrostatic energy is given by Eelectrostatic = CV where2C

C is the capacitance between two adjacent CNTs and V is the

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applied voltage. Considering two CNT's symmetricallybending toward each other, the "C" can be approximated usinga parallel cylinder capacitor with uniform distance d,nt It can

2 godLbe shown that C - . When the two CNTs touch

3 dCNTeach other, we have &-=d,,/2.

Next we note that the electrostatic

(F =-aEelectrostatic ) and van der Waalsdx

(FdW - vdW ) forces are both attractive while the

vx

elastic force (Feiastic - aEelastic ) is not. Thus, atax

aEtotal = 0, the total forces acting on the CNTs cancelax

out and result in a stable configuration. When

FVdW .Felastic (V=O V) the van der Waals forces overcome

the elastic force and CNTs can latch onto each other. Clearlythis situation should be achieved after application of a voltagepulse because otherwise, the CNTs' will spontaneously clamponto each other. This simple but important observation puts a

limit on how close CNTs can be to each other.The above equations can be solved to study scaling laws

of CNEMS and design devices with different feature sizes andcharacteristics. To demonstrate feasibility of switching andlatching with reasonable voltages and device structures, we

consider the CNEMS structure schematically shown in Fig. 1.Taking d,,t-2Onm, and L=5Onm, and dl-3nm, d2-3.5nm, we

calculate Eelasti,- 34 eV while EVdv-740 eV. The two energiesare equal at L-19nm for d-3.5nm and dc,1t of 20nm (6-lOnm).

Vi

CNT2 CNT2

CNT1 CNT1I

CNT3 CNT3(a) (b)

CNT2 CNT2

CNT1 CNT1

,c,CNT3 @ CNT3

V2

(c) (d)CNT2 CNT2

CNT1 - CNTI

Bottom gate- CNT3 CNT3

V3 (e) (f)

Figure 3. Schematic of CNEMS switching cycles. a) Avoltage pulse (VI) causes CNT1 to be attracted to CNT2.b) the van der Waals force latches CNT1 to CNT2. c) Totransition the switch, CNT1 and CNT2 are connectedtogether and a voltage pulse (V2) is applied betweenCNT1 and CNT3, d) which unlatches CNT1 from CNT2and latches CNT1 to CNT3. e) and f) to reset, a bottomgate will be used to apply a voltage pulse to all CNTs .

1.21

0.80.60.40.20

0 5 10 15 20

Voltage (V)

Figure 2. Simulated Switching characteristics of CNEMS(L-50nm, dr'3.5nm, d2-3nm, and d,nt-20nm, and5-10nm). During the programming phase, the thresholdvoltage is around 10 V. This voltage reducedconsiderably in subsequent cycles owing to recycling ofthe stored elastic energy.

The electrostatic potential needed to bend the 50nm-long CNTto achieve defection of 6 lOnm is around 10 V (this iscalculated by setting Eelectrostatic-Eelastic). In subsequentswitching, however, this voltage will be dropped to around 1 Vsince a large portion of the elastic energy stored in the CNTwill be recovered.

Based on the above considerations, we note that Vth-10 Vdropping to -1 volt after the initial cycle as shown in Fig. 2.The main reason for this reduction is that the stored elasticenergy causes the center CNT (CNT1 in Fig. 1) to spring backtowards the CNT3 when it is released from CNT2. The van derWaals force latching CNTI and CNT2 is almost entirelybalanced out as soon as CNT1 and CNT2 are charged with thesame polarity.

To calculate the switching speed we note that theresonant frequency of a CNT (see Fig. 1) is given by:

1SEIc = , where "m" is the CNT's mass and the rest of

parameters are defined above. For L-5Onm, the radialfrequency is around 3.16 xlO" radian/s corresponding to a

frequency of 50 GHz. This yields a transition speed (vt-wOL) ofaround 1.6x104 m/s that results in transition time (m-6/vt) ofaround 10-12_ 10-1° s. The charging time constants may limitthe CNEMS speed in the final circuits.

The device isolation resistance in "off' state can becalculated using the tunneling current between two adjacentand non-contacting CNTs as IL-oe dcnt/A where X isapproximately the De Broglie wavelength (-10 A) and I0-0.1gA (@ IV). For d,11t-20nm, I-2x10-6 A that yields an

isolation resistance of around 5x1015 Q.The device resistance in the "on" state is given by the

sum of contact resistances, the two CNT resistances and theCNT-CNT contact resistance. With good titanium carbide or

Pd contacts to the CNTs, the contact resistance can be madesmall (-lkQ). The CNT-CNT contact resistance when the twoCNTs are touching with an overlap of 30-5Onm, is also verysmall (this will be dictated by tunneling in clean CNTs). Theoverall resistance will be around 10 kQ (for pc1tl- kQ-cm).

The CNTs can be programmed by applying voltage pulsesto attract and latch adjacent CNTs to allow for setting the

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Figure 4. a) Carbon nanotubes (CNTs) we have grown using a metal-catalyzed (iron) chemical vapor depositiontechnique using C2H2 between two raised silicon posts. The self-aligned and welded CNTs can be grown into anylayer that can withstand the growth temperature of 500-800 °C. b) CNTs grown into a copper layer that wassubsequently sulfidized. c) CNTs grown over atomic force microscope tip with co-axial shielding.

current path in the circuit (Fig. 3(b), 3(d)). To "un-stuck" theCNTs, we integrate an electrode under the CNTs so that whena voltage is applied between the bottom electrode and theCNTs, the CNTs are attracted to the bottom electrode that willbe covered with a thin oxide layer to prevent current flow butto enable electrostatic actuation. The distance between theCNTs and bottom electrode will be set around 25nm so thatthe elastic energy of the bent CNTs will be larger than the vander Waals force to prevent latching with the bottom surface.Thus, after the resetting pulse is applied, the CNTs will relaxback to their initial pre-programmed state (Fig. 3(f)).2.3 Defect Tolerance at Device Level

CNEMS's operation critically depends on CNT diameter,length, location, and conductivity. We have developed ametal-catalyzed chemical vapor deposition growth techniquethat results in the growth of multi-walled and single-walledcarbon nanotubes that are self-aligned and self-welded tosilicon posts, as shown in Fig. 4. The CNT diameter dependson the diameter of the starting catalyst particles, growthtemperature and gas flow rates. These parameters are readilycontrolled to yield uniform CNT diameter. The post that theCNT grows from (see Fig. 4) is coated with a thin layer of iron(other metal catalysts such as Cu, Ni, etc. that are morecompatible with CMOS can also be used). The post that theCNT grows into can be coated with a variety of suitablematerials or left as a bare silicon or it can be coated with asacrificial oxide layer that upon removal will free the CNTtips. To ensure regular CNT lengths, we will use a CNT-

growth stop composed of a sacrificial oxide layer. The CNT'sgrowth will be stopped by this oxide layer. Subsequently, theoxide layer will be etched away leaving CNT cantilever beamswith nearly identical lengths in place. The CNT location canbe specified using nanopores on oxide or similar material or bypatterning the catalyst layer. The CNT conductivity dependson the chirality of the graphene layer in single walled CNTsand 2/3 of grown SWCNTs are semiconducting while 1/3 aremetallic. By adding another layer to grow double-walledCNTs, majority of DWCNTs become metallic because twolayers of different chirality or even the same chirality areshown to produce metallic CNTs.

Thus, the uncertainty in CNT length can be reduceddrastically by using sacrificial oxide growth stop layers. TheCNT positions can be dictated by using patterned catalystlayer or nanopores/nano-openings, and metallic CNTs can beproduced by growing DWCNTs.

3. CIRCUIT IMPLEMENTATIONAs described in Section 2, the proposed CNEMS device

has fundamentally different principle of operation compared toconventional MOSFET. Thus, logic and memory design withthese devices require a major shift in design methodology.3.1. Logic Behavior of CNEMS

To understand how the proposed switch can be used torealize logic function, let us discuss the behavior of the switchin terms of logical operation. Fig. 5(a) depicts the schematicdiagram of the switch, which has three terminals A, B and C.

Depending on the voltage differentialCNT2 r1 c between the terminals, either A or B (not

X both) may be connected to terminal C.9X_1 out

For a given voltage at A and B, we canEL CNT3consider C as the controlling terminal,

which determines configuration of theBIC Out switch. However, unlike MOSFET, the

) 0 Open complementary nature of the CNEMSO IOegal does not allow a signal path between B10 1 and C. From Fig. 5(b), we can observeo 0 that by using two-valued logic, CNEMS0 1 switch can be taken to one of the four

I1 0 states. Apart from the two states

I 0 Ilegal discussed earlier (where terminal C iso Open connected to either A or B), the switch

11l OpenI 'afa r] { ; r t

Figure 5. a) b) ProgrammingSchematic of CNEMS. CNEMS.

c) Logical behavior ofCNEMS.

mayc ectdmpietey openB) ws nalconnected to any of A or B) when all

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A T2 A -

B No CNT3 B

A -1 1 CNT2

CNT2_l_ C A B C State AIKLEO 0 0 Open 0 C

B CNT3 O) 0 1 Indet 0 CO 1 0 B-C 0 10 1 1 A-C 0 11 0 0 A-C 1 C1 0 1 B-C 1 C1 1 0 Indet 1 11 1 1 Open 1 1

B

- 17 - --

In

VssVdd Out

Vdd->Vss

Figure 6. a) An inverting b) Clocked latch in initialclocked latch design. The position before writing.complement of the data With a pulse to the bottominput at D is latched by terminals it is "reset"the clock. removing history effect.terminals have the same voltage or state of the switch may beindeterminate, when both A and B have the same voltagedifference with respect to C. In the later case, position of theswitch will eventually depend on the relative strength of theCNTs at A and B, which will be determined by designmarginalities like process variations. This state therefore,should be considered as "illegal" with respect to logic design.It can be observed that the switch can be used for pass-transistor like logic implementation. However, it requires twosteps to evaluate the logic. In the first step, terminal C can beused to configure the switch by applying appropriate voltagedifferential. In the second step, terminal C should bedisconnected from the controlling input and treated as theoutput. Fig. 5(c) shows the truth table for the logic operationof the switch with C as controlling input. It can be noted thatoutput terminal has a valid state as long as A ( B = 1.

However, if A (3 B = 1 and terminal C is connected to A, twoCNTs connected together (A and C) will be charged with thesame polarity and hence terminal C will be attracted towardsB, resulting in an unstable state. To avoid this, we can connecttwo CNEMS devices as in Fig. 6(a), which realizes a stableWr =O

10 IIll

MUX

Tree(CMOS)

BL

VDD _ / Data=1 _WW~~~~~~~ I

VDD

VDD [ , Data=O

WL, VDD

VDD Data=O

Out WL VDD

VDD _ Data = 1

WL VDD

In

Rea

Vdd VedIn

Data = 0 Vdd Vdd Data

_Vss VssVss t= Vss

(a) (b)Figure 7. Two possible implementations of a two-inputlookup table (LUT) using CNEMS. In (a), decoding isrealized with a multiplexer tree implemented with CMOS.A separate decoder and a set of selection switches(circled) are required for the implementation in (b).

c) Latch storing logic 1 in d) Latch storing logic 0.response to a data value0. Notethat it is aninverting latch.

inverting latch controlled by the clock signal that connects andisolates the input from one of the side terminals. To write a

value in the latch, it requires to be configured as in Fig. 6(b),by creating a voltage difference between terminals B and C.Taking the latch to this "reset" state is important to remove

history effect and to allow the CNTs to make a transition whenthe input is connected. Fig. 6(c) and Fig. 6(d) show two validstates of the latch storing logic 1 and 0, respectively.3.2 Reconfigurable Logic Fabric

Stable and reconfigurable logic functions can be realizedwith CNEMS using small memory array organized as lookuptable, similar to conventional SRAM-based FPGA [13]. Fig. 7shows schematic of two possible implementations of a LUTfor a 2-input function. Each storage bit is realized by two (Fig.7(a)) or one (Fig. 7(b)) CNEMS device(s). In Fig. 7(a), thedecoding is implemented with a multiplexer tree (implementedwith CMOS switches), while in Fig. 7(b) additional decoderand select switches (circled) are required. In the rightschematic, depending on the input signals, one of the wordlinewill be asserted. A common bitline connected to a CNEMS-based latch (Fig. 6) will latch the value. In a multilevel logicimplementation using LUT, the schematic in Fig. 7(a) is moreefficient in terms of delay, while the one in Fig. 7(b) takes lessarea. The propagation delay in the left configuration iscontributed by scattering-free (ballistic) propagation throughthe CNTs and signal propagation through the mux-tree. On theother hand, propagation delay on the right configuration isdominated by the transition delay (-Ins) of the sensingCNEMS, which accumulates for multi-level logic.

The CNEMS can also be used, in interesting ways, torealize complex functions with very few basic switches. For

Inl_Out1

In2 _ =Out2

(a)B

A ; _ OutOO

VDD

Outl O

l~~~~~~~~~~~OtIFA' Ot1

(b)Figure 8. a) Interesting switch matrix using CNEMS; b)Implementation of 2X4 decoder circuit using CNEMSdevice (configured for A=O, B=0).

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CkEIn

A

B VSS

B VssVs CIkE

Out

C1k

Vdd Out

In

Vdd

Vss

Out

.-

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Table 1. Comparison of delay and power results between CMOS and CNEMS implementationDelal (sec) Power (watt)

Circuit CNEMS CMOS (70nm, CNEMS CMOS (70nm, IV, 100°C)IV, 100IC) Dynamic Leakage Total

Ripple Carry Adder (4-bit) 6.125e-1 1 1.392e-10 58.38e-08 6.570e-06 8.972e-06 1.542e-05Magnitude Comparator (4-bit) 7.877e- 1I 3.481e- 1I 18.07e-08 1.859e-06 2.689e-06 4.548e-06Priority encoder (8:3) 5.252e-1 1 7.143e-1 1 23.63e-08 2.470e-06 3.328e-06 5.798e-06Even Parity (8-bit) 6.127e- 11 2.205e-10 29.19e-08 3.701 e-06 4.903e-06 8.604e-06

example, Fig. 8(a) shows implementation of a specificcrossbar switch matrix where only one output is connected toone input at a time. Fig 8(b) describes a customizedimplementation of a decoder circuit (2X4), which requires lessnumber of primitive switches and less active power comparedto static CMOS implementation. The proposed logicimplementations have robust switching operation, low activepower for switching states (along with negligible leakage).The reconfiguration can be accomplished at high speed bywriting configuration bits to CNEMS switches forcingtransition (with -1GHz transition speed). It is worth notingthat since the non-volatile memory cell implemented withCNEMS device is not charge-based, the stored value does notflip due to alpha or neutron particle hit, and hence, completelyimmune to soft error [14]. The selection switches (connectedto the wordline, bit line and data inputs), decoding logic (Fig.7(b)) and mux-tree (Fig. 7(a)) can be implemented withMOSFET switches for high speed and ease of fabrication.

4. MODELING AND RESULTSWe have used a simple model of CNEMS device

schematically shown in Fig. 9. The R12 and R13 areproportional to 1/112 and 11113 (Fig. 3). Using the simple modelin Fig. 9, we have computed power and performance for a setof circuits implemented with two-input LUT-based functions(as described in Fig. 7(a)). The circuit descriptions weresynthesized from Verilog using Synopsys Design Compilerand then mapped to 2-input Boolean functions. In thisexperiment, we used a hybrid implementation with MOSFETpass transistor (NMOS) for mux-tree and CNEMS switchbased storage element. The power and delay for a two-inputpre-configured LUTs were contributed by a) two CNTsmaking a connection and b) a NMOS pass transistor. The biasvoltage of the CNEMS device was set to 1V. To compare theeffectiveness of CNEMS-based implementation with staticCMOS implementation, we computed power and performancefor static CMOS realization of the circuits using a 70nmpredictive technology model (at 100°C, with a supply voltageof lV). The simulation results are reported in Table 1. We canobserve that the CNEMS based implementation has delayvalues of the same order as70nm static CMOScircuits, since thepropagation delay in amulti-level CNEMScircuit is contributed bythe ballistic transport inthe CNTs and signalpropagation through themux-tree. However, interms of total power,

R12

C12 P2

Pi L12

L13C23

C~13 P3

R13

Figure 9. Simple model of theswitch that is used in circuitsimulations.

CNEMS implementation consumes orders of magnitude lesspower compared to CMOS counterparts. Note that theCNEMS in the LUTs do not switch during normal operationand switches only during reconfiguration. The internal energystorage helps to achieve low reconfiguration energy.

5. CONCLUSIONWe have proposed a novel Nano Electro-Mechanical

switch that exploits unique properties of carbon nanotube. Theswitch can provide robust low-voltage operation. Two mostimportant features of this device are: a) its internal energystorage and negligible leakage for ultralow-power operationand b) reconfigurability into a non-volatile memory element.The device is amenable to look-up table based reconfigurablelogic implementation and can be fabricated with conventionalCMOS devices for hybridization. We have developed simplecircuit-compatible models of the proposed switch anddemonstrated that system development using CNEMS canachieve orders of magnitude power reduction while havingequivalent performance compared to a CMOS implementation.

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