Two-Dimensional Analytical Modeling of Fully Depleted Dual-Material Gate (DMG) SOI MOSFET and...

8/14/2019 Two-Dimensional Analytical Modeling of Fully Depleted Dual-Material Gate (DMG) SOI MOSFET and Evidence for Di

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Two-dimensional analytical modeling of

Fully Depleted Dual-Material Gate (DMG) SOI MOSFET andEvidence for Diminished Short-channel Effects

M. Jagadesh Kumar1

and Anurag Chaudhry

Department of Electrical Engineering,

Indian Institute of Technology, Delhi,

Hauz Khas, New Delhi 110 016, INDIA.

Email: [email protected]: 91-11-2658 1264

1Corresponding author

M. Jagadesh Kumar and Anurag Chaudhry, "Two-Dimensional AnalyticalModeling of Fully Depleted Dual-Material Gate (DMG) SOI MOSFET andEvidence for Diminished Short-Channel Effects", IEEE Trans. onElectron Devices Vol.51 .569-574 A ril 2004.


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Abstract

A 2-D analytical model for the surface potential variation along the channel in fully depleted

Dual-Material Gate silicon-on-insulator (DMG-SOI) MOSFETs is developed to investigate

the short-channel effects. Our model includes the effects of the source/drain and body doping

concentrations, the lengths of the gate metals and their work functions, applied drain and

substrate biases, the thickness of the gate and buried oxide and also the silicon thin-film. We

demonstrate that the surface potential in the channel region exhibits a step function which

ensures the screening of the drain potential variation by the gate near the drain resulting in

suppressed short-channel effects like the hot-carrier effect and drain-induced barrier-lowering

(DIBL). The model is extended to find an expression for the threshold voltage in the sub-

micron regime, which predicts a desirable roll-up in the threshold voltage with decreasing

channel lengths. The accuracy of the results obtained using our analytical model is verified

using 2-D numerical simulations.

Index Terms: Silicon-on-Insulator MOSFET, Short-channel effects, Threshold voltage,Device scaling, Insulated Gate Field Effect Transistors, Two-dimensional modeling


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1. Introduction

In keeping with the progress in process technology, CMOS devices have been scaled

down continuously pushing the MOS technology into the deep-submicron era. However,

when the channel length shrinks, the absolute value of threshold voltage becomes smaller due

to the reduced controllability of the gate over depletion region by the increased charge

sharing from source/drain. Therefore, the study of short-channel effects (SCEs) has assumed

a significant role because both the threshold voltage roll-off at decreasing gate length as well

as drain-induced barrier-lowering (DIBL) at increasing drain voltage pose a serious challenge

to the efforts for down scaling the CMOS technology.

Thin-film, fully-depleted silicon-on-insulator (SOI) MOSFETs offer superior

electrical characteristics over bulk MOS devices , such as reduced junction capacitances,

increased channel mobility, excellent latchup immunity and reduced SCEs [1]. As a

consequence, deep-submicron SOI circuit design and simulation are increasingly becoming

important in VLSI technology research. In contrast to the bulk device, the front gate of the

SOI device has better control over its active device region in the thin-film and hence charge

sharing effects from source/drain regions are substantially reduced. However, the thin-film

thickness has to reduce to the order of 10 nm to significantly improve the device

performance, which becomes prohibitively difficult to manufacture and causes large device

external resistance due to shallow source/drain extension (SDE) depths

Long et al [2] recently demonstrated that the application of dual-material gate (DMG)

in bulk MOSFET leads to a simultaneous transconductance enhancement and suppression of

short-channel effects due to the introduction of a step function in the channel potential. In a

DMG-MOSFET, the work function of metal gate 1 (M1) is greater than metal gate 2 (M2)

i.e., M1 > M2 for an n-channel MOSFET and vice-versa for a p-channel MOSFET.

However, the effects of the DMG structure have not been studied so far in the case of SOI


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MOSFETs which play an important role in the present day CMOS design. The aim of this

work is, therefore, to study for the first time the potential benefits offered by the DMG gate in

suppressing the short-channel effects in SOI MOSFETs using two-dimensional modeling. In

this paper an analytical short-channel model for a fully depleted DMG-SOI MOSFETs is

presented by solving the 2-D Poisson equation. The model is used to calculate the surface

potential distribution in the SOI thin-film under the two metal gates and explain the unique

attributes of the DMG structure in suppressing the short-channel effects like hot-carrier

effect, DIBL and threshold voltage Vth roll-up in SOI-MOSFETs. This model thus

provides an efficient tool for design and characterization of the novel DMG-SOI MOSFET.

The effects of varying device parameters can easily be investigated using the simple models

presented in this work. The model results are verified by comparing them with the 2-D

simulated results from MEDICI [3].

2. Two-Dimensional Model for the Surface Potential

A schematic cross-sectional view of a fully depleted SOI MOSFET is shown in Fig.1

with gate metals M1 and M2 of lengthsL1 andL2, respectively. Assuming that the impurity

density in the channel region is uniform and the influence of charge carriers and fixed oxide

charges on the electrostatics of the channel can be neglected, the potential distribution in the

silicon thin-film, before the onset of strong inversion can be written as [4]

( ) ( )2 2

2 2

, ,A

Si

d x y d x y qN

dx dy

+ = for 0 , 0 Si x L y t (1)

whereNA is the film doping concentration, Si is the dielectric constant of silicon, Sit is the film

thickness and L is the device channel length. The potential profile in the vertical direction,

i.e., the y-dependence of ( ),x y can be approximated by a simple parabolic function as

proposed by Young [4] for fully depleted SOI MOSFETs.

( ) ( ) ( ) ( )2

1 2, Sx y x c x y c x y = + + (2)


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where ( )S x is the surface potential and the arbitrary coefficients ( )1c x and ( )2c x are

functions ofx only.

In a conventional SOI-MOSFET, the gate is made of only one material, but in the

DMG structure, we have two different materials with different work functions, which are

amalgamated together laterally. Therefore, the flat-band voltage for the two gates would be

different, as it depends upon 1M and 2M , the metal work functions of M1 and M2,

respectively, which are given as

1 1 1FB MS M SV = = and 2 2 2FB MS M SV = =

The semiconductor work function can be written as

2

g

S Si F

E

q = + +

where, ( )lnF T A iV N n = is the Fermi potential, gE is the silicon bandgap, Si is the

electron affinity, TV is the thermal voltage and in is the intrinsic carrier concentration.

In the DMG structure, since the gate is divided into two parts, the potential under gate

regions M1 and M2, can be written as

( ) ( ) ( ) ( ) 21 1 11 12, Sx y x c x y c x y = + + for 10 , 0 Si x L y t (3)

( ) ( ) ( ) ( ) 22 2 21 22, Sx y x c x y c x y = + + for 1 1 2 , 0 SiL x L L y t + (4)

The Poissons equation is solved separately under the two gate regions using the following

boundary conditions:

1. Electric flux at the gate/front-oxide interface is continuous for both the metal gates.

( ) ( ) '1 1 1

0

, S GSox

Si fy

d x y x V

dy t

=

= for Metal1 (5)

( ) ( ) '2 2 2

0

, S GSox

Si fy

d x y x V

dy t

=

= for Metal2 (6)

where ox is the dielectric constant of the oxide, ft is the gate oxide thickness, and

'

1 1,GS GS FB f V V V= and'

2 2,GS GS FB f V V V=


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where GSV is the gate-to-source bias voltage, 1,FB fV and 2,FB fV are the front-channel flat-

band voltages of Metal 1 and Metal 2, respectively.

2. Electric flux at the interface of buried oxide and the back-channel is continuous for both

the metal gates.

( ) ( )'1 ,

Si

SUB Box

Si by t

d x y V x

dy t

=

= for Metal1 (7)

( ) ( )'2 ,

Si

SUB Box

Si by t

d x y V x

dy t

=

= for Metal2 (8)

where bt is the buried oxide thickness, ( )B x is the potential function along the back-

side oxide-silicon interface, and ' ,SUB SUB FB bV V V= , where, SUBV is the substrate bias and

,FB bV is the back-channel flat-band voltage.

3. Surface potential at the interface of the two dissimilar metals is continuous

( ) ( )1 1 2 1,0 ,0L L = (9)

4. Electric flux at the interface of the two dissimilar metals is continuous

( ) ( )

1 1

1 2, ,

x L x L

d x y d x y

dx dx

= =

= (10)

5. The potential at the source end is

( ) ( )1 10,0 0S biV = = (11)

6. The potential at the drain end is

( ) ( )2 1 2 2 1 2,0 S bi DS L L L L V V + = + = + (12)

where ( ) ( )2 lnbi g T A iV E V N n= + is the built-in potential across the body-source junction.

The constants ( )11c x , ( )12c x , ( )21c x and ( )22c x in equations (3) and (4) can be deduced

from the boundary conditions (5) (8). Substituting their values in (3) and (4) and then in (1)

we obtain

( )

( )

2

1

1 12

S

S

d x

xdx

= and( )

( )

2

2

2 22

S

S

d x

xdx

= (13)


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where

( )( )2

2 1

1 2

f b f Si

Si Si b

C C C C

t C C

+ +=

+

( ) ( )' '

1 1 2 2

12 2

1 2 1 2

f b f SiAGS SUB

Si Si Si b Si Si b

C C C C qNV V

t C C t C C

+= + + and

( ) ( )' '

2 2 2 2

12 2

1 2 1 2

f b f SiAGS SUB

Si Si Si b Si Si b

C C C C qNV V

t C C t C C

+= + +

where Si Si SiC t= , ox fC t= and b ox bC t= .

The above equations are simple second-order non-homogenous differential equations with

constant coefficients which have a solution of the form

( ) ( ) ( )1 1 2 1exp expS x A x B x = + (14)

( ) ( )( ) ( )( )2 1 1 2 1 2exp expS x C x L D x L = + (15)

where 1 = and 2 = . Now using boundary conditions (9) (12) to solve forA,B,

CandD , we obtain

( ) ( )( ) ( ) ( ) ( )( )( ) ( )( )

2 1 1 2 1 1 2 1 2

1 1 2

1 1 2

exp cosh

exp1 exp 2

bi DS biV V L L V L

A L LL L

+ + = + +

( ) ( ) ( )( ) ( ) ( ) ( )( )( )( )

1 2 1 1 2 1 2 1 2 1 1 2

1 1 2

exp cosh exp

1 exp 2

bi bi DSV V V L L L L LB

L L

+ + + +=

+

( )( )1 2

1 1exp2

C A L

= + and ( )( )1 2

2 1exp2

D B L

= +

where 1 1 = and 2 2 = . The above expression for surface potential can be

reduced to the form presented in [4] for a single material gate (SMG) structure upon

substituting 1 2 f = = and 1 2 L L L+ = in (14).

The minimum potential of the front-channel can be calculated from (14) as

1,min 12S AB = + (16)

The minima occurs at


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min

1

1ln

2

Bx

A

=

(17)

DIBL effect can be demonstrated by plotting the surface potential minima S1,min, as a

function of the position along the channel for different drain bias conditions.

The electric field pattern along the channel determines the electron transport velocity

through the channel. The electric field component in thexdirection, under the metal gates

M1 and M2 is given as

( )( ) ( )

( ) ( )1 11 1 1 2 20

,exp exp

S

y

d x y d x E x A x B x

dx dx

=

= = = + (18)

( )( ) ( )

( )( ) ( )( )2 22 1 1 1 2 2 10

,exp exp

S

y

d x y d x E x C x L D x L

dx dx

=

= = = + (19)

The above two equations are useful in examining how the drain side electric field is modified

by the DMG structure.

3. Two-dimensional Threshold Voltage Model for the DMG FD SOI MOSFET

The threshold voltage thV is that value of the gate voltage GSV at which a conducting

channel is induced at the surface of SOI MOSFET. In a fully depleted thin-film SOI, it is

desirable that the front channel turns on before the back channel. Therefore, the threshold

voltage is taken to be that value of gate source voltage for which ,min 2S F = , where F is

the difference between the extrinsic Fermi level in the bulk region and the intrinsic Fermi

level. In the case of DMG structure, due to the co-existence of metal gates, M1 and M2, with

different work functions, the surface potential minima is solely determined by the metal gate

with higher work function. So the threshold voltage is defined as the value of GSV at which

the minimum surface potential 1,minS equals 2 F . Hence we can determine the value of

threshold voltage as the value of GSV by solving (16).


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When andb f SiC C C


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In Fig. 2, the calculated and simulated values of surface potential are plotted against

the horizontal distance x in the channel for channel lengths of 0.1 m and 0.2 m at

different drain voltages. It can be seen from the figure that due to the presence of the dual-

material gate, there is no significant change in the potential under the gate M1 as the drain

bias is increased even for channel lengths upto 100 nm. Hence, the channel region under M1

is screened from the changes in the drain potential, i.e., the drain voltage is not absorbed

under M1 but under M2. As a consequence, DSV has only a very small influence on drain

current after saturation and the drain conductance is reduced. It is evident from the figure

that the shift in the point of the minimum potential is almost zero irrespective of the applied

drain bias. This is a clear indication that the DIBL effect is considerably reduced for the

DMG-SOI MOSFET. The model predictions correlate well with the simulation results

proving the accuracy of our proposed analytical model.

In Fig. 3, the electric distribution along the channel near the drain is shown for SMG

and DMG-SOI MOSFETs with a channel length L = 0.4 m. It is evident from the figure

that the presence of a lower function gate at the drain side reduces the peak electric field

considerably. This reduction of the electric field experienced by the carriers in the channel

can be interpreted as the reduction of the hot-carrier effect at the drain end. As shown in the

figure, the results from the analytical model are in close proximity with the simulation results.

Fig. 4 shows the variation of surface potential with the normalized channel position

for different combination of gate lengths L1 andL2of M1 and M2, respectively, keeping the

sum of total gate length, (L1+L2),to be constant. It is seen from the figure that the position of

minimum surface potential, lying under M1 is shifting toward the source as the length of gate

M1 is reduced. This causes the peak electric field in the channel to shift more towards the

source end and thus there is a more uniform electric field profile in the channel. Moreover, it

is observed that the channel potential minima for the three cases are not the same. This


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happens because as L1 increases, a portion of the channel controlled by the gate metal with

larger workfunction [6] is increased.

The variation of the front-channel minimum potential as a function of channel length

L (=L1+L2) for fully depleted DMG-SOI with silicon thin-film thickness tSi = 100 nm and 50

nm is shown in Fig. 5. In the case of DMG-SOI MOSFET, the dependence of minimum

channel potential on the thin-film thickness can be more effectively reduced by decreasing tSi

as compared to the SMG-SOI MOSFETs. This is due to the existence of a workfunction

difference in the case of DMG-SOI MOSFETs. The validity of model for the minimum

surface potential under the gate for different combinations ofL1 and L2 ofM1 and M2 is

verified by the close match between the analytical results and the 2-D simulation results[3].

In Figure 6, the calculated values of threshold voltage as a function of channel-length

are compared with those obtained from 2-D simulation [3] extracted from the commonly used

maximum transconductance method for two different values of L1. It is seen from Figure

6(a) that the threshold voltage obtained from the analytical model tracks the simulation

values very well but with an insignificant negative offset of approximately 90 mV whereas

the offset is nearly 20-50 mV for Figure 6(b). This small discrepancy between analytical and

simulated VT values is due to the two different definitions of threshold voltage used for

comparison viz., 2F and max. gm. As is often done in literature, in our model we have used

s = 2F as the threshold condition while MEDICI calculates the threshold voltage from the

maximum gm condition. The model results compared with simulation data, however, justify

the validity of the model for channel lengths well up to 100 nm and as can be discerned from

the figures, the predictions are in line with MEDICI results.

In Figure 7, the effect of gate-workfunction engineering on the threshold voltage is

shown for a fully depleted DMG-SOI MOSFET of channel lengthL (=L1+L2) 0.5 m for two

different ratios ofL1andL2. It is evident that with the increasing workfunction difference,


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threshold voltage increases but, for the same workfunction difference a higher L1/L2 ratio

leads to a corresponding increase in threshold voltage. This is due to the increasing

proportion of channel lengthL, under the larger workfunction gate M1.

5. Conclusions

For the first time, we have examined the effectiveness of the Dual-Material-Gate

structure in fully depleted SOI MOSFETs to suppress short-channel effects by developing a

2-D analytical model for surface potential and threshold voltage and comparing the results

with accurate MEDICI [3] simulations. The calculated values of the surface potential in the

silicon thin-film obtained from the proposed model agree well with the simulated results.

Our results unambiguously establish that the introduction of the DMG structure in a fully

depleted SOI MOSFET leads to subdued short-channel effects due to a step-function in the

channel potential profile. The shift in the surface channel potential minima position is

negligible with increasing drain biases. The electric field in the channel at the drain end is

also reduced leading to reduced hot-carrier effect. Also, the variation of the minimum

channel potential with decreasing thin-film thickness can be more effectively reduced in the

DMG structure at shallow thin film thicknesses. Further, it is clearly seen that the DMG

structure gives rise to the desirable threshold voltage roll-up with decreasing channel

lengths. Thus, the introduction of the DMG structure opens up a new avenue to improve the

short-channel behavior of the SOI MOSFETs over their single gate SOI and the bulk

counterparts.

One of the difficulties in integrating DMG structure in the present CMOS technology

maybe the increased constraint on lithography due to its asymmetric gate structure. Zhou [5]

suggested two fabrication procedures requiring only one additional mask step for realizing

the DMGFET in bulk CMOS technology. Wong et al. demonstrated a DMG-HFET using the

method of tilt angle evaporation (TAE) [2]. With the CMOS processing technology


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aggressively pushing forward, fabricating sub-100 nm feature gate lengths should not

preclude the possibility of realizing the substantial performance gains over conventional SOI

and excellent immunity against SCEs that the DMG-SOI MOSFET promises.


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References

[1] T. Ohno, Y. Kado, M. Harada; T. Tsuchiya, Experimental 0.25-m-gate fully depleted

CMOS/SIMOX process using a new two-step LOCOS isolation technique, IEEE

Trans. Electron Devices, vol. 42, pp.1481-1486, August 1995.

[2] W. Long, H. Ou, J.-M. Kuo, and K. K. Chin, Dual material gate (DMG) field effect

transistor,IEEE Trans. Electron Devices, vol. 46, pp.865-870, May 1999.

[3] MEDICI 4.0, Technology Modeling Associates, Inc., Palo Alto, CA, 1997.

[4] K. K. Young, Short-Channel Effect in Fully Depleted SOI MOSFETs,IEEE Trans.

Electron Devices, vol. 36, pp.399-402, February 1989.

[5] X. Zhou, Exploring the novel characteristics of Hetero-Material Gate Field-Effect

transistors (HMGFETs) with gate-material engineering, IEEE Trans. Electron

Devices, vol. 47, pp.113-120, January 2000.

[6] X. Zhou and W. Long, A Novel Hetero-Material Gate (HMG) MOSFET for deep-

submicron ULSI technology, IEEE Trans. Electron Devices, Vol. 45, pp. 2546-2548,

December 1998.


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Figure Captions

Figure 1 : Cross-sectional view of an n-channel fully depleted DMG-SOI MOSFET.

Figure 2(a) : Surface channel potential profiles of a fully depleted DMG-SOI MOSFET

obtained from the analytical model and MEDICI simulation for different drain

biases with a channel lengthL = 0.1 m.

Figure 2(b) : Surface channel potential profiles of a fully depleted DMG-SOI MOSFET

obtained from the analytical model and MEDICI simulation for different drain

biases with a channel length L = 0.2 m. The screening effect is distinctly

visible. The parameters used are : tf= 5 nm, tb = 450 nm, tSi = 150 nm and

VSUB = 0 V.

Figure 3 : Longitudinal electric field along the channel towards the drain end obtained

from the analytical model and MEDICI simulation in DMG-SOI and SMG-SOI

MOSFETs with a channel length L = 0.4 m and a drain bias VDS = 1.75 V.

The parameters used are : VGS = 0.15 V, tf= 5 nm, tb = 400 nm, tSi = 100 nm,

VSUB = 0 V andNA = 6 x 1016

cm-3.

Figure 4 : Variation of surface potential with position in channel for different

combination of gate lengthsL1 andL2, keeping the sum (L1+L2) constant.

Figure 5 : Variation of the front-channel minimum potential with channel length L

(=L1+L2) for fully depleted DMG-SOI MOSFETs for different silicon thin-

film thickness and withL1 constant at 0.1 m. The parameters used are: VGS =

0.15 V, tf= 5 nm, tb = 400 nm and VSUB = 0 V.

Figure 6(a) : Threshold voltage versus channel length for channel lengths upto 100 nm with

VDS = 50 mV.

Figure 6(b) : Threshold voltage versus channel length for VDS = 50 mV. The parameters


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used are:, tf= 5 nm, tb = 450 nm, tSi = 50 nm and VSUB = 0 V.

Figure 7 : Threshold voltage variation with gate workfunction difference with M2 fixed

at 4.1 eV for the DMG-SOI MOSFET a with channel lengthL (=L1+L2) of 0.5

m. The parameters used are : tf = 5 nm, tb = 400 nm, tSi = 50 nm, VSUB = 0 V

and NA = 6 x 1016

cm-3

.


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p substrate

Burried oxide

n

+

n+

tf

L1

L2

x

y

Gate

DrainSource

Substrate

tSi

tb

M1 M2

p substrate

Burried oxide

n

+

n+

tf

L1

L2

x

y

Gate

DrainSource

Substrate

tSi

tb

p substrate

Burried oxide

n

+

n+

tf

L1

L2

x

y

Gate

DrainSource

Substrate

tSi

tb

M1 M2

Figure 1.


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M1 M2 DS

0.0 0.02 0.06 0.08 0.120.0

1.0

2.0

2.5

Position in channel (m)

SurfacePote

ntial(Volts)

MEDICI

Model

VGS = 0.15 V

NA = 1 x 1017 cm-3

L = 0.1 m

M1 = 4.77 V

M2 = 4.1 V

VDS = 0.25 V

VDS = 1.0 V

0.5

1.5

0.04 0.10-0.02

M1 M2 DS

0.0 0.02 0.06 0.08 0.120.0

1.0

2.0

2.5


SurfacePote

ntial(Volts)

MEDICI

Model

VGS = 0.15 V

NA = 1 x 1017 cm-3

L = 0.1 m

M1 = 4.77 V

M2 = 4.1 V

VDS = 0.25 V

VDS = 1.0 V

0.5

1.5

0.04 0.10-0.02

Figure 2(a).


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M1 M2 DS

0.0 0.05 0.10 0.15 0.200.0

1.0

2.0

3.0

Position in channel (in m)

SurfacePotential(

involts)

MEDICIModel

VGS = 0.15 V

NA = 6 x 1016 cm-3

L = 0.2 m

M1 = 4.77 VM2 = 4.1 V

VDS = 0.25 V

VDS = 0.95 V

VDS = 1.75 V

M1 M2 DS

0.0 0.05 0.10 0.15 0.200.0

1.0

2.0

3.0


SurfacePotential(

involts)

MEDICIModel

VGS = 0.15 V

NA = 6 x 1016 cm-3

L = 0.2 m

M1 = 4.77 VM2 = 4.1 V

VDS = 0.25 V

VDS = 0.95 V

VDS = 1.75 V

Figure 2(b).


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0

50

100

150

200

250

300

350

400

450

500

0.30 0.32 0.34 0.36 0.38 0.40

ElectricFiel

d(kV/cm)


M1 = 4.77 V

M2 = 4.1 V

L1 = 0.1 m

L2 = 0.3 m

DMG-SOI

SMG-SOI M = 4.77 V

L = 0.4 m

MEDICI (DMG)Model (DMG)MEDICI (SMG)

0

50

100

150

200

250

300

350

400

450

500

0.30 0.32 0.34 0.36 0.38 0.40

ElectricFiel

d(kV/cm)


M1 = 4.77 V

M2 = 4.1 V

L1 = 0.1 m

L2 = 0.3 m

DMG-SOI

SMG-SOI M = 4.77 V

L = 0.4 m

MEDICI (DMG)Model (DMG)MEDICI (SMG)

Figure 3.


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0.0 0.05 0.10 0.15 0.200.0

0.5

1.0

1.5


SurfacePotent

ial(Volts)

MEDICI

Model

VGS = 0.15 V

VDS = 0.25 V

L = 0.2 m

M1 = 4.77 V

M2 = 4.1 V

NA = 6 x 1016 cm-3

L1/L2 = 0.08/0.12

L1/L2 = 0.10/0.10

L1/L2 = 0.12/0.08

2

2

1

3

1

3

0.0 0.05 0.10 0.15 0.200.0

0.5

1.0

1.5


SurfacePotent

ial(Volts)

MEDICI

Model

VGS = 0.15 V

VDS = 0.25 V

L = 0.2 m

M1 = 4.77 V

M2 = 4.1 V

NA = 6 x 1016 cm-3

L1/L2 = 0.08/0.12

L1/L2 = 0.10/0.10

L1/L2 = 0.12/0.08

22

22

11

33

11

33

Figure 4.


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VDS = 50 mV

M1

= 4.5 V

M2 = 4.1 V

L1 = 0.1 m

NA = 6 x 1016 cm-3

ModelMEDICI

0.0 0.2 0.4 0.6 0.8 1.00.2

0.4

0.6

0.8

1.0

tSi = 50 nm

tSi = 100 nm

MinimumSur

facePotential(involts)

Channel Length (in m)

VDS = 50 mV

M1

= 4.5 V

M2 = 4.1 V

L1 = 0.1 m

NA = 6 x 1016 cm-3

ModelMEDICI

0.0 0.2 0.4 0.6 0.8 1.00.2

0.4

0.6

0.8

1.0

tSi = 50 nm

tSi = 100 nm

MinimumSur

facePotential(involts)


Figure 5.


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50 100 200 300 400 500

Channel Length (nm)

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

ThresholdVoltage,

Vth

(Volts) Model (DMG)

MEDICI (DMG)

L1 = 50nm

tSi = 50 nm

tf = 2 nm

tb = 400 nm

VDS = 50 mV

NA = 1017 cm-3

MEDICI (SMG)

M1 = 4.77 V

M2 = 4.1 VDMG-SOI:

M = 4.77 VSMG-SOI:

0

50 100 200 300 400 500

Channel Length (nm)

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

ThresholdVoltage,

Vth

(Volts) Model (DMG)

MEDICI (DMG)

L1 = 50nm

tSi = 50 nm

tf = 2 nm

tb = 400 nm

VDS = 50 mV

NA = 1017 cm-3

MEDICI (SMG)

M1 = 4.77 V

M2 = 4.1 VDMG-SOI:

M = 4.77 VSMG-SOI:

0

Figure 6(a)


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24

0.1 0.2 0.4 0.6 0.8 1.0


0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

ThresholdVoltage(

involts)

ModelMEDICI

VDS = 0.05 V

M1 = 4.77 V

M2 = 4.1 V

NA = 6 x 1016 cm-3

0.1 0.2 0.4 0.6 0.8 1.0


0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

ThresholdVoltage(

involts)

ModelMEDICI

VDS = 0.05 V

M1 = 4.77 V

M2 = 4.1 V

NA = 6 x 1016 cm-3

Figure 6(b).


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25

ModelMEDICI

VDS = 0.05 V

L = 0.5 m

L1/L2 = 2/3

L1/L2 = 1/4

0 0.2 0.4 0.6 0.8 1.0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0

0.9

1.0

ThresholdVolta

ge(involts)

Gate Workfunction Difference (in volts)

ModelMEDICIModelMEDICI

VDS = 0.05 V

L = 0.5 m

L1/L2 = 2/3

L1/L2 = 1/4

0 0.2 0.4 0.6 0.8 1.0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0

0.9

1.0

ThresholdVolta

ge(involts)

Gate Workfunction Difference (in volts)

Figure 7.


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Bio-Data of Dr. M. Jagadesh Kumar(MS # 1872 R)

Dr. M. Jagadesh Kumar (SM'99) was born in Mamidala, Nalgonda district, Andhra

Pradesh. He received the M.S. and Ph.D degrees both in Electrical Engineering from the

Indian Institute of Technology, Madras. From 1991 to 1994, he did his Post-doctoral

research in modeling and processing of high speed bipolar transistors with Prof. David J.

Roulston in Department of Electrical and Computer Engineering, University of Waterloo,

Waterloo, Ontario, Canada. During his stay at Waterloo, he also collaborated with Prof.

Savvas G. Chamberlain on amorphous silicon TFTs. From July 1994 to December 1995, he

first taught in the Department of Electronics and Electrical Communication Engineering,

Indian Institute of Technology, Kharagpur and later moved to the Department of Electrical

Engineering, Indian Institute of Technology, Delhi where he was made an Associate

Professor in July 1997. More than once, his teaching has been rated as outstanding by the

Faculty Appraisal Committee, IIT Delhi. His research interests are in VLSI Device

modeling and Simulation, IC Technology and Power Semiconductor Devices.

Dr. Kumar is a Fellow of Institute of Electronics and Telecommunication Engineers(IETE) ,

India.

Bio of Anurag Chaudhry

Anurag Chaudhry received his B.E. degree with distinction in electronics and communication

engineering from Birla Institute of Technology, Mesra, India, in 1999. He is currently

working towards his M.S. degree at Indian Institute of Technology Delhi.

From 1999 to 2001, he worked as a Design Engineer in the FPGA group with ST

Microelectronics Ltd., NOIDA, India. His work primarily involved proposing logic blockarchitecture for an FPGA. His research interests include modeling and simulation of novel

device structures on silicon-on-insulator (SOI) MOSFETs.

Two-Dimensional Analytical Modeling of Fully Depleted Dual-Material Gate (DMG) SOI MOSFET and...

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