Technical University Hamburg-Harburg Winter Semester 2004-2005Department of MicroelectronicsMaster’s Program Microelectronics and Microsystems

Course: Circuit Design Laboratory- Part 1: Analog DesignProf. Dr.-Ing. Wolfgang Krautschneider

Instructor: M.Sc. Paola Vega-Castillo

Tutorial 4: Layout and Verification of the OP-AMP Design

4.1 Introduction

The most important aspect of layout is the minimization of area. The price of ASICs depends both on the selected process and on the layout area. Therefore, designers always try to create a layout of minimum dimensions. In addition to the area consumption, matching effects and parasitic capacitances should be considered.

For the layout of your operational amplifier, first consider an arrangement of the components (floorplan) that requires minimum area. Figure 1 is an example of a possible floorplan for the OP-AMP.

Set the width of the power rails to 10µm and layout them using Metal1. Do not forget to include metal1 input and output pins in the design. The value of the compensation capacitor is determined from both its area and perimeter. Use the value you have in the schematic and layout the capacitor using the layers POLY1 and POLY2 laying one above the other.

4.2 Layout-XL and DLE

Cadence offers assistance for the layout generation by means of the DEVICE level editor (DLE). The DLE generates the layouts of the transistors and resistances (not the capacitances). In addition to this, it supports the wiring of the individual elements.

To start with the layout, follow the next steps:

a) Create the layout view of your operational amplifier.

Figure 1: Possible floorplan for the OP-AMP

Power Rail vdda

Power Rail vssa

inp

inn

idc50u

M4

M5/M6

M3

M7

M8

M0/M1 M2

M9

C

out

b) Start the DLE clicking on LAYOUT/Tools/Layout XL. The layout and the schematics windows are now available.

c) Select LAYOUT/create/Pick from Schematic in the layout window.

d) In the Schematic window, mark all the elements and change to the layout window.

e) Click on the position where the elements should be placed. If you see no elements placed, press Shift-F to make all display Levels visible. If you need to redraw the window contents, press Crtl-r.

f) Click on LAYOUT/Connectivity/Show Incomplete Nets to display all unconnected nets. The appearing window can be closed with OK. If a transistor in the layout window is marked, then it appears also in the schematic window as selected.

g) Complete the connections between the circuit elements and include the input and output pins.

Remind to frequently run the design rule check. Your layout should be free of DRC errors to continue with the next steps of the design flow.

4.3 Extraction and LVS

Extraction and Layout vrs Schematic (LVS) check have to be carried out for preparing the design for layout verification. In this handout the extraction, LVS check and the procedure for postlayout simulation are explained.

4.4.1 Extraction

The individual components of your design are extracted from the layout. During the extraction, the extraction tool infers what kind of components are present in the layout. These are stored in the view " extracted ". To extract your design, follow the next instructions:

a) Before you start the CDFII Environmnet, please set the environment variable in the Unix-Terminal-window:

setenv CDS_Netlisting_Mode Analog

b) Open the layout of the OP-AMP and perform the Design Rule Check to make sure that the layout does not contain any errors.

c) Open the extraction window with LAYOUT/Verify/Extract... To start the extraction click OK.

d) If the extraction was succesfull, the message “Total Errors Found: 0” prompts in the CIW.

4.4.2 LVS

LVS means layout versus schematic. In this verification step the netlist of the schematic view is compared with the netlist, which was produced by the extraction. If layout and schematic correspond, then a post layout simulation can be started. To run this verification, follow the next instructions:

a) Before you start the LVS check, open the schematic of the OP and erase all voltage and current sources.

b) Open the extracted view. Click on LAYOUT/Verify/LVS....

c) Fill out the fields for the schematic and extracted view. This can be done by using the browse button. In the column Schematic enter schematic as the selected view and in the column Extracted enter the extracted as the selected view.

d) Make sure that the Rules File is divaLVS.rul and the Rules Library is TECH_CYE. Start the LVS by clicking on Run.

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e) After finishing the LVS you can get information about the results of the LVS run by clicking Output in the LVS setup window.

f) If the message "LVS failed" appears, you can analyze the error by opening the logfile and/or output file. If the message "LVS succeeded" appears, have a look at the output file. If it contains the message "the net-lists match", the layout correctly describes the circuit in the schematic. In that case the LVS is finished, otherwise the error must be eliminated and a new LVS run should be started.

4.4 Postlayout Simulation

The layout can be verified by means of postlayout simulation. After executing the Extraction and LVS in the last part, the actual post layout simulation can be performed. With simulation, the influence of the parasitic elements in the design performance can be estimated. If the postlayout simulation still fulfills the specifications, then the layout can be submitted for production. Otherwise it must be redesigned.

4.5.1. Settings for postlayout simulation

a) In order to run a postlayout simulation, you must first extract the parasitic capacitances. For this, extract your design again, but this time set the switch by clicking Set Switches to capall.

b) Create a new cell.

c) In this cell’s schematic, insert the OP-AMP symbol and all the necessary voltage/current supplies.

d) Execute any analog simulation, in order to test whether the wiring of the OPs is correct or not.

e) For the postlayout simulation, the parasitic capacitances must be taken into account. For that, click on Affirma/Setup/Environment.... to open the Environment Options window of the simulator.

f) In the option Switch View List, enter the view extracted directly behind spectre and press OK.

g) Create a new netlist with Affirma/Simulation/Netlist/Create Raw. Do the parasitic elements appear in the new netlist?

h) Start the simulation as usual. Check by means of different simulations whether the specification of the OP-AMP’s are still fulfilled or not.

4.5 Protocoll

a) Print the final layout as a Postscript file.

b) Have a look at the netlists of the schematic and extracted views. How large is the extracted poly capacitance ?

c) Have a look at the elements of the extracted view and explain the parasitic capacitances.

d) Print the netlist of the postlayout simulation

e) Verify that the post layout simulation of the extrated View still fullfills the specification. Simulate and print the most important characteristics of the OP-AMP.

f) Explain the difference between both simulations.

g) How large is your layout’s area? Are improvements still possible?

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