Tunneling Devices

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Tunneling Devices Dane Wheeler April 19, 2005 EE666 – Advanced Semiconductor Devices

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EE666 – Advanced Semiconductor Devices. Tunneling Devices. Dane Wheeler April 19, 2005. EE666 – Advanced Semiconductor Devices. Tunneling Devices. Dane Wheeler April 19, 2005. Outline. Motivation Band-to-Band Tunneling Device Proposals Fabrication Techniques Notre Dame Devices - PowerPoint PPT Presentation

Transcript of Tunneling Devices

Page 1: Tunneling Devices

Tunneling DevicesDane WheelerApril 19, 2005

EE666 – Advanced Semiconductor Devices

Page 2: Tunneling Devices

Tunneling DevicesDane WheelerApril 19, 2005

EE666 – Advanced Semiconductor Devices

Page 3: Tunneling Devices

OutlineOutline• MotivationMotivation• Band-to-Band TunnelingBand-to-Band Tunneling• Device ProposalsDevice Proposals• Fabrication TechniquesFabrication Techniques• Notre Dame DevicesNotre Dame Devices• ConclusionsConclusions

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MotivationMotivation• ScalingScaling: some proposed tunneling field : some proposed tunneling field

effect transistor (TFET) designs do not effect transistor (TFET) designs do not suffer from short channel effectssuffer from short channel effects

• Power Dissipation:Power Dissipation: TFETs can beat the 60 TFETs can beat the 60 mV/decade sub-threshold swing of mV/decade sub-threshold swing of MOSFETsMOSFETs

• Design Flexibility:Design Flexibility: Circuits can be made Circuits can be made with fewer deviceswith fewer devices

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Obligatory Moore’s Law Obligatory Moore’s Law ReferenceReference

http://www.intel.com/research/silicon/mooreslaw.htmhttp://www.intel.com/research/silicon/mooreslaw.htm

human brain in 2012?human brain in 2012?

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What’s so great about a What’s so great about a tunneling device?tunneling device?• Lower sub-threshold swing can allow for Lower sub-threshold swing can allow for

lower operating voltages to be usedlower operating voltages to be used• Negative differential resistance (NDR) Negative differential resistance (NDR)

properties can be exploited to create properties can be exploited to create simpler designs for bi-stable circuits, simpler designs for bi-stable circuits, differential comparators, oscillators, etc.differential comparators, oscillators, etc.

• Leads to chips that consume less powerLeads to chips that consume less power

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TunnelingTunneling• Tunneling is a quantum mechanical Tunneling is a quantum mechanical

phenomenon with no analog in classical phenomenon with no analog in classical physicsphysics

• Occurs when an electron passes through Occurs when an electron passes through a potential barrier without having enough a potential barrier without having enough energy to do soenergy to do so

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(Esaki) Tunnel Diode (TD)(Esaki) Tunnel Diode (TD)• Simplest tunneling deviceSimplest tunneling device• Heavily-doped pn junctionHeavily-doped pn junction

– Leads to overlap of conduction and valence Leads to overlap of conduction and valence bandsbands

• Carriers are able to tunnel inter-bandCarriers are able to tunnel inter-band• Tunneling goes exponentially with Tunneling goes exponentially with

tunneling distancetunneling distance– Requires junction to be abruptRequires junction to be abrupt

EC

EVEF

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Band-to-Band Tunneling in a Band-to-Band Tunneling in a Tunnel DiodeTunnel Diode

EC

EVEF

I

V

(a)

(b)

(c)

(d)

(e)

(a) (b) (c) (d) (e)

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Figures of MeritFigures of Merit

I

V

Peak current100 kA/cm2

Peak-to-Valley Ratio (PVR)

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Bi-stable ConfigurationBi-stable Configuration

I

V

D2

D1

X

V

X1 X2

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TD Differential ComparatorTD Differential Comparator

M1 M2

ITAIL

VEE

VCC

M4M3

VOUT

RL

I1 I2

RL

VOUT

CK

VIN VIN

D1

D3

D2

D4X

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Direct vs. Indirect TunnelingDirect vs. Indirect Tunneling

DirectDirect IndirectIndirect

Indirect materials require phonons to tunnel, thus Indirect materials require phonons to tunnel, thus reducing the probability of a tunneling eventreducing the probability of a tunneling event

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Tunnel Current ExpressionsTunnel Current Expressions

EE

eFEmT tG 2exp

22exp

2/32/1*

GEm

eFE*3

24

)3

*24exp(

24*

2/3

2/122

2/13

qEm

EVmqJ g

g

at

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Lateral TFETLateral TFET• Proposed by our own Qin ZhangProposed by our own Qin Zhang• Can theoretically beat 60 mV/decade sub-Can theoretically beat 60 mV/decade sub-

threshold swingthreshold swing

S D

G

oxn+ Sip+ Si

xy

BOXL W

tox

tSi

12

1ln10( )eff

eff gs gs

dV B dSV dV dV

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Lateral TFETLateral TFET

Off State On State

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Another Lateral TFETAnother Lateral TFET• Proposed by A. Zaslavsky in SOI, Proposed by A. Zaslavsky in SOI,

although original idea from Shockleyalthough original idea from Shockley• Gate placed on top of depletion regionGate placed on top of depletion region

Si

OXP+

GATEN+

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More about AZ TFETMore about AZ TFET

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Double Lateral TFETDouble Lateral TFET• Acts as back-to-back TD pair at 0 gate Acts as back-to-back TD pair at 0 gate

biasbias• Gate bias of either polarity will break Gate bias of either polarity will break

tunneling conditiontunneling condition

Si

OXP+

GATEN+ N+

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Fabrication TechniquesFabrication Techniques• As mentioned earlier, heavily-doped, As mentioned earlier, heavily-doped,

abrupt junctions are neededabrupt junctions are needed• Can be obtained using several different Can be obtained using several different

methodsmethods– Ion implantationIon implantation– Rapid thermal diffusionRapid thermal diffusion– Molecular beam epitaxyMolecular beam epitaxy– Laser diffusionLaser diffusion

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Doping by Rapid Thermal Doping by Rapid Thermal ProcessorProcessor

Approach:Approach:

Rapid thermal diffusionRapid thermal diffusion

Spin-on diffusantsSpin-on diffusants

100 mm wafers100 mm wafers

IC-compatible IC-compatible processesprocesses

Modular Process TechnologyModular Process TechnologyRTP-600SRTP-600S

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Proximity Rapid Thermal Proximity Rapid Thermal DiffusionDiffusion

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Rapid Thermal DiffusionRapid Thermal Diffusion

10-17

10-16

10-15

10-14

10-13

10-12

D (c

m-2

/s)

Temperature (º C)800 900 1000 1100

Athena defaults

Gaussian peak

040712DPfit.QCP

Phosphorus

D = D.0*exp[-D.E/(kT)]

ERFC tail

Gaussian tail

Transient-enhanced diffusion effects dominate, Transient-enhanced diffusion effects dominate, increasing diffusivity of dopantsincreasing diffusivity of dopants

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Ion ImplantationIon Implantation

1019

1020

1021

1022

0 0.2 0.4 0.6 0.8 1

Act

ive

Con

cent

ratio

n (c

m-3

)

Horizontal Position (µm)

phos.

boron

net

1 nm/decadeat junction

B: 1.6e15 cm-2anneal:800º C spike

P: 1e15 cm-2

040915lateraldop01.qpc

1 keV implants:

cut line

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Simulated Built-in FieldSimulated Built-in Field

-5.0 105

0.0

5.0 105

1.0 106

1.5 106

2.0 106

2.5 106

3.0 106

0 0.2 0.4 0.6 0.8 1

Ele

ctric

Fie

ld (V

/cm

)

Horizontal Position (µm)

averageE-field:2.41e6 V/cm

040915efield01.qpc

calculatedpeak tunnelcurrent:20.2 kA/cm2

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Simulated Band DiagramSimulated Band Diagram

-1.5

-1

-0.5

0

0.5

1

1.5

0 0.2 0.4 0.6 0.8 1

Ene

rgy

(eV

)

Horizontal Position (µm)

EC

EV

tunnelingdistance:6 nm

040915band01.qpc

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First TDs from Rapid Thermal First TDs from Rapid Thermal DiffusionDiffusion

0

2 10-9

4 10-9

6 10-9

8 10-9

1 10-8

0 0.2 0.4 0.6 0.8 1

Temperature Dependence

Cur

rent

(A)

Wafer: W22Voltage (V)

25° C

-25° C

°

0° C

device area:150 µm diameter

Peak-to-Valley Current Ratio: 1.22

Peak Current Density: 30.85 µA/cm2

n+ Si, P-diffusionp+ Si, B-diffusion

n+ Si substrate, P-doped

Al

2a0716

n+ Si, P-diffusionp+ Si, B-diffusion

n+ Si substrate, P-doped

Al

2a0716

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TDs with Oxide Window TDs with Oxide Window ProcessProcess

-0.2

-0.1

0

0.1

0.2

0.3

-0.2 0 0.2 0.4 0.6 0.8

Cur

rent

(mA

)

Voltage (V)

Jp = 266 A/cm2

PVR = 2.15

High resistivity substrate1-5 k cm

Y140, (5,3)(2,1), 4 x 16 m2

First demonstrationof tunnel diodes

onhigh resistivity1 – 5 k cmsubstrates

Enables microwavecharacterization

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ConclusionsConclusions• Tunnel diodes are expected to add Tunnel diodes are expected to add

another node in the roadanother node in the road• Three-terminal tunnel devices could add Three-terminal tunnel devices could add

several nodes at the end of CMOS-scalingseveral nodes at the end of CMOS-scaling• Challenges facing TFETs are more Challenges facing TFETs are more

practical than theoreticalpractical than theoretical– Lithography, SOI process optimizationLithography, SOI process optimization