TUG '07

29
HOLLYWOOD SHERATON UNIVERSAL HOTEL APRIL 23-25

description

Teradyne Annual Conference Guide

Transcript of TUG '07

Page 1: TUG '07

Teradyne, Inc. 600 Riverpark Drive North Reading, MA 01864 978-370-2700

www.teradyne.com

Teradyne® is a registered trademark of Teradyne, Inc.All brands and product names are trademarks or registered trademarks of Teradyne, Inc., including its subsidiaries.

©2007 Teradyne, Inc. • All rights reserved.

B e c a u s e T e s t i n g M a t t e r s

HOLLYWOODSHERATON UNIVERSAL HOTEL

APRIL 23-25

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HOLLYWOOD•APRIL 23-25

TUG 2007 STEERING COMMITTEE

ChairKevin Walt, Broadcom

Vice ChairJohnny Steck, Texas Instruments

SecretaryDonna McNeill, Teradyne, Inc.

Treasurer/RegistrarNancy Wenstrom, Teradyne, Inc.

ASSEMBLY TEST

Mil/AeroTodd Bigham, U.S. Air ForceTeresa Lopes, Teradyne, Inc

SEMICONDUCTOR TEST

DigitalTom Munns, Freescale SemiconductorMike Patnode, Teradyne, Inc.

Mixed SignalRainer Fink, Texas A & MZak Zakour, Teradyne, Inc.

Power Management/AutomotiveTim McCoy, Texas InstrumentsChris Quaranta, Teradyne, Inc

Production Integration & HW/SW InterfaceLarry Grieve, Freescale SemiconductorMarcel Jussaume, Teradyne, Inc.

RF WirelessMike Bellanger, NXP SemiconductorsGreg Renk, Teradyne, Inc.

Semiconductor Delegates-at-LargeJessica Faulkner, Teradyne, Inc.Zoltan Goldschmidt, Teradyne, Inc.Karin Mogler, Teradyne, Inc.Bill Wyckoff, Teradyne, Inc.

Daily Session Grids ..............................6

Semiconductor Test Program

• Digital . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

• Mixed Signal . . . . . . . . . . . . . . . . . . . . . . . . .21

• Power Management/Automotive . . . . . .28

• Product Integration &

Hardware/Software Interface . . . . . . . . . .34

• RF Wireless . . . . . . . . . . . . . . . . . . . . . . . . . .42

Assembly Test Program

• Mil/Aero . . . . . . . . . . . . . . . . . . . . . . . .48

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Letter from the Chairman

Dear TUG 2007 Attendees –

Welcome to the Sheraton Universal Hotel, here in beautiful Southern California (my home town) As you are here, you

have accepted the challenge to take on this “daring adventure”. The Teradyne Users Group Conference has continued

for over 24 years with the “best in test” sharing the tools and methods that work in the never ending quest to reduce

the cost of test and deliver the best possible products to the consumer.

The 2006-2007 Steering Committee has put together 3 days of technical papers, presentations and tutorials by the

brightest engineers in test today. TUG continues to be the place where the test community gathers to share new tech-

niques, discuss new challenges and breakthroughs in the use of Teradyne equipment, as well as discussing the direction

and latest trends in the industry.

I have been in the test industry since 1983 and consider myself lucky to be working with a dedicated and professional

group of elected industry “users” as well as Teradyne employees. If you are interested in becoming a part of the

Steering Committee, contact anyone on the current committee and submit a nomination! We will start working on

TUG 2008 soon.

Please go now and attend sessions, investigate, share and give feedback to Teradyne. Meet new people, establish

valuable relationships, learn something new from your peers. TUG’s goal is to provide each of you with a technical

experience that will benefit your job, career, product line and your industry. Remember to take the knowledge you gain

here and share it with your fellow engineers.

Thank you again for your participation and for being a member of the Teradyne Users Group.

Sincerely,

Kevin Walt2007 TUG Chair

Principal EngineerBroadcom

since been a focal point for Zero Defect programs, driving innova-tive methods to further improve the quality of Freescale's integrat-ed circuits.

In his current role, Mr. Keshvari is responsible for product andtest engineering for all microcontrollers for the automotive, con-sumer and industrial markets. Freescale microcontroller quality lev-els have improved dramatically during Keivan’s tenure in this posi-tion. The company’s latest flagship 32-bit microcontroller forengine management applications shipped more than one millionunits without a customer return.

Mr. Keshvari holds a Bachelor’s degree in Computer Science, aswell as a Master's of Business Administration degree.

Ahmad Abde-YazdaniDirector of Test EngineeringAutomotive Products WorldwideInfineon TechnologiesMunich, Germany

Mr. Ahmad Abde-Yazdani has been the Director of TestEngineering for Automotive Products Worldwide at InfineonTechnologies since 2000. Before that he was at Siemens Companyfor 14 years working as the Department Leader in TestEngineering, and as a test engineer for Analog, Mixed Signal, andMicroprocessor devices. He also worked with the UniversityWuppertal from 1985-1986 on scientific investigation in Digital fil-tering methods.

Mr. Abde-Yazdani has a strong background in test engineer-ing, from his days working at the University Wuppertal, to hisexperience at Siemens where he held several positions from test-ing microprocessor devices and mixed-signal devices beforebecoming the department leader for test engineering.

Mr. Abde-Yazdani holds a Master's degree inElectronic/Broadcasting from University Wuppertal in Germany.

For the keynote presentation, Mr. Keshvari will open thekeynote address discussing Freescale’s involvement in the trans-portation industry, the history of ICs in the automotive industry,current and future applications, and why zero defects are criticaltoday.

Mr. Abde-Yazdani will then discuss Infineon’s involvement inthe transportation industry: the technical challenges that zerodefects have on the manufacturing and design process; the histo-ry of IC's application complexity in the automotive industry; whatwill the next generation of products bring; and, what the chal-lenge is to the ATE Industry.

Please join us.

If you are reading this,

you have accepted the challenge

to participate in TUG 2007

License to Test. You are now a

part of the longest running Users

Group conference in the ATE

Industry. Continue reading for

more information...

WHO IS ATTENDING

The Annual Teradyne Users Group Conference is open to alllicensed users of Teradyne’s test systems and software products.

KEYNOTE ADDRESS TUG 2007

We are honored this year to have two keynote presenters speak-ing to us at TUG 2007. Both are leaders in their fields.

Keivan KeshvariDirector, Product and Test EngineeringMicrocontroller DivisionTransportation & Standard Products Group Freescale Semiconductor Inc. Austin, Texas

Mr. Keshvari has held various engineering and management posi-tions within Freescale (formerly Motorola Semiconductor ProductsSector) during the past 18 years and has a strong background insemiconductor test and manufacturing. He was one of the keydrivers of Motorola’s original Six Sigma implementation and has

CONFERENCE INFORMATION

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Advint, LLC

Aeroflex

AMI Semiconductor

Analog Devices

Anteon Corporation

Applied Wave Research

ATI Research

BAE Systems

Boca Test

Broadcom

Circuit Check

CSR

DARA

DOD

Eagle Systems

Everett Charles Technologies

Freescale Semiconductor

Galaxy SemiconductorSolutions

Gennum Corporation

Hewlett Packard

IBM Canada

Infineon Technologies

Infineon Technologies Austria

Infineon Technologies AsiaPacific

Integrated Systems Test

Intel

Intersil

Iowa State University

Lockheed Martin

Marvell Semiconductor

Medtronic

Mfg Vision Ltd

Microchip Technology

Micron Technology

Micronas GmbH

Mindscale Consulting

National Semiconductor

Naval Surface Warfare Center

Naval Undersea WarfareCenter

Philips Semiconductors

Philips Styria Austria

Qualcomm

Raytheon

Raytheon Missile Systems

RF Micro Devices

Royal NL Navy

Salland Engineering

Samsung Electronics

Siemens VDO

SigmaTel

Sitel Semiconductor

STMicroelectronics

Syndetix Corp.

Tessolve Services

Test Advantage

Test Spectrum

Texas A&M University

Texas Instruments

The Boeing Company

The MathWorks, Inc.

U.K. MOD

U.S. Air Force

U.S. Army

VXI Technology, Inc.

Wolfson Microelectronics

Zarlink Semiconductor

TUG 2006 Attendees — Jacksonville, Florida

CONFERENCE INFORMATION

CAR RENTAL

If anyone wants to rent a car while at the Sheraton Universal, thereis an Enterprise desk at the hotel.

TERADYNE PARTY ON MONDAY NIGHT!

Join us for a tour of Universal Studios and a party at the UniversalStudios Theme Park. This year Teradyne will host their annual TUGparty on Monday, April 23, from 6:00-9:00 PM. Join us at UniversalStudios where you can experience the behind-the-scenes action, aswell as re-live your favorite movie sets such as “Jurassic Park”, “BackDraft” and “Revenge of the Mummy”. Shuttles will depart the con-vention area of the hotel (check with the TUG registration desk for pickup location) to take you on a studio tour ending at Studio Center, anarea specially reserved for TUG. Enjoy food and beverage from any ofthe vending areas such as Panda Wok, Jurassic Cafe, and Ben & Jerry's,as you explore the stage sets, relax and listen to the music, or challengeothers in the video game room. Shuttles are available throughout theevening for your return trip, and should you decide to extend yourevening, hotel shuttles will be available from the City Walk area.

SURVIVOR PARTY

For those staying over Wednesday, April 25th, TUG will be hostinga “Survivor” Party at the hotel.

EVALUATION FORMS

Everyone will be given evaluation forms before every session. It isimportant that these forms are completed and put into the basketslocated at the back of every room. Awards are given to the BestPapers based on these forms.

Overall TUG 2007 Evaluation Forms will be distributed with yourTUG materials at registration. Everyone who completes and returnsthe Overall Evaluation Form by lunchtime will be eligible for a prizeat daily drawings each lunch hour. These forms are especiallyimportant as the TUG Steering Committee reviews your commentsand takes them into consideration when planning the TUG 2008Program. As always, feedback regarding meeting content, logisticsand location will be appreciated.

TUG 2008 STEERING COMMITTEE NOMINATIONS

During this 2007 Conference, a new TUG Chairman will be elect-ed, along with committee members who will plan TUG 2008. Ifyou would like to nominate yourself or a colleague for the SteeringCommittee, please go to the Registration Desk for the forms.NOTE: Elections will be held on Tuesday afternoon, so please sub-mit your nominations by 12:00 PM on Tuesday.

NEW THIS YEAR!

We are offering Seminars on Sunday to those who are continu-ously searching for knowledge and don’t want to wait until Monday.

Semiconductor Customer Forum Discussion Attend the Engineering Update by Mike Malone, Teradyne VP ofEngineering and hear what Teradyne is planning for the future.Immediately following, representatives from Teradyne’s Marketing,Engineering and Customer Support organizations will be there to answer questions, listen to concerns, and make note of your inputs.

BACK THIS YEAR

Vendor Fair The TUG 2007 Steering Committee is pleased to provide a forumto discuss breakthrough technologies that meet a broad range oftest challenges. Vendors will highlight key products and servicesthat interface with Teradyne semiconductor test systems. TheVendor Fair begins Tuesday afternoon as part of the RoundtableSession. TUG attendees are invited to enjoy refreshments while par-ticipating in this informal vendor/customer exchange. A descriptionof each company can be found later in the Program Book.

The following companies will be exhibiting this year:• Dynamic Test Solutions, Inc.• GSI Group Inc.• Everett Charles Technologies• Gorilla Circuits, Inc.• HCL America, Inc.• inTEST Corporation• Mentor Graphics Corporation• Pintail Technologies• Salland Engineering (Europe) BV• Teradyne – Test Assistance Group (TAG)• Test Advantage

REGISTRATION FEES AND PAYMENT

The fee for TUG 2007 registration on-site (no prior registration) is$300.00 per day.

TUG accepts U.S. currency and personal, travelers or companychecks. Please make checks payable to “Teradyne Users Group”.You may also pay on-site by American Express, MasterCard orVISA. (Please note: We cannot accept Diners Club orDiscover card, nor can we accept company or governmentPurchase Orders).

TUG REGISTRATION DESK IS OPEN:

Monday, April 23, 2007 6:00 AM – 5:00 PMTuesday, April 24, 2007 7:00 AM – 5:00 PMWednesday, April 25, 2007 7:30 AM – 12:00 PM

LOCAL ATTRACTION DISCOUNTS

Please check with the hotel concierge for any local attraction dis-counts that may apply for Teradyne Users and Guests.

SPECIAL NEEDS

Both TUG and the Sheraton Universal Hotel are ADA compliantand will accommodate special needs, as well as dietary require-ments. If you do have special dietary or other ADA needs, we willaccommodate you.

HOTEL INFORMATION

Enjoy the warmth of smiling faces and the California sun at theSheraton Universal Hotel. The hotel has over 30,000 square feetof versatile meeting space and it will provide the atmosphere ofelegance and professionalism our attendees expect. The hotel'scentral location makes it easy to leave the premises when not in atechnical session and take advantage of free time.

Complimentary tram rides to Universal Studios Hollywood andUniversal Citywalk save you time and keep you relaxed.

Find refreshment in the heated outdoor swimming pool. Maketime for conversation in the outdoor whirlpool. Or re-energize atthe fitness center, open all day and night.

After sessions, catch up with friends and stroll over to MelroseAvenue, Hollywood, Beverly Hills, and downtown Los Angeles. Letthe good times linger late into the night as you gather togetherfor refreshments at the Baja Bar.

Share amazing views of Universal Studios and find all the com-forts of home.

Other Services at the hotel include:• Business Center• Wake up service• Babysitting service• Laundry Service

PARKING

For those attendees driving in for the day to attend sessions, parking will be offered at a special rate of $8.00 for the day forself-parking only. Overnight parking is $16.00 for self-parking and$21.00 for valet parking with in and out privileges.

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BREAK BREAK

GROUP

BREAKFAST BREAKFAST

WELCOME WELCOME

KEYNOTE I KEYNOTE I

LUNCH LUNCH

1/A Pattern Matching on the Tiger™Jason Laderman, Intel Corp.

1/B Using the HexVS as an Independent DVMData Acquisition Instrument Patrice Ducharm, Roxan Lemire, Michel Paradis,IBM; George. Simbles, Teradyne

DIGITAL

The Man with the Innovative Test Technique

1/C KeepAlive™: Then and Now Way Kyi, Teradyne

1/A Jitter Testing with Dig_Cap Joyce Ng, Kevin Walt, David Yin, Broadcom

1/B What Is and How to Use Learn Mode Michael Cavallini, Brent Herling, Kent Magnuson,Teradyne

MIXED SIGNAL

Q's Lab

1/C FLEX™ DSSC vs. ADB Bus Kevin Cheng, Jerry Hsieh, Teradyne

1/A Reduce Program Development Time for theAutomotive Market on the FLEX™ Dominique Le Roux, Teradyne

1/B VBT or POP? How to Decide theImplementation of a Mixed-Signal Test Fast Cristian Cesarini, Filomena Ricci Teradyne

POWER MANAGEMENT/ AUTOMOTIVE

Accelerating Program Developmentand Characterization

1/C Better Programming on the FLEX™ Testerfor Easy Debug and Easy Switch fromCharacterization to Production Test Elie Trognon, Freescale Semiconductor

For Your SB6G Only

2/A A User Characterization of the SB6G Instrument Patrice Ducharme, Roxan Lemire, Dany Minier,Doris Viens, IBM; Fady Bishay, Mike Patnode,George Simbles, Teradyne

2/B Characterizing High-Speed Parallel Buseswith the SB6G and Sub-MOSC Timing Erik Lusis, IBM; Fady Bishay, Doug Mainz, Teradyne

2/C Testing High-Speed Serial Buses through aGeneralized Template for the UltraFLEX™ SB6GJoe DeSimone, Freescale Semiconductor; Bill Davis,Teradyne

Q's Lab

2/A Advanced Measurement Methods ofHysteresis Featured in Mixed-Signal IC Chips Weishu Wu, Texas Instruments

2/B The Implementation of Fourier eXtendedTransform (FXT) in IG-XL™ Edmond Tan, Shu Xia, Teradyne

2/C Understanding IG-XL™ DSP Enhancements Hmayak Dravatshyan, Scott Therrien, Teradyne

Accelerating Program Developmentand Characterization

2/A My Pattern is Running - Can I Still Debug? Lorenzo Simonini, Elisa Woo, Teradyne

2/B Using the PLMeter as a Debug Resource Krista Bertsch, Teradyne

2/C Sync Panel, Uncovering Issues Walter Oldham, Derek Sam, Teradyne

BREAK BREAK

3/A High-Speed Loop-Back Test Solution forSerDes Products Using SB6GPatrice Ducharme, Dany Minier, Doris Viens, IBM;David Keezer, Georgia Institute of Technology

3/B SATA Testing with SB6G Zubir Ebrahim, Teradyne

3/C High-Definition Multimedia Interface(HDMI) Receiver Characterization and TestTechniques on the UltraFLEX™ Peter Huber, Edward Seng, Teradyne

3/D HyperTransport™ 3.0 Link Characterizationwith SB6G on the UltraFLEX™James Yeh, AMD; Fady Bishay, Shawn Sullivan,Teradyne

Protocol, High-Speed Protocol

3/A Get the Best of your High-Density PMU DirkJan Stuij, Salland Engineering; Francois Deun,Teradyne

3/B AC Characterization of BBAC and POOL2Signal Sources Don Jussaume, Analog Devices

3/C Automated Test Program Conversion K. Padma Priya, Vinai Kumar Singh, Teradyne/HCLTechnologies

3/D Understanding DCTime Larry Lovell, Teradyne

Tools

3/A Faster Ramps and Higher Yields in thePursuit of 0 DPM Richard Ackerman, Mentor Graphics (Vendor)

3/B Force Fail Tool, Accelerating ProductionRelease Walter Oldham, Teradyne

3/C Relays — Conquering the Test Engineer'sNemesis Paul Nelson, Elisa Woo, Teradyne

3/D Lowering DPPM without Increasing Burn-inor Test Time Jeff Bibbee for OptimalTest

Test Quality: Ready to Ramp?

1/A Use Scripting to Get the Most out of DataAnalysis Antoine Megens, Salland Engineering

1/B Data Analysis in Real-time Mode Martijn van der Vlag, Salland Engineering

PRODUCTION INTEGRATION & HW/SW INTERFACE

Data Analysis

1/C Yield Monitor Tool for IG-XL™ Platforms Jimmy Chan, Yeng Chee Liew, Broadcom;Nagappan Nachiappan, Jeffrey Tan, Teradyne

Tester Integration A

2/A Integrating the FLEX™ Test System into aWell-Established Test Floor Chad Bray, Trevor Dixon, Texas Instruments

2/B Planning and Logistics: Converting aComplex SoC Catalyst™ to FLEX™ in Asia withoutLeaving Europe John Tatchell, CSR; Ian Beck, Teradyne

2/C Working with OpenFLEX™ — A Customer’sExperience of Developing Test Solutionsthrough Teradyne’s OpenFLEX Office Omar Biabani, Sten Peeters, Teradyne

3/A DIB Design Sanity Check Using CircuitSimulation Software Ambika Krishnamoorthy, Swetha Thiagarajan, IntelCorp; Tom Chambers, Chris Paull, Teradyne

3/B Automating Schematic Verification forBetter Efficiency and Better Chance for First-Pass Success David Baird, Freescale Semiconductor

3/C Self-Documenting PIB Diagnostics Chad Bray, Trevor Dixon, Texas Instruments

3/D A Chip that Avoids Mechanical Relays on aDIB Giuseppe Amelio, Francesco Cantini, Moreno Lupi,Francesco Picchi, Microtest

DIB Design Verification

1/A Introducing the Port Expander Instrument Glenn Burnham, Teradyne

1/B Improving the Level Accuracy of Gen4 MWHardware David DiBona, Teradyne

RF WIRELESS

Instrumentation

1/C The Implementation of GSM/EDGE Sourceand Receive Library in IG-XL™ Ronald Burke, Helen Chen, Peter Chen, GregDionne, Shu Xia, Zhe Xu, Teradyne

Code Examples

2/A Migrating a Final Test RF SoC from Single-Site Catalyst to Quad-Site FLEX™ Kim Gundersen, AMI Semiconductor

2/B On-the-Fly Statistics with IG-XL™Jos Driessen, NXP Semiconductors

3/A Defining Inductance in Contactors Ryan Satrom , Everett Charles (Vendor)

3/B RF Connectors and Material: APerformance Comparison Martin Dresler, Wolfgang Steger, Teradyne

3/C Design Example for a Generic RF DIB andCustom Daughter BoardKN Chui, Corad; Charles Kao, Teradyne

3/D RF Debugging Techniques for VolumeProduction Peter Higgins, Teradyne

Board/Material Considerations

1/A Using Interchangeable Virtual Instrument(IVI) to Increase Test Development EfficiencySameer Bivalkar, Teradyne

1/B Cost Benefit Analysis for Using ATLAS Brandon Beaulieu, Jim Danscuk, U.S. AirForce/Tinker

ASSEMBLY TESTMIL/AERO

Test Development

1/C Programmable Test Boards for AssemblyTPS Troubleshooting Luis Villalta, Teradyne

Programming in C #

2/A Programming in C # Workshop (90 Minutes)

3/A Hands-on Programming the Bi4-SeriesWorkshop

TERADYNE PARTY TERADYNE PARTY

10:30 – 11:00

11:00 – 11:30

10:30 – 12:00

11:30 – 12:00

12:00 – 1:00

1:00 – 2:30

1:00 – 1:30

1:30 – 2:00

2:00 – 2:30

2:30 – 3:00

3:00 – 5:00

3:00 – 3:30

3:30 – 4:00

4:00 – 4:30

4:30 – 5:00

6:00 – 9:00

7:00 – 8:00

8:15 – 8:45

8:45 – 9:30

KEYNOTE II KEYNOTE II9:30 – 10:15

10:15 – 10:30

Bi-Series

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GROUP

BREAKFAST BREAKFAST

BREAK BREAK

4/A TUTORIAL - FLEX™ Platform Calibration 101 Igor Lavrinenko, Teradyne

4/B How to Capture All Fail Data from ScanVectors Using the Memory Test Option (MTO)on the FLEX™ Johnny Steck, Texas Instruments; DwayneDohmann, Thuy Tran, Teradyne

DIGITAL

Letting Q Program the FLEX

4/A Use Half of ADC Bits Output toReconstruct Waveform for Dynamic TestingAdonis Chang, Teradyne

4/B Improving INL DNL Repeatability Steve Matej, Jim Ptasinski, Texas Instruments; KentMagnuson, Teradyne

MIXED SIGNAL

How Many Bonds Can You Convert? I

5/B Undersampling Using Beat Frequency(Theory and Practice) Ching-Chia Tien, Teradyne

4/A How to go Beyond 30V @ 100mA with onlyTwo DC30 Channels Dean Garrison, Sherry Sponheimer, Teradyne

4/B Pararallel Test Solution for a High CurrentPROFET Device Using FLEX™ DC90 DEMUXPetar Fanic, Tzong Sheng Ng, Infineon Technologies

POWER MANAGEMENT/ AUTOMOTIVE

Welcome to Power: HighVoltage/High Current Test

5/A DC90™ Voltage Compliance, Part 1: InsiderLook at the DC90 Power ModelCristian Cesarini, Arthur Russell, Chi-Heng Wang,Teradyne

FLEX: Shaken not Stirred

5/B A Simplified J750™ Technique to Handle E-Flash Data Management Chi Wee Ang, Gang Liu, Infineon Technologies

5/C ETAccess to IG-XL™ Silicon Solution Givargis Danialy, LogicVision; Ted Kim, Iwan Oei,Guillermo Pidal, Teradyne

How Many Bonds Can You Convert? II

5/A Microcontroller-Based Servo Loop for ADCLinearity Testing Shu Xia, Teradyne

5/C Testing a Correlated Double Sampling ADCon the FLEX™Lai-Choon Chan, Teradyne

6/B Conversion of ADC Ramp Tests from theJ750™ to the UltraFLEX™ Russell Long, Freescale Semiconductor; TimScanlon, Teradyne

Welcome to Power: HighVoltage/High Current Test

5/B TUTORIAL — DC90™ Voltage Compliance,Part 2: Are You Getting your Two Kilowatt'sWorth? Cristian Cesarini, Arthur Russell, Chi-Heng Wang,Teradyne

6/A When to Use Which V/I Crossover Type onthe FLEX DC90™XP Mereen Mammen, Teradyne

LUNCH LUNCH

6/A Enabling Modularity and Portability to TestMulti-Configuration Memories within a SingleChip TayBian Yeoh, Texas Instruments

6/B Trade Between Speed and Flexibility:Develop a Pattern Conversion Tool Adun Ye, Teradyne

6/C High-Speed Memory Test and RedundancyAnalysis (RA) on the UltraFLEX™ Hiroshi Kaga, NEC Electronics; Hideaki Nakajima,Teradyne

BUSINESS MEETING, ENGINEERING UPDATE, POSTER/ROUNDTABLE SESSIONS, VENDOR FAIR

7/A SEMICONDUCTOR BUSINESS MEETING

7/B SEMICONDUCTOR ENGINEERING UPDATE

7/C SEMICONDUCTOR OPEN FORUM DISCUSSION

POSTER/ROUNDTABLE SESSIONS

VENDOR FAIR

Memory Test Never Dies

6/A Clock Jitter Effect for Testing DataConverters Jin-Soo Ko, Teradyne

6/C Testing High-Speed Mixed-Signal Deviceson the UltraFLEX™ Daniel Weinberg, Analog Devices

How Many Bonds Can You Convert? III

6/B Paralleling DC90XP VIs to Achieve CurrentsBeyond Merged Mode Eric Bergeron, Maurilio Fabiano, Teradyne

6/C Introduction to the DC90XP™ — A HighPower Instrument Optimized for theAutomotive Market Cristian Cesarini, Larry Klein, Teradyne

Welcome to Power: HighVoltage/High Current Test

4/A PI Version Selector Mike Knapp, Analolg Devices; Laurent Bonneval,Teradyne

4/B How to Write and Use Simple DLLs toAccelerate Code Execution Emanuele Vazzoler, STMicroelectronics; AlfredoStabile, Teradyne

PRODUCTION INTEGRATION & HW/SW INTERFACE

Collaboration

Collaboration and Revision Control

5/A Test Program Guidelines for CollaborativeDevelopment Jeff Cramer, Jonathan Kubala, Tom Vance,Teradyne

5/B Subprogram Modularity: Improving TestProgram Development Productivity andReusability Kevin Bushe, Teradyne

5/C Smarter ASCII Export for Dumber CMTools: Using Interpose Functions withASCII_Utils.xla Glenn Carson, Freescale Semiconductor

6/A Mixed-Signal Simulation for Test ProgramDevelopment Philippe Raynaud, Mentor Graphics; PhilippePlanelle, STMicroelectronics

6/B Integrating the GSI Group WaferTrim™M310 with the microFLEX™ John Grandbois, Analog Devices; Peter Turner,Teradyne

6/C Enabling Customers to Develop TailoredInstruments for the FLEX™ Architecture throughOpenFLEX™ Omar Biabani, Lee Holt, Robert Manlick, Teradyne

Tester Integration B

4/A Characterization/HVM Comprehensive TestSolution for 10G/3G Transceiver Utilizing theTeradyne Tiger Platform and SDM 10G ModuleFayez Sedarous, Intel Corp.

4/B Interpolation Cookbook: Algorithms,Performance, and Guidelines Aimen Oueslati, NXP Semiconductors; MartinDresler, Teradyne

RF WIRELESS

Miscellaneous

Tutorials

5/A TUTORIAL — Forward Error Correction inWireless Communication Standards Steven Fields, Teradyne

5/B TUTORIAL — GSM/EDGE EVM Test Ching-Chia Tien, Teradyne

6/A TUTORIAL — DTV/HDTV testing onUltraFLEX™ Fang Xu, Teradyne

Tutorial

4/A Hands-on Programming the Di-Series usingiStudio Workshop

ASSEMBLY TESTMIL/AERO

iStudio/Di-Series

iStudio/Di-Series

5/A Hands-on Programming the Di-Series usingiStudio Workshop (Continued)

5/B Replacing M9-Series Digital TestInstruments (M9-Series DTI) with Di-SeriesDigital Test Instruments (Di-Series DTI) Lloyd Frick, Teradyne

6/A Applications for Ai- and Bi-SeriesInstruments in Legacy™ Tester Replacement Gary Bryant, Richard Lawrence, NAVAIR

6/B TBA

6/C A Reconfigurable, Extendable L200 Auto-Converter Yonet Eracar, Teradyne

7/A Engineering Update

ROUNDTABLE DISCUSSIONS

BREAK BREAK

9:00 – 9:30

9:30 – 10:00

9:00 – 10:00

10:00 – 10:30

10:30 – 12:00

10:30 – 11:00

11:00 – 11:30

11:30 – 12:00

12:00 – 1:00

1:00 – 2:30

1:00 – 1:30

1:30 – 2:00

2:00 – 2:30

2:30 – 3:00

3:00 – 7:00

3:00 – 3:15

3:15 – 4:00

4:00 – 4:45

4:45 – 7:00

4:00 – 7:00

7:30 – 8:30

Instrument Replacement

5/A Fast Time Measurements in Millisecondswith HSD Channels on the FLEX/microFLEXDiego Koch, Massimo Zambusi, Teradyne

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The following companies are participatingin the TUG 2007 Vendor Fair:

Dynamic Test Solutions, Inc.RICHARDSON, TX 75081 • TEL 972-235-9477

Dynamic Test Solutions offers custom designedPCBs for ATE applications, including loadboards,DUT boards and Probe Card circuit boards. DTSprovides complete turn-key test hardware (probecard, socket, stiffeners and assembly) for allTeradyne tester platforms. DTS specializes in complexdesigns, including RF, mixed signal and fine pitchapplications. Design platforms include CadenceAllegro, Mentor Expedition and PADS Power PCB.

Additional information about DTS is availableat www.dynamic-test.com

GSI Group, Inc.WILMINGTON, MA 01887 • TEL 734-623-8170

GSI Group Inc. supplies laser-based manufactur-ing systems to global medical, semiconductor,electronics, and industrial markets.

Featuring the WaferTrim M350 laser system.The superior solution for active IC trim (trimmingwhile probing and measuring), passive trim, linkcutting, and linear trimming at wafer level. TheM350 incorporates precision probing, wafer han-dling, latest laser technology while integratingtoday's state of the art testers.

Everett Charles TechnologiesWARWICK, RI 02886 • TEL 401-739-7310 X237

The Semiconductor Test Group of Everett CharlesTechnologies (ECT) is the premier supplier ofTurnkey Interface Solutions to the worldwidesemiconductor test market. ECT designs, manu-factures, services and supports printed circuitboards, test sockets, probe towers and springprobes, offering Integration Services for BOMmanagement and PCB Assembly with 100%post-assembly test. They offer bare-board-onlyfabrication, board + assembly, contactor-only, orany combination of products for ATE InterfaceSolutions. ECT provides true worldwide support,with Design and Applications Centers in Arizona,California, Minnesota, the United Kingdom,Malaysia, Singapore, and the Philippines, and FieldRepair offices in California, Malaysia, Singapore,the Philippines, and China. Additional informationabout ECT is available at www.ectinfo.com

Gorilla Circuits, Inc. SAN JOSE, CA 95112 • TEL 781-238-0214

Gorilla Cicuits is a Printed Circuit BoardManufacturer that has extensive experience withall Teradyne ATE Test Platforms. Gorilla hasfocused its technology and expertise to cater toDUT and Probe Card PCB manufacturing. Thesetechnologies include: 31:1+ aspect ratio holes,.5mm pitch, 50+ layers, critical impedance toler-ances, multiple lamination steps, and highspeed/mixed materials.

HCL Amereica, Inc.SUNNYVALE, CA 94085 • TEL 408-733-0480

HCL Technologies is one of India’s leading globalIT Services companies, providing software-led ITsolutions, remote infrastructure managementservices and BPO. HCL Technologies focuses onTransformational Outsourcing, working withclients in areas that impact and re-define the coreof their business. HCL leverages an extensiveglobal offshore infrastructure and its global net-work of offices in 16 countries to deliver solutionsacross select verticals including Financial Services,Retail & Consumer, Life Sciences Aerospace,Automotive, Semiconductors, Telecom and MPE(Media Publishing & Entertainment). Additionalinformation about HCL Technologies is availableat www.hcltech.com

inTEST Corporation CHERRY HILL, NJ 08003 • TEL 856-424-6886

inTEST provides test head docking, manipulator,and wafer probing interfaces for Teradyne testsystems. Our products are available from Teradyne,as OEM products, or are available from inTESTdirectly. Our engineers work closely withTeradyne to ensure that our products will enhancethe productivity and utility of your test floor.

Visit our website:www.intest.com to see thecomplete array of products available from inTEST.

Mentor Graphics Corporation WILSONVILLE, OR 97070 • TEL 502-685-7000

As technologies move below 100nm, the ICindustry is experiencing a significant change inthe way devices are failing and the types ofdefects encountered. New defect mechanisms,combined with initial and mature yields that aretrending downward, require a renewed focus onthe quality of test in order to maintain adequatequality levels of shipped devices. MentorGraphics market-leading DFT tools are critical tothe role test methodologies and tools play indefect detection and yield improvement. Mentoroffers new diagnostics techniques that can beused to mine valuable data about the failingmechanisms, enabling isolation of the root caus-es and correction of the yield loss issues.

Additional information about MentorGraphics Design-for-Test is available atwww.mentor.com/dft.

Pintail TechnologiesPLANO, TX 75024 • TEL 972-464-5835

Pintail Technologies is a leading semiconductortest improvement and yield learning company.Pintail’s software products are based upon real-time data acquisition running on most popularATEs. With over 250 systems installed worldwide,these products reduce the test cost, increasequality and accelerate yield learning across thesupply chain. Pintail has offices in Dallas, Austin,San Jose, Seoul, Singapore, Taiwan, and Munich.www.pintail.com.

Salland Engineering (Europe) BV8024 HA ZWOLLE, THE NETHERLANDS •TEL 31 38 454 7702

Salland Engineering is a world leader in TestApplication Support, Data Analysis, ATE customhardware products and solutions. The unique com-bination of Test Engineering knowledge with hands-on experience has helped our customers achievetheir goals in terms of time-to-market, reducedtest time and overall improved test efficiency.

We are specialized on new high-density testinstruments, and we offer now the highestamount of channels for DC & AC instruments inthe market. We offer, as well, test cell integrationsolutions for: EG, TSK, TEL, KLA, handlers, includ-ing PAT, real-time monitoring etc.

Additional information about Salland is avail-able at www.salland.com.

Teradyne — Test AssistanceGroup (TAG)WORLDWIDE LOCATIONS • WEB http://teradyne.com/TAG• EMAIL [email protected]

Teradyne's Test Assistance Group (TAG) combinesglobal presence with a successful test develop-ment history to provide the low risk solution forbringing your products to market sooner. TAG'sfull spectrum of support solutions satisfy yourneeds in device test planning, code development,characterization, interface hardware design, cor-relation and porting to high-volume test facilities.Additionally, TAG's global support and trainingcenters offer convenient access to the latestTeradyne test systems and expertise. We look for-ward to meeting you personally at TUG-2007.

Take advantage of TAG's technical support:Milestone Project Solutions • Test InterfaceHardware • Training & Skill Development •Consulting/Coaching

Test Advantage TEMPE, AZ 85296 • TEL 480-357-3351

Test Advantage offers a software product linefocused on improving yield, quality, DPPM, andoverall test process efficiency during both ramp-up and volume production. Products include:Streetwise™ Production, Streetwise™ Engineeringand Express™. Streetwise is an integrated, in-linedata analysis solution utilizing automatic algo-rithm selections for highly efficient dynamic para-metric outlier detection for all types of data population distributions, with additional compre-hensive spatial outlier detection methodologies atwafer test. Express is an off-line test engineeringassistant offering comprehensive analysis of testdata, in order to automatically generate recom-mendations for improving the test process in theareas of quality, yield, and test efficiency.

Additional information about Test Advantageis available at www.testadvantage.com.

POSTERS

DIGITALA Perl Script to Search Pattern Files for One Port and WriteValues in a Summary File Tao Li, Yi Fan Li, InfineonTechnologies

A Total Solution to Convert aVerigy 93000 Project Henry Zhou, Teradyne

IMAGE™ to UltraFLEX™Conversion: New Strategy andNew SolutionJack Chen, Hall Lou, Teradyne

Performance Enhancement forPattern LoaderHemamalini Nagarajan,Gopalakrishnan Srinivasan,Teradnye/HCL Technologies

Standalone Pattern CompilerVinai Kumar Singh, LathaSubramanian, Teradnye/HCLTechnologies

MIXED SIGNALAdvanced Techniques toOvercome Tester Limitations When Testing ADCsAarthi Sundararajan, Tessolve TestServices

Another POP StoryKent Magnuson, David Pickard,Teradyne

Increase Time for Coffee Breaks— Reduce Time for Test Development and DebugRoy Chorev, Ali Syed, Teradyne

Incorporating the J750™ into the Electrical and ComputerEngineering Curriculum — MSO OptionRobert Weber, Iowa State University

POWER MANAGEMENT/AUTOMOTIVEImplementating a SetupManager VB Class to Simplify PSet-BasedInstrument ProgrammingManfred Graf, Teradyne

PRODUCTION INTEGRATIONVOM (Voice of Mine) — Closing the LoopSwagata Chakrabarti, PeterChuang, Teradyne

Integration of Full Dynamic Test-Cell Controller with IG-XL™Rob Marcelis, Salland Engineering

Enabling Customers to DevelopTailored Instruments for theFLEX™ Architecture throughOpenFLEX™ Omar Biabani, Lee Holt, RobertManlick, Teradyne (Also Paper - PI_6C)

Securing Test Systems in theProduction EnvironmentBob Mastrogiacomo, Jaci WilsonTeradyne

ROUNDTABLEDISCUSSIONS

SEMICONDUCTOR TESTUpdate on IG-XL HelpJohn Buckley, Mike Gill, Teradyne

DTV/HDTV Testing on theUltraFLEX Q&AFang Xu, Teradyne

OpenFLEX

TAG Table

ASSEMBLY TEST —MIL/AEROBi-Series

Di-Series

iStudio

Spectrum

Ai-Series

POSTER/ROUNDTABLE SESSIONS TUG 2007 VENDOR FAIR

Page 8: TUG '07

BREAKFAST

GROUP

BREAK

8/A Getting More with UltraFLEX™: PatternFiles, Modules, and Sets Preeti Nargund, Teradyne

8/B A Flexible Pattern Format and PlatformConversion Tool Ramon Liu, Freescale Semiconductor

DIGITAL

R. Moore Patterns

9/A Test Time Reduction Technique throughShared Resources Joo Yong Teng, Kar Meng Thong, InfineonTechnologies

8/A Programming Pattern Vectors and DSSC onMUX Mode for FLEX™ Yan Jin, Jason Miller, Haibo Zhang, TexasInstruments; Cliff McCallister, Teradyne

8/B High-Speed Dynamic ADC Test on a Low-Cost Digital Tester Mile Cheung, Claus Dworksi, Infineon Technologies

MIXED SIGNAL

Spectre's World DominationConcepts I

9/A How to Specify Units and Scale Test Limitsin the IG-XL™ 5.1 Flow Sheet Eric Buvry, Teradyne

8/A Challenges to Test an ADC in anAutomotive Device Hugo Molina, Texas Instruments

8/B An Easy Way for SPI Communication via DSSC Wei Chong Ng, Infineon Technologies; NazlenJabar, Teradyne

POWER MANAGEMENT/ AUTOMOTIVE

Automotive SoC and IC Integration

9/A Airbag Device Testing on the FLEX™ Jian-Wei Wang, Kenny Zhu, Teradyne

Production is Not Enough

9/B Converting J750™ Test Programs from DPSto High Density Voltage and Current Source(HDVIS) for More Parallelism Leo Di Bello, Thomas Fanter, Teradyne

9/C Adding Setup Information to Test FlowUsing IG-XL™ VBT Ramon Liu, Freescale Semiconductor

10/A Getting the Most Out of IG-XL™Characterization Mike Patnode, Teradyne

Spectre's World DominationConcepts II

9/B Advanced Parallel Trim Algorithm withPOOL PVM Auto-Calibration Jared Jones, Analog Devices

9/C Improving Test Efficiency Using DFTConcepts: A Potpourri of Ideas from ServoDevices Sundeep Desai, Texas Instruments

10/A It Pays to Own a FLEX™ Norikazu Sugano, Sony Japan; Jack Chen, GavinGao, Terayne

Automotive SoC and IC Integration

9/B Octal-Site Final Test Concept forAutomotive Intelligent Distributed ControlProducts Johann Hilburger, Gerhard Knez, OlafNeper, Freescale Semiconductor

9/C The Lowest Cost Method of IDDQ Testingon the J750™ Satoshi Funakoshi, Teradyne

10/A Modulation Input Applications ExtendDCVI Applicability in POP Diego Koch, Alfredo.Stabile, Massimo Zambusi,Teradyne

LUNCH

10/B AppsShmoo: A Tool for CharacterizingDevices Stephen Davis, Zubir Ebrahim, Yukichi Inoue,Teradyne

10/C IG-XL™ UltraFLEX™ Characterization Library Anne Marie Guray, Broadcom; Vivian Wang,Teradyne

11/A IG-XL™ STIL Bridge Michael Cavallini, Julia DiChiaro, Teradyne

11/C Extended Characterization Method for theJ750™ Deyan Karastoyanov, Infineon Technologies

11/B Proper PPMU Route Sequence to MinimizeGlitches at the DUT Zuyan Liang, Shams Syed, Teradyne

A Golden Eye on Characterization

Testing is Forever UltraFLEX Concepts Reducting Test Costs

10/B Double Your Sampling Rate See Hwa Goh, Teradyne

10/C Controlling the Flow - ImplementingComplex Test Program Flows in the IG-XL™ FlowTable John Arico, Analog Devices

11/A New Approaches to Pulse Train IntegrityTesting Scott Therrien, Fang Xu, Teradyne

11/B Using DCTimeHP to Measure SpreadSpectrum Clock Generation (SSCG) ModulateClock Frequency on the UltraFLEX™David Wu, Teradyne

11/C UltraFLEX™ DSSC Test Time Optimization Tyler Tolman, Broadcom; David Lam, Teradyne

11/D An Easily Integrated, Efficient Approachfor Wideband Captures Using TurboAC™ Andrew Varley, Teradyne

Spectre's World DominationConcepts III

10/B Octal-Site High-Power Class-D AmplifierInterface Board Design Mike Chu, Yan Jin, Haibo Zhang, Texas Instruments

11/A Reducing Wafer Testing Cost for theAutomotive Market on the FLEX™ Jerome Mercier, Freescale Semiconductor; FrancisDanel, Teradyne

11/B Speed Up Test Program Execution for DCInstrumentation Giorgio Calia, STMicroelectronics; Nicolino Tassara,Teradyne

11/C Help! Where Do I Start in Test ProgramConversion? WL Chan, Dean Garrison, Teradyne

Power Management General Programming Test Techniques

8/A Calibration of SE-HDACTO Pushes the DCCalibration Unit to its Limits Dirk Jan Stuij, Salland Engineering

8/B Effective Spot Calibration of the DC30™Source and Meter Using PSets Michael Shilhanek, Texas Instruments; ZaydHammoudeh, Nathaniel Jansak-NobleTeradyne

PRODUCTION INTEGRATION & HW/SW INTERFACE

Calibration

9/A A Useful VBT Programming Tool Integratedin IG-XL™ Hao Chang, Teradyne

Programming

9/B Buttons to Generate VBT Bin Chiu, Teradyne

9/C Automated Optimization and Cleanup ofVBA-based Test Programs Hubert Schafzahl, Infineon Technologies

10/A Automated Voltage and TemperatureCharacterization Utility for IG-XL™ Tarang Dadia, Qualcomm; Daniel Buker, Teradyne

10/B Introducing Power Supply Status Variables– A Simple and Efficient Way to Organize andDocument Test Functions Yaw-Hua Hong, Weishu Wu, Texas Intruments

10/C A Software Technique for Checking DataIntegrity in Fuses Steve Sheck, Freescale Semiconductor

Handler n'All

8/A Test Time: A License for an RF TestEngineer! Philippe Soleil, NXP Semiconductors

RF WIRELESS

Test Time Reduction

8/B Test Time Reduction and Strategy on aMulti-Chip Device Mike Bellanger, Salvatore Cutrupia, NXPSemiconductors

Test Techniques

9/A Generating ASK Modulation Signals forContactless Chip Card Controllers on the J750™ Hubert Schafzahl, Johannes Schorrer, InfineonTechnologies

9/B Low-cost Alternate EVM Test for WirelessTransmitter Systems Philippe Brousse, NXP Semiconductors

9/C RF Test Code Templates for WCDMA+GSMTransceiver on Generic RF DIB Albert Jen, Charles Kao, Luis Tang, Teradyne

10/A Developing the Spectrum Mask/AdjacentChannel Power Test on the FLEX HongBin Tong, NXP Semiconductors; Ching-ChiaTien, Teradyne

10/B Accurate GSM Phase Error and EVMMeasurements on the FLEX™ Helen Chen, Greg Dionne, Shu Xia, Zhe Xu,Teradyne

10/C RF Modulation/ Demodulation forDummies M.Ramasamy, Gopalakrishnan Srinivasan,Teradyne/HCL Technologies

SURVIVOR PARTY

10:30 – 12:00

10:30 – 11:00

10:00 – 10:30

9:30 – 10:00

9:00 – 9:30

9:00 – 10:00

11:00 – 11:30

11:30 – 12:00

12:00 – 1:00

1:00 – 2:00

1:00 – 1:30

1:30 – 2:00

2:00 – 2:30

2:30 – 3:00

3:00 – 5:00

3:00 – 3:30

3:30 – 4:00

4:00 – 4:30

4:30 – 5:00

5:30 – 7:00

7:30 – 8:30

12

11/A Reduce, Reuse, and Recycle: On-the-Fly DCMeasurements without a New Instrument Jim Crafts, Amit Shah IBM

11/B Using 32x Parallel Test with ViProbe forTest Time and Test Cost Reduction on Low CostDevices Andreas Berdzentis, Texas Instrumentsy; AndreVogel, Teradyne

11/C Practical Hardware and SoftwareConsiderations for High-Parallel Mixed-SignalTesting with the J750™Michael Jonas, Texas Instruments

11/D Simultaneous Device Testing at MultipleHandlers with Single FLEX™ and Cable Docking Armin Winkler, Infineon Technologies;Ramanamurthy Pakki, Teradyne

BREAK

13

Page 9: TUG '07

DIGITAL

Session 2/C: 2:00 – 2:30

Testing High-Speed Serial Busesthrough a Generalized Template forthe UltraFLEX™ SB6GJoe DeSimone, Freescale Semiconductor; Bill Davis, Teradyne

This paper will demonstrate the key features of the SB6G high-

speed serial test instrument for the UltraFLEX. Several of the chal-

lenges met while testing today's high-speed 8b10b encoded data

streams will be addressed using various test methodologies. For

example, the differences between real-time compare, post-

processed capture data, and 32-bit signature generation will be

explained in detail. The template code provided with this paper

will enable customers to bring up their high-speed tests for pro-

duction and/or characterization quickly and easily. Several options

are available for the end-user with regard to datalogging, jitter

and eye measurements, and the creation of data files for post-

process or use with the offline Cyclops tool provided by Teradyne.

BREAK: 2:30 – 3:00

Session 3/A: 3:00 – 3:30

High-Speed Loop Back Test Solutionfor SerDes Products Using SB6GPatrice Ducharme, Dany Minier, Doris Viens, IBM; David Keezer,

Georgia Institute of Technology

One test strategy used for testing SerDes and high-speed buses is

the built-in self test or BIST (sometimes called BOST or built off

self-test) approach where the device under test is in loop-back

mode. To complement the SB6G cards, the authors developed a

modular approach that allows passive and active loop-back test

on an UltraFLEX™ device interface board. This paper outlines the

technique used and presents the characterization results for the

solution in the test environment.

Session 3/B: 3:30 – 4:00

SATA Testing with SB6GZubir Ebrahim, Teradyne

The Parallel ATA is being replaced with the high-speed Serial ATA

(SATA). Currently there are three generations of SATA which run

at the rates of 1.5Gbps, 3.0Gbps, and 6.0Gbps, respectively.

SATA Gen I and SATA Gen II are in production today. At present,

customers are preparing to characterize SATA GEN III, which will

run at the rate of 6.0Gbps.

Session 3: 3:00 – 5:00Protocol, High-Speed Protocol

As the speed increases, current loop-back testing methods are

starting to have gaps and flaws. Customers recognize the need to

test at high speed to determine the critical test items that will

guarantee their devices will operate in the end application.

This paper will describe testing SATA using SB6G. One main

challenge in testing SATA is the Out of Band Sequence (OOB).

This paper will focus on how the author uses SB6G to character-

ize and test the OOB sequence and the other critical test items.

Session 3/C: 4:00 – 4:30

High-Definition Multimedia Interface(HDMI) Receiver Characterization andTest Techniques on the UltraFLEX™Peter Huber, Edward Seng, Teradyne

HDMI is an all-digital interface capable of transmitting streams of

uncompressed audio/video information between compatible mul-

timedia equipment. Examples include set-top box, DVD player, PC,

video game console, audio receiver, and video monitor and/or dig-

ital television (DTV). HDMI is readily becoming the industry stan-

dard, supporting content protection and future-generation video

resolution standards, and is subsequently being integrated into

the majority of next-generation SoC multimedia devices. This

paper will describe ways to characterize an HDMI receiver, utilizing

the features of the SB6G instrument synchronized with the

HSD1000 on the UltraFLEX test system.

Session 3/D: 4:30 – 5:00

HyperTransport™ 3.0 LinkCharacterization with SB6G on theUltraFLEX™James Yeh, AMD; Fady Bishay, Shawn Sullivan, Teradyne

This paper will describe characterization of a HyperTransport (HT)

3.0 Link using the SB6G option on the UltraFLEX test system. HT

3.0 is an extremely high-bandwidth interconnect with low latency;

it can be used for chip-to-chip and board-to-board connections.

The SB6G was designed to test SerDes devices with embedded

clock and, therefore, has relatively loose edge placement accuracy

specs. HT is a source-synchronous link which requires tight edge

placement accuracy. Although HT 3.0 has loosened lane-to-lane

timing requirements, it still requires the test instrument skew to be

tightly controlled to allow characterization of some key specs.

Devices with HT 3.0 links must also be able to boot up in HT 1.x

mode which also requires tight control of edge placement during

characterization.

The primary HT 3.0 transmitter characterization tests include

unit interval, differential peak-to-peak output voltage swing, com-

mon mode output voltage, transmitter eye width, rise/fall time,

output impedance and data valid time relative to the clock. The

primary HT 3.0 receiver characterization tests include differential

input voltage sensitivity, common mode input voltage, eye width

(jitter tolerance), input impedance, and max skew allowed

between clock and data.

TERADYNE PARTY: 6:00 – 9:00

15

7:00 – 8:00: BREAKFAST

8:15 – 8:45: WELCOME

8:45 – 9:30: KEYNOTE I

9:30 – 10:15: KEYNOTE II

10:15 – 10:30: BREAK

Session 1/A: 10:30 – 11:00

Pattern Matching on the Tiger™ Jason Laderman, Intel Corporation

The Tiger offers a variety of methods to determine a passing pat-

tern. However, there are limitations, particularly when distinguish-

ing different failure modes and getting conclusions from non-

deterministic interfaces. When the Tiger’s HRAM is used, realistic

methods can be developed to automate checking non-determin-

istic logic outputs, broaden an edge search, decrease tester time,

read registers easily, and manipulate data to distinguish different

failure modes.

Session 1/B: 11:00 - 11:30

Using the HexVS as an IndependentDVM Data Acquisition InstrumentPatrice Ducharme, Roxan Lemire, Michel Paradis, IBM; George

Simbles, Teradyne

With more applications in the high power range of 100+ watts,

having the capability to profile power planes against temperature

rise becomes a valuable tool. This profiling capability will help to

characterize and understand hot spots, thermal resistances, and

power fluctuations. Previously, mixed-signal digitizers or external

scope/data acquisition equipment were commonly used to cap-

ture analog-type profiles. This paper will present a novel approach

to accomplish DATAQ using the HexVS as an independent DVM

profiler.

Session 1: 10:30 – 12:00The Man with the Innovative

Test Technique

DIGITAL Session 1/C: 11:30 – 12:00

KeepAlive™: Then and Now Way Kyi, Teradyne

KeepAlive can be used for uninterrupted (seamless) pattern oper-

ation while changing a new pattern or downloading a new pat-

tern subroutine. All of these functions can be done without losing

a pattern heartbeat. It can also be used to run multiple DSSC pat-

terns without stopping and restarting pattern generator.

KeepAlive is used to keep Phase Lock Loop running while switch-

ing from one pattern to another. There are other applications, like

changing digital levels or timing edges which can be used in

KeepAlive mode. In this presentation, the similarities and differ-

ences of KeepAlive usage among all three platforms (J750™,

FLEX™ and UltraFLEX™) will be described. An application note in

a Microsoft Word file will accompany this presentation.

LUNCH: 12:00 – 1:00

Session 2/A: 1:00 – 1:30

A User Characterization of the SB6GInstrument Patrice Ducharme, Roxan Lemire, Dany Minier, Doris Viens, IBM;

Fady Bishay, Mike Patnode, George Simbles, Teradyne

With more applications in the Gbps range, test engineers should

seriously consider using the SB6G instrument for its speed and

capabilities for at-speed functional test or as a clean high-frequen-

cy clock source. Before using SB6G, the authors first characterized

its performance and functions using different loadboard, board

strips, and test JIG designs for evaluation. Particular focus was put

on the TX side SB6G instrument. In this paper, the results of that

characterization will be presented from the customer’s perspec-

tive.

Session 2/B: 1:30 – 2:00

Characterizing High-Speed ParallelBuses with the SB6G and Sub-MOSCTimingErik Lusis, IBM; Fady Bishay, Doug Mainz, Teradyne

A method for characterizing parallel high-speed buses using the

SB6G and sub-MOSC timing will be presented. A requirement for

this technique is that the lane-to-lane skew on the device inputs

are compensated by phase adjust circuitry (e.g., Rambus FlexIO).

Techniques used to achieve sub-MOSC timing for SB6G drive and

receive will be shown, along with how they are used to measure

input data eye and output setup and hold.

Session 2: 1:00 – 2:30For Your SB6G Only

14

Page 10: TUG '07

DIGITAL

LUNCH: 12:00 – 1:00

Session 6/A: 1:00 – 1:30

Enabling Modularity and Portability toTest Multi-Configuration Memorieswithin a Single ChipTayBian Yeoh, Texas Instruments

Memory Test Chip (MTC) architecture presents a unique challenge

to test engineering. An MTC may consist of a few dozen memory

instances, each with its own array configuration, word width,

operating mode, power management, and Design-For-Test

options. Using Pattern Runtime Modification techniques, this

paper will introduce concepts and methods for modularity and

code portability which, when used within this multi-configuration

environment, will greatly improve programming efficiency. Test

environment initialization that employs parallel-load controller reg-

isters and the serial-shifting JTAG protocol are discussed. In addi-

tion, the concept of an ‘Algorithm Repository’ with appropriate

methods to control SVM usage will be introduced. Limitations

and workarounds are also highlighted.

Session 6/B: 1:30 – 2:00

Trade Between Speed and Flexibility:Develop a Pattern Conversion ToolAdun Ye, Teradyne

Unlike translating a test program from one platform to another,

pattern conversion is more difficult and usually requires a tool. To

develop a tool, several things need to be considered, including

program language, grammar analysis, and potential reuse for the

tool. Using an LTX Envision to IG-XL™ pattern converter tool and

its coding experience, the author will describe the exploration of

different text parsing methods and apply them to the same proj-

ect. Based on the author’s analysis, a general rule and program

structure which balances development difficulty and application

flexibility for a pattern conversion tool will be recommended.

Session 6: 1:00 – 2:30Memory Test Never Dies

Session 6/C: 2:00 – 2:30

High-Speed Memory Test andRedundancy Analysis (RA) on theUltraFLEX™Hiroshi Kaga, NEC Electronics; Hideaki Nakajima, Teradyne

Recently, the device trend is on highly integrated SoC or SiP, but

no tester can be used for all products. The UltraFLEX test system

has a universal slot architecture and HSD1000 already includes

MTO hardware which can generate up to a 250MHz pattern, cre-

ate the bit map data, and execute the redundancy analysis. In

addition, the MTO can run up to 500Mbps with some techniques.

In this paper, the authors will describe a high-speed memory test

and RA on the UltraFLEX.

BREAK: 2:30 – 3:00

Session 7/A: 3:00 – 3:15

Semiconductor Business Meeting

Session 7/B: 3:15 – 4:00

Semiconductor Engineering Update

Session 7/B: 4:00 – 4:45

Semiconductor Open ForumDiscussion

VENDOR FAIR: 4:00 – 7:00

Session 7: 3:00 – 7:00Engineering Update, Round Table/

Poster Sessions & Vendor Fair

17

BREAKFAST: 7:30 – 8:30

Session 4/A: 9:00 – 9:30

Tutorial — FLEX™ Platform Calibration 101Igor Lavrinenko, Teradyne

This tutorial will include many FLEX calibration topics. Some topics

that will be covered are: 1) high-level user model and tools; 2) cal-

ibration and processes in an IG-XL™ job as well as in the mainte-

nance (MUI) environment; 3) software and hardware components

involved in the calibration process; 4) from the software perspec-

tive, autocal, job-dependent calibration, cal-related activities in the

maintenance environment, success and failure patterns in calibra-

tion software, and various ways to view and interpret calibration

status; 5) calibration-related hardware components, including DC

Cal Module, Timing Cal Module, PSP, DIB, EEPROM, and the

extent of their involvement in calibration; 6) digital instrumenta-

tion highlights; and 7) VBT and other calibration related program-

ming interfaces. In addition, various useful cal-related “tricks” and

“hacks” that one day may save your life will be shared.

Session 4/B: 9:30 – 10:00

How to Capture All Fail Data fromScan Vectors Using the Memory TestOption (MTO) on the FLEX™Johnny Steck, Texas Instruments; Dwayne Dohmann, Thuy Tran,

Teradyne

An easy way to build a datalog of scan results is to capture scan

index, scan cycle, and scan output pins with HRAM and write the

result to a text file. While this method works well with smaller

patterns or fail counts, it is difficult to use when capturing data

sets that exceed the 256 locations available in HRAM. One alter-

native method is to use the larger capture memory or Capmem

(1.5 GB RAM: 24M x 64 bits wide). Capmem is available on the

digital channel cards and capable of capturing data up to

100MHz to obtain the fail data. Using MTO opcodes such as X-

address-increment (xa inc) and Y-address-increment (ya inc), the

scan index and scan cycle can be mapped into the X and Y coun-

ters. In addition, by using the MTO resource map it is possible to

obtain the scan output pins for capture bits. This paper will

describe this method as applied to a customer application program.

Session 4: 9:00 – 10:00Letting Q Program the FLEX

DIGITAL

BREAK: 10:00 – 10:30

Session 5/A: 10:30 – 11:00

Fast Time Measurements inMilliseconds with HSD Channels onthe FLEX/microFLEX™Diego Koch, Massimo Zambusi, Teradyne

This test technique enables precise measurement of propagation

delays and rise/fall times to be performed in milliseconds with

one HSD board. Standard techniques require two HSD boards or

time-consuming edge-find methods. The technique uses a special

timing and a pattern that can be generated automatically. It uses

a linear search instead of a binary one, thus improving the

robustness in the presence of jitter and noise. This technique

scales to multi-pin and multi-site easily and efficiently and over-

comes some severe limitations of accuracy and parallelism in the

FLEX/microFLEX instrumentation.

Session 5/B: 11:00 – 11:30

A Simplified J750™ Technique toHandle E-Flash Data ManagementChi Wee Ang, Gang Liu, Infineon Technologies

Most of the new microcontrollers have embedded flash which can

be used to store unique chip information during test runs. The

data storing activities are to be handled by the test program with

the help of some special pattern and functions. This paper intro-

duces a technique to implement a simple but efficient method to

store and verify unique chip information to a dedicated address

in e-flash.

Session 5/C: 11:30 – 12:00

ETAccess to IG-XL™ Silicon SolutionGivargis Danialy, LogicVision; Ted Kim, Iwan Oei, Guillermo Pidal,

Teradyne

To increase the silicon debugging capabilities of the UltraFLEX™, a

solution to interface IG-XL™ and ETAccess from LogicVision was

developed. The ETAccess group of products supports the at-speed

testing, datalogging, and debugging of silicon. When the power of

ETAccess is combined with ATE, engineers can diagnose and debug

devices much faster than ever before. This presentation will give a

brief introduction to ETAccess and describe the solution for UltraFLEX

and how it can be leveraged for other IG-XL-based testers.

Session 5: 10:30 – 12:00FLEX: Shaken not Stirred

16

Page 11: TUG '07

DIGITAL

BREAKFAST: 7:30 – 8:30

Session 8/A: 9:00 – 9:30

Getting More with UltraFLEX™:Pattern Files, Modules, and SetsPreeti Nargund, Teradyne

For many years, the challenge for the ATE industry is to provide

fast, low-cost test solutions. Test times include loading, validating,

and executing test programs with large quantities of input data

called Patterns. The architecture for each test platform focuses on

additional techniques that will achieve test time reduction. The

features on the UltraFLEX which decrease test time include the

capability to reduce binary test pattern size and pattern load time,

as well as make test program debug easier.

This paper will discuss how UltraFLEX pattern compiler and stor-

age options, as well as various configurations of pattern files and

pattern modules, can affect test program load times. The first part of

the paper will focus on the use of the Channel Data Latch (CDL)

technique and its advantages with pattern load times. The same

technique will be carried out to compress the patterns using Z-zip

compression to measure the pattern compile and load times.

Advantages and disadvantages associated with both techniques are

compared. The second part of the paper will describe Pattern files,

modules, and the Patset architecture of the UltraFLEX platform — its

tradeoffs in debug capability vs. test program load times.

Session 8/B: 9:30 – 10:00

A Flexible Pattern Format andPlatform Conversion ToolRamon Liu, Freescale Semiconductor

In semiconductor test, platform conversion is strategically required

to tradeoff the cost of test and capacity. Along with platform con-

version, pattern conversion is an important but difficult task.

Normally, pattern conversion tools are written in script language

and customized for a particular pattern format. These customized

tools are rarely used again but, when reused, require program-

ming skills to modify and debug to fit the new conversion task.

This paper will introduce a flexible text pattern format modifica-

tion and platform conversion tool. The tool reads only pre-defined

format information from a configuration file to complete the pat-

tern format conversion, vector trim/shift, pin/column shift, and

micro-code extraction/conversion. With a one-time configuration,

it can be applied to any test platform; there is no re-configuration

and programming required. This tool has been widely used in

Freescale MCU platform conversions from Advantest to the J750™.

Session 8: 9:00 – 10:00R. Moore Patterns

BREAK: 10:00 – 10:30

Session 9/A: 10:30 – 11:00

Test Time Reduction Techniquethrough Shared ResourcesJoo Yong Teng, Kar Meng Thong, Infineon Technologies

With the complexity of our SoC devices and the increased test

time needed to test each device with embedded memories, we

are under tremendous pressure to reduce our test time/cost per

device. One of the quickest ways to achieve this is to increase the

number of devices tested in parallel.

This paper describes the experience of using the shared

resource feature available in IG-XL™ to increase the number of

sites being tested concurrently.

With this technique, we were able to double the number of

sites being tested on the J750 Teradyne tester, and achieved sig-

nificant test time reduction.

Session 9/B: 11:00 – 11:30

Converting J750™ Test Programs fromDPS to High Density Voltage and CurrentSource (HDVIS) for More ParallelismLeo Di Bello, Thomas Fanter, Teradyne

The high number of channels (24) per board on the HDVIS, a new

instrument on the J750, allows for more parallelism. Since the

HDVIS fits into the DPS slot, the test engineer can easily replace the

DPS with the HDVIS when needed. This paper will describe how to

convert existing DPS test programs to start using the HDVIS in the DPS

slot. The authors will describe their experiences and lessons learned

from two microcontroller program conversions. In addition, the

paper will describe how to use some of the other additional features

of the HDVIS to save test time and improve repeatability.

Session 9/C: 11:30 – 12:00

Adding Setup Information to TestFlow Using IG-XL™ VBTRamon Liu, Freescale Semiconductor

In a typical IG-XL test environment, the test setup information is

stored separately in Test Instance/PatSet/TimingSet/Level Sheets,

requiring frequent switching between worksheets to search setup

information for a test. This reduces the efficiency of program

debugging and increases the possibility of error, especially when

some test instances are using inheritance mechanisms to follow

the setup of a previous test instance in test flow. This paper will

introduce a technique to add setup information (such as

Level/Timing/Pattern/Specs/Relay Mode) to each test instance in

test flow using VBT. This technique will facilitate debugging for

test engineers. In addition, it can be integrated into VBA IDE as an

Add-In program or a VB module.

Session 9: 10:30 – 12:00Production is Not Enough

19

Poster Presentations/Roundtable Sessions: 4:45 – 7:00

Poster 1

A Perl Script to Search Pattern Filesfor One Port and Write Values in aSummary FileYi Fan Li, Tao Li, Infineon Technologies

Multi-site testing is the most effective way to reduce test time and

cost of test. While the number of sites is restricted by the number

of available testers and channels on the tester, reducing the pin

count or shared drivers is one way to maximize the number of

sites. This is especially true for front-end testing. When using a

reduced pin count method, some functional pins or ports are dis-

connected with minimal impact on test coverage.

The Perl Script described in this paper will help the test engi-

neer search all pattern files for one port and write input and out-

put values in a summary file. With the information provided in

the summary file, the test engineer will know which port can be

reduced with the least impact. Currently, this script can be used

only on the J97x platform and several 16-bit microprocessors.

Poster 2

A Total Solution to Convert a Verigy93000 ProjectHenry Zhou, Teradyne

In addition to TestFunction in Verigy 93000 software, TestMethod

is also a vital programming style widely used in mixed-signal tests.

When V93000 conversion capability extends to TestMethod level,

the "Template-Only" conversion is no longer limited, opening the

possibility for mixed-signal program conversion. This paper will

propose a total solution to convert a Verigy 93000 project. It will

begin with an overview of basic structures of TestMethod pro-

gramming style, followed by the necessary information in the

V93K program package, and ending with a description of the

approaches to map it to IG-XL™ platforms. Issues such as code

and pattern optimization will also be covered.

Poster 3

IMAGE™ to UltraFLEX™ Conversion:New Strategy and New SolutionHall Lou, Jack Chen, Teradyne

While Teradyne’s IMAGE-based testers (A5, Catalyst, Tiger) have a

very large installed base in the ATE market, Teradyne’s latest

tester, UltraFLEX, is gaining momentum. There have been and will

continue to be an increase in conversions from IMAGE-based

testers to the UltraFLEX. Currently, before an IMAGE-based tester

can be converted to UltraFLEX (pattern only), it must first be con-

DIGITAL verted to the FLEX™ followed by a conversion to the UltraFLEX

platform. This conversion process is inefficient and may cause loss

of information. In this paper, the authors will propose a strategy

based on the concept of a virtual platform that stores all the

extracted information from the IMAGE-based program/pattern

and efficiently converts it to the UltraFLEX without information loss.

Poster 4

Performance Enhancement forPattern LoaderHemamalini Nagarajan, Gopalakrishnan Srinivasan, Teradyne/HCL

Technologies

ATE performance depends on how fast it can load and test

devices. When the pattern is edited, the existing procedure loads

the entire pattern file into the memory instead of only the modi-

fied portion. In this paper, the authors will describe an alternate

method which loads only the edited portion of the pattern file

into the memory. When this method is used, the pattern load

time is decreased and tester performance is increased, resulting in

enhanced throughput to the customers. This method is expected

to result in a performance increase of 50% in, for example, the

case of pattern files with 1M vectors

Poster 5

Standalone Pattern CompilerVinai Kumar Singh, Latha Subramanian, Teradyne/HCL

Technologies

Currently, the Catalyst™/Tiger™ pattern needs the IMAGE™ envi-

ronment for compilation. Pattern needs only the pinmap information

for compilation which can be provided independently. The draw-

backs for implementing the current pattern compiler are: 1) compila-

tion time is high; 2) tester time in the debug mode is an overhead;

3) an IMAGE-dependent environment; and 4) a heterogeneous plat-

form so that the pattern source, i.e., Automated Test Program

Generation, could be in Windows but the compilation needs to be

carried out in UNIX. In this paper, the authors will propose a solution

to remove the dependency of the pattern compiler. The standalone

pattern compiler on a separate Linux m/c will compile the pattern

(.pat) file in a binary equivalent of .pat file, created in solaris m/c.

Round Table 1

Update on IG-XL HelpJohn Buckley, Mike Gill, Teradyne

Round Table 2

DTV/HDTV Testing on the UltraFLEX™ — Q&AFang Xu, Teradyne

Q&A for Session 6/A

Round Table 3

OpenFLEX

Round Table 4

TAG Table

18

Page 12: TUG '07

LUNCH: 12:00 – 1:00

Session 10/A: 1:00 – 1:30

Getting the Most Out of IG-XL™CharacterizationMike Patnode, Teradyne

This paper will explore how IG-XL characterization can be used

with interposing functions, other Visual Basic functions, and Excel

programming tools to present device characterization data in a

clear way. The author will describe standard shmoo and measure

capabilities and how customization can expand these capabilities.

Among the techniques discussed will be creating a VI curve,

showing per-pattern shmoos, and extracting device datasheets

from characterization data.

Session 10/B: 1:30 – 2:00

AppsShmoo: A Tool for CharacterizingDevicesStephen Davis, Zubir Ebrahim, Yukichi Inoue, Teradyne

This paper will describe AppsShmoo, an application Shmoo tool

developed by Teradyne for the FLEX™ and UltraFLEX™ platforms.

AppsShmoo has all the main capabilities of the current IG-XL™

Shmoo tool. The features that make AppsShmoo a great device

characterization tool include the accumulated Shmoo capability,

one-click import and export of ASCII outputs, easy tracking of

input parameters, command-line Shmoo, and one-click margin.

When installed, this .exe file will integrate into Datatool to allow

AppsShmoo to work with all device programs without requiring

explicit references.

Session 10/C: 2:00 – 2:30

IG-XL™ UltraFLEX™ CharacterizationLibraryAnne Marie Guray, Broadcom; Vivian Wang, Teradyne

When a test program is first developed for production, patterns

and timing generated by designers are usually not optimized for

characterization. Many times, timing characterization involves a

Session 10: 1:00 – 2:30A Golden Eye on Characterization

DIGITAL relationship between two signals (i.e., setup, hold, delay, and so

on). Specified timing involves capture of both signals to get the

desired results. In the past, getting these results involved the

development of custom interpose functions to calculate and data-

log data. To optimize the process, a reusable library which con-

tains commonly used functions was developed. The library can be

ported easily into IG-XL test programs and save time for test engi-

neers who will no longer need to develop custom routines.

BREAK: 2:30 – 3:00

Session 11/A: 3:00 – 3:30

IG-XL™ STIL BridgeMichael Cavallini, Julia DiChiaro Teradyne

In this paper, the author will describe the add-in application for

IG-XL test platforms and how to use it. The add-in allows the user

to convert the IEEE Standard Test Interface Language (STIL) to

Teradyne’s IG-XL test language and convert it back to STIL.

Session 11/B: 3:30 – 4:00

Proper PPMU Route Sequence toMinimize Glitches at the DUTZuyan Liang, Shams Syed, Teradyne

This paper will describe the PPMU connect and disconnect require-

ments during customer or checker jobs. Uncontrolled PPMU con-

nection sequences produce transients that may cause device dam-

age and PPMU latch up. A few customers have raised concerns

about the transients at the DUT. Current customer templates were

used to quantize transient levels. To minimize transients during

PPMU routing, function calls to the current templates were modified.

Session 11/C: 4:00 – 4:30

Extended Characterization Method forthe J750™Deyan Karastoyanov, Infineon Technologies

Semiconductors are getting smaller, faster, and have more fea-

tures. These improvements bring new requirements for test and

characterization. The characterization ability of the J750 is limited;

it cannot run pre-condition and post-condition tests. In this paper,

the author will describe a DUT that requires this type of character-

ization and a technique that will resolve the problem.

SURVIVOR PARTY: 5:30 – 7:00

Session 11: 3:00 – 5:00Testing is Forever

20

MIXEDSIG

NAL

BREAKFAST: 7:00 – 8:00

WELCOME: 8:15 – 8:45

KEYNOTE I: 8:45 – 9:30

KEYNOTE II: 9:30 – 10:15

BREAK: 10:15 – 10:30

Session 1/A: 10:30 – 11:00

Jitter Testing with Dig_Cap Joyce Ng, Kevin Walt, David Yin, Broadcom

This paper will describe how to measure jitter on digital pins using

Dig_Cap with VB code.This technique can be used for multiple

tester platforms, and has been implemented on one of the prod-

ucts in production at Broadcom.

Session 1/B: 11:00 - 11:30

What Is and How to Use Learn Mode Michael Cavallini, Brent Herling, Kent Magnuson, Teradyne

Have you ever wondered why a tester would have the capability

to learn the outputs of a pattern? If so, this paper is for you. It

will describe the learn mode on the FLEX™. In addition, the

authors will explore one of the many reasons to use learn mode,

the time it saves, and the programming necessary to implement it.

Session 1/C: 11:30 – 12:00

FLEX™ DSSC vs. ADB Bus Kevin Cheng, Jerry Hsieh, Teradyne

To reduce the cost of test for the complex/high performance

ADC/DAC on the FLEX, it is very important to assign a tester

resource when doing loadboard layout. To minimize the DSSC

used for the digital slot, it is necessary to take care of the pin

assignment, especially with multisite implementation. In this pres-

entation, a guideline will be provided for coding the DSSC when

serial/parallel mode is used. The DSSC loadboard design will also

be discussed. In addition, the problems encountered by the

authors and their countermeasures will be addressed.

Session 1: 10:30-12:00Q’s Lab

LUNCH: 12:00 – 1:00

Session 2/A: 1:00 – 1:30

Advanced Measurement Methods ofHysteresis Featured in Mixed-SignalIC Chips Weishu Wu, Texas Instruments

Hysteresis is a common parameter in many mixed-signal IC chips.

To determine the exact amount of hysteresis is often time-con-

suming because two searches for two transit points are involved.

To reduce test time, a novel binary method that searches both

transit points concurrently has been implemented in Catalyst™-

based test programs. To take advantage of the source memories

and ramping capability of the FLEX™ testers, a search method

that utilizes asynchronous trigger of DCVI by DCTime has been

implemented. Test time can be reduced further when the test pro-

gram is moved from Catalyst to FLEX.

Session 2/B: 1:30 – 2:00

The Implementation of FouriereXtended Transform (FXT) in IG-XL™Edmond Tan, Shu Xia, Teradyne

This paper is a follow-up to the TUG 2006 paper titled Incoherent

Sampling without Spectrum Leakage, Is It Possible?. When coher-

ent sampling is not achievable, FXT eliminates spectrum leakage

by demodulating the fractional portion of the non-integer number

of captured cycles. Since FFT-based testing is widely used in ana-

log and mixed signal testing today, this technique has received a

lot of attention. This paper will implement FXT into IG-XL as a uni-

versally functional VBT method that works transparently and con-

sistently like other standard DSP methods to calculate dynamic

results such as SNR, THD, SINAD, SFDR, and so on.

Session 2/C: 2:00 – 2:30

Understanding IG-XL™ DSPEnhancementsHmayak Dravatshyan, Scott Therrien, Teradyne

This paper will discuss FLEX™ Family DSP performance considera-

tions that need to be understood in order to write the most effi-

cient DSP procedures, as well as symptoms and remedies for the

most common issues that users encounter when working with

DSP procedures. The paper will also touch on topics such as

understanding DSPWaves and improvements made to them in IG-

XL version 6.10 and how to minimize memory usage in DSP pro-

cedures. In addition, the authors will present an overview of the

global variable feature for DSP procedures.

Session 2: 1:00 – 2:30Q’s lab

21

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BREAKFAST: 7:30 – 8:30

Session 4/A: 9:00 – 9:30

Use Half of ADC Bits Output toReconstruct Waveform for DynamicTestingAdonis Chang, Teradyne

This DSP algorithm needs only half of ADC bits output for pro-

cessing which means that half of the digital captured pins on par-

allel output devices or half of the captured memory on serial out-

put devices are needed. For parallel output devices, the digital

captured pins need to run below 25MHz on the J750 if the ADC

device is more then 16 bits output. When this DSP algorithm is

used on the J750, it will no longer have this restriction and will be

capable of supporting tests of 32-bits ADC up to 50MHz. For seri-

al output devices using this DSP algorithm, only half of the cap-

tured memory size previously required is needed, resulting in

twice the captured memory size. If the ADC output can be modi-

fied to use this DSP algorithm on the J750, it will be capable of

testing ADC devices up to 100MHz.

Session 4/B: 9:30 – 10:00

Improving INL DNL Repeatability Steve Matej, Jim Ptasinski, Texas Instruments; Kent Magnuson,

Teradyne

The uncertainty of sample location reduces measurement preci-

sion and repeatability from run-to-run or tester-to-tester. This

paper will examine some steps to create better repeatability when

measuring INL DNL on an ADC device.

BREAK: 10:00 – 10:30

Session 4: 9:00 – 10:00How Many Bonds Can You Convert? I

Session 5/A: 10:30 – 11:00

Micocontroller-Based Servo Loop forADC Linearity TestingShu Xia, Teradyne

ADC linearity testing measures the transition points of digital

codes. Servo loop technique is widely used in testing the linearity

of high resolution (14-bit, 16-bit, and more) analog to digital con-

verters. However, current solutions are using either test programs

or sophisticated pattern microcodes to control the servo loop

operations. They also rely on expensive AC source or digitizer

instruments. This paper will propose a microcontroller-based low

cost and intelligent servo loop solution whose operation is fully

handled by the firmware inside the microcontroller. Hence, this

solution will not only simplify the programming, but can be used

on a pure digital tester.

Session 5/B: 11:00 – 11:30

Undersampling Using Beat Frequency(Theory and Practice)Ching-Chia Tien, Teradyne

When facing the limitation of the digitizer, engineers are forced to

test the signal higher than the Nyquist frequency. The traditional

undersampling method uses one unit test period plus a small

delta to walk through the waveform, which is prone to droop

because of the low frequency jitter. In this paper, the author will

describe how to test high frequency signal using beat frequency.

Session 5/C: 11:30 – 12:00

Testing a Correlated Double SamplingADC on the FLEX™Lai-Choon Chan, Teradyne

The general rule for testing an ADC is to use an AWG with a

higher resolution than the device being tested. In the event that

the instrument resolution is inadequate, a segmented ramp test

technique is sometimes used. In converter technology, resolution

decreases as sampling frequency increases.

The challenges in testing a correlated double sampling (CDS)

ADC are twofold. They are: 1) the AWG has to sample at twice

(or higher) the rate of the DUT because it has to generate a refer-

ence level and a data level for each ADC sample clock, and it

should preferably have higher resolution; and 2) since the refer-

ence (black) level has to be generated for each test sample, the

output of the AWG must be able to span the entire dynamic range

throughout the test. Segmented ramp testing cannot be employed.

This paper will investigate three techniques to test a CDS ADC

and will describe their strengths and weaknesses. The techniques

are VHFAC source; BBAC source + DC30; and high-speed, high-

resolution DAC + DSSC source.

LUNCH: 12:00 – 1:00

Session 5: 10:30 – 12:00How Many Bonds Can You Convert? II

23

BREAK: 2:30 – 3:00

Session 3/A: 3:00 – 3:30

Get the Best of your High-DensityPMUDirkJan Stuij, Salland Engineering; Francois Deun, Teradyne

As part of the OpenFLEX initiative, Salland Engineering developed

the High-Density PMU (HDPMU). This highly integrated instru-

ment provides the FLEX™ and microFLEX™ up to 192 VI chan-

nels to any mixed-signal DUT. This paper will introduce the basic

features of the HDPMU (ForceV/I, Measure V/I) and describe the

advanced techniques like channel merging, external/local sensing,

focused cal, PSet usage and fast readback measurement. Written

like a cookbook, this paper can be used as a reference for begin-

ners to advanced HDPMU test engineers who are developing on

the FLEX.

Session 3/B: 3:30 – 4:00

AC Characterization of BBAC™ andPOOL2 Signal Sources Don Jussaume, Analog Devices

This paper will examine the AC Performance of the FLEX™ BBAC

Signal Source and the POOL2 Function generator. SNR, THD, and

SINAD performance will be characterized at specific frequencies

using the FLEX internal ‘loopback to capture’ feature and an inde-

pendent spectrum analyzer. Amplitude linearity of the BBAC

source will also be characterized. In addition, test methods, pro-

gramming examples, and data result summaries will be presented.

Session 3: 3:00 – 5:00Tools

MIXEDSIGNAL

Session 3/C: 4:00 – 4:30

Automated Test Program ConversionK. Padma Priya, Vinai Kumar Singh, Teradyne/HCL Technologies

Due to the growing complexity of integrated mixed-signal video

devices and shorter time-to-market cycles, the test program con-

version process needs to be automated to reduce the program

development time. This automated process will be most beneficial

when the customer moves from one tester platform to another. In

this paper, the authors will introduce the automated converter

tool which will convert nearly 70% of the test program and pat-

terns and provide a guideline for manual modification for the

remainder of the test program. This user-friendly tool will be

developed in the form of frameworks so that future conversions

can be automated quickly.

Session 3/D: 4:30 – 5:00

Understanding DCTime Larry Lovell, Teradyne

One advantage of the FLEX™ system is its capability to have mul-

tiple instruments on each board. Each DC30, DC75, and DC90

has the advantage of two DCTime instruments onboard. This

advantage is often misunderstood, especially when the engineer is

migrating from the IMAGE™-based platform. In this presenta-

tion, the author will describe some of the pitfalls encountered

when using DCTime, offer some insight for its proper use, and

provide some alternatives when necessary.

TERADYNE PARTY: 6:00 – 9:00

22

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Poster Presentations/Roundtable Sessions: 4:45 – 7:00

Poster 1

Advanced Techniques to OvercomeTester Limitations When Testing ADCsAarthi Sundararajan, Tessolve Services

This paper will substantiate the use of inexpensive crystal filtering

techniques in providing remarkable noise filtering capabilities to

aid ADC testing when using low resolution tester resources. In

addition, the author will describe how to expand the tester’s DSP

library by adding some simple algorithms.

Poster 2

Another POP Story Kent Magnuson, David Pickard, Teradyne

This paper will describe how to take advantage of the Pattern

Oriented Programming (POP) available on the FLEX™ by convert-

ing an existing program to the tester. It will examine the time

saved when using POP compared to non-POP.

Poster 3

Increase Time for Coffee Breaks –Reduce Time for Test Developmentand Debug Roy Chorev, Ali Syed, Teradyne

Test engineers realize that the time required to develop a test pro-

gram is becoming as important as test time. With the increasing

need to get to market faster, test engineers require development

and debug tools that improve their efficiency, create highly opti-

mized test programs, and allow time for coffee breaks! Integrated

into the existing FLEX™ IG-XL™ architecture are new develop-

ment/debug tools that will help test engineers improve their pro-

ductivity.

Through a variety of test examples and illustrations, this paper

will describe how test development and debugging productivity

can be improved for engineers who create mixed-signal test pro-

grams. Among the topics covered are tools to generate VBT code

from instrument debug displays and create PSet and Signal

Definitions from standard IG-XL DataTool Sheets.

Poster 4

Incorporating the J750™ into theElectrical and Computer EngineeringCurriculum — MSO OptionRobert Weber, Iowa State University

This paper will describe an extension of a testing curriculum in the

Department of Electrical and Computer Engineering at Iowa State

University (ISU), Ames, based on the addition of a Mixed-Signal

Option (MSO) to the J750 platform. Several different events coa-

lesced to enable the establishment of a testing curriculum at ISU.

In the early 1990s, a center for mixed-signal and analog VLSI

design was formed at ISU. In early 2000, Teradyne and ISU initiat-

ed discussions on the need to augment the VLSI design center

with the capability for high-speed VLSI testing. In late 2002,

Teradyne donated a J750 with 64 channels of 100 Mb/s digital

capability to ISU. After continued interaction, Teradyne donated a

Mixed-Signal Option (MSO) for the J750 in late 2005. In March

2006, ISU alumni working at Teradyne conducted an on-site train-

ing for the MSO. A senior design team is writing an operating

manual for the use of students for the MSO.

Round Table 1

Update on IG-XL™ HelpJohn Buckley, Mike Gill, Teradyne

Round Table 2

DTV/HDTV Testing on the UltraFLEX™ — Q&AFang Xu, Teradyne

Q&A for Session 6/A

Round Table 3

OpenFLEX

Round Table 4

TAG Table

25

Session 6/A: 1:00 – 1:30

Clock Jitter Effect for Testing DataConvertersJin-Soo Ko, Teradyne

Estimating data converter noise by clock jitter performance is not

a simple task. In most cases, jitter vs. noise tables or some compli-

cated calculations are used. Since the estimate is related more to

the input and output frequency than the clock frequency, this can

create confusion for the test and design engineers.

The author has suggested a simple noise power calculation

formula by changing the clock jitter RMS level. The formula was

tested with a 14-bit DAC using a jittered clock source. The calcu-

lation was verified using a simulation model by DSP. This formula

provides a simple way for engineers to design and test data con-

verters.

Session 6/B: 1:30 – 2:00

Conversion of ADC Ramp Tests fromthe J750™ to the UltraFLEX™Russell Long, Freescale Semiconductor; Tim Scanlon, Teradyne

As part of an overall program conversion project, a series of ADC

ramp tests were converted from the J750 to the UltraFLEX. The

primary instruments used on the J750 platform were the MSO,

MTO and DPS. The target instruments on the UltraFLEX platform

were the BBAC, DSSC Capture, and DCVI. In addition, differ-

ences in the software components such as Test Procedure ele-

ments, instrument-specific VB code, and DspWave objects were

addressed. The primary benefit of this conversion was improve-

ment in throughput and accuracy.

Session 6: 1:00 – 2:30 How Many Bonds Can You Convert? III

MIXEDSIGNAL

Session 6/C: 2:00 – 2:30

Testing High-Speed Mixed-SignalDevices on the UltraFLEX™Daniel Weinberg, Analog Devices

This paper will present the findings from an evaluation of the

UltraFLEX High-Speed Digital Subsystem and its suitability as a

platform for testing high-speed mixed-signal devices. A Dual, 16-

bit, 1GSPS DAC was used to evaluate the system's digital capabili-

ties to provide clock and data signals for the DUT and the per-

formance of the GigaDig as an AC capture and analysis mecha-

nism. In addition, the test execution times to existing test solu-

tions will be compared.

BREAK: 2:30 – 3:00

Session 7/A: 3:00 – 3:15

Semiconductor Business Meeting

Session 7/B: 3:15 – 4:00

Semiconductor Engineering Update

Session 7/B: 4:00 – 4:45

Semiconductor Open ForumDiscussion

VENDOR FAIR: 4:00 – 7:00

Session 7: 3:00 – 7:00Engineering Update, Round Table/

Poster Sessions & Vendor Fair

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Session 10/A: 1:00 – 1:30

It Pays to Own a FLEX™Xnorikazu Sugano, Sony; Gavin Gao, Jack Chen, Teradyne

In this paper, the authors will describe a key customer’s conver-

sion to the FLEX platform and its advantages over the customer’s

original platform. With the FLEX, test time is reduced 70%. The

capabilities on the FLEX that make this major reduction in test

time possible include its multisite flexibility, DSSC, and parallel DSP

processing. The authors will describe the differences between the

instruments on the FLEX and the original platform, test solutions,

and how tests were done before and how they are done now.

Session 10/B: 1:30 – 2:00

Double Your Sampling RateSee Hwa Goh, Teradyne

Using one DC30 channel, the maximum capture sampling rate of

100kHz can be doubled with the aid of another DC30 channel.

Connect the two DC30 channels to the point of capture and set one

DC30 channel to capture at 100kHz and one to capture at 100kHz

at about 5us later. Both captured data can be interleaved accordingly,

resulting in twice the waveform samples. This method, as described

by the author, will achieve an effective capture rate of 200kHz.

Session 10/C: 2:00 – 2:30

Controlling the Flow — ImplementingComplex Test Program Flows in theIG-XL™ Flow TableJohn Arico, Analog Devices

Most test programs require only a simple, sequential flow.

Sometimes, however, a more complex route through the test list is

required. Although this can be accomplished by writing complex

program code underneath the test instances, the result is less

portable code. Portability can be maintained, though, if test flow

decisions are made at a higher level, instead of in the program code.

The IG-XL Flow Table provides many features through which a very

complex test flow can be implemented using simple, more modular

test instances. This paper will discuss some of these features and will

provide practical examples of complex Flow Table programming.

BREAK: 2:30 – 3:00

Session 11: 3:00 – 5:00UltraFLEX Concepts

Session 10: 1:00 – 2:30Spectre's World Domination Concepts III

Session 11/A: 3:00 – 3:30

New Approaches to Pulse TrainIntegrity TestingScott Therrien, Fang Xu, Teradyne

Testing integrity of PLL or clock circuits is often a difficult challenge

requiring very high speed sampling instrumentation. Typical solu-

tions use an undersampling technique to reconstruct the time

domain aspects of the pulse train output for analysis. But what

happens if there are missing pulses in the pulse train? Will an

undersampling technique be a robust solution in such a case? This

paper will show how one can utilize a mathematical solution to

accomplish the task of testing pulse train integrity using frequency-

based measurement instrumentation instead of time-based sam-

pling instrumentation. In addition, mathematical principles as well

as actual tester characterization data will be discussed.

Session 11/B: 3:30 – 4:00

Using DCTimeHP to Measure SpreadSpectrum Clock Generation (SSCG) ModulateClock Frequency on the UltraFLEX™David Wu, Teradyne

This paper will describe an inexpensive solution to test SSCG by

implementing two DCTimeHP time stamps on the UltraFLEX. This

presentation will provide a guideline to use DCTimeHP to stamp

events for SSCG into Dspwave for analyzing the next step. It will

point out how to measure SSCG and what the spec limitation is

for DCTimeHP on this application.

Session 11/C: 4:00 – 4:30

UltraFLEX™ DSSC Test Time OptimizationTyler Tolman, Broadcom; David Lam, Teradyne

During test program development on the UltraFLEX tester, DSSC pro-

gramming is a very convenient tool to program and test the device.

However, getting the tool to work efficiently can be a challenge. This

paper will explain the techniques used in both DSSC pattern and VBT

programming to reduce test time significantly for DSSC applications.

Session 11/D: 4:30 – 5:00

An Easily Integrated, Efficient Approachfor Wideband Captures Using TurboAC™Andrew Varley, Teradyne

Wide bandwidth measurements usually require the user to take mul-

tiple captures and re-center the local oscillator between each acquisi-

tion. Multiple captures have always meant longer test times, but this

paper will describe how automated multiple captures can acquire

wide bandwidth spectrums with fast test times and high perform-

ance. The program is easily portable, which allows users to plug-n-

play this technique into any test program to capture the desired

wideband spectrum. DSP reconstruction interweaves the multiple

captures together to generate a single plot of the total spectrum.

Efficient test time and high performance for wideband spectrums

is possible using TurboAC and multiple down conversion captures.

SURVIVOR PARTY: 5:30 – 7:00

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BREAKFAST: 7:30 – 8:30

Session 8/A: 9:00 – 9:30

Programming Pattern Vectors andDSSC on MUX Mode for FLEX™Yan Jin, Jason Miller, Haibo Zhang, Texas Instruments; Cliff

McCallister, Teradyne

The HSD200 can run at only 50MHz without a license for a high-

er frequency. To run the serial port above 50MHz and avoid the

extra license, a MUX mode design and programming method is

needed. In this paper, the authors will introduce the methodology

to program the serial port to write at 80MHz using digital pat-

terns, and read at 80MHz using DSSC capture, both at MUX

mode. The details of hardware design, digital timing program-

ming, DSSC capture setup, pattern programming at MUX mode,

and data manipulation from dual channel DSSC capture will be

discussed.

Session 8/B: 9:30 – 10:00

High-Speed Dynamic ADC Test on aLow-Cost Digital TesterMile Cheung, Claus Dworski, Infineon Technologies

With the trend to integrate analog or RF parts on one silicon chip,

the normal approach is to test the device on more than one tester

platform, namely digital, mixed signal and RF. However, this

approach will increase the overall cost of test or reduce EBIT.

Therefore, a simple and effective reusable solution is needed.

In this paper, the authors will demonstrate and describe the

implementation of a high-speed direct digital synthesizer add-on

circuit on the J750™ test system. As a result, a good resolution

sinusoidal wave up to 40MHz (14-bit, 400MSPS internal clock

speed running on the DDS) will be generated using the J750

MTO option to capture the device outputs and perform certain

DSP functions (e.g., FFT, Digital Filtering, and so on). The demon-

stration will show that a high-speed dynamic ADC test can be

performed on a low-cost digital tester.

BREAK: 10:00 – 10:30

Session 8: 9:00 – 10:00Spectre's World Domination Concepts I

MIXEDSIGNAL

Session 9/A: 10:30 – 11:00

How to Specify Units and Scale TestLimits in the IG-XL™ 5.1 Flow Sheet Eric Buvry, Teradyne

IG-XL 5.1 supports limits in the flow sheet. Without impacting test

time, a custom VB module can support unit limits and scaling from

the same flow sheet. When using POP, a routine will help to reduce

the VB code to be written. In this paper, the author will describe

how to specify units and scale test limits in the IG-XL 5.1 flow

sheet.

Session 9/B: 11:00 – 11:30

Advanced Parallel Trim Algorithm withPOOL PVM Auto-CalibrationJared Jones, Analog Devices

Multisite, parallel, fast, and accurate test techniques are the goals

in keeping costs low and meeting customer demands. Trimming

the product helps to guarantee high performance. Complicated

trim algorithms challenge the test engineer to meet these goals.

This paper will describe techniques to achieve these goals of the

test program. “Flattening” a complicated trim flowchart and

using the IG-XL™ SiteVariants allow the test engineer to imple-

ment a parallel multisite trim flow even when sites require differ-

ent trim steps. Using a fast measurement instrument which

measures multiple sites in parallel is desired. Automatic calibration

of the faster instrument with the ideal measurement instrument

helps to meet accuracy requirements.

Session 9/C: 11:30 – 12:00

Improving Test Efficiency Using DFTConcepts: A Potpourri of Ideas fromServo Devices Sundeep Desai, Texas Instruments

DFT has become a cliché in test parlance and has attained a

rhetorical value in its implementation. By providing practical exam-

ples for DFT usage in SPG mixed-signal designs, this paper will dis-

prove that cliché. A careful distinction will be made between ideas

that deal primarily with observability and controllability issues to

ones that employ authentic changes to architecture and tech-

nique. Thus, the possibilities that will be covered run the gamut

from having test access to observe latched over current signals on

power FETs to converting time measurements to DC. In addition,

a number of ideas that cannot yet be implemented will also be

included, e.g., voltage divider ratios on hysterectic comparators.

LUNCH: 12:00 – 1:00

Session 9: 10:30 – 12:00Spectre's World Domination Concepts II

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Session 2/C: 2:00 – 2:30

Sync Panel, Uncovering IssuesWalter Oldham, Derek Sam, Teradyne

The market window for today’s devices is much tighter than in

the past. As a result, the time to develop and debug the HW and

SW components to test devices in production has also shrunk. As

test engineers, we seek debug tools that allow us to get our jobs

done faster and more effectively. Using the Sync Panel and an

oscilloscope on the FLEX™ platform provides an efficient means

to debug device setups and tester signals. This paper will demon-

strate the use of the Sync Panel in a variety of use cases.

BREAK: 2:30 – 3:00

Session 3/A: 3:00 – 3:30

Faster Ramps and Higher Yields inthe Pursuit of 0 DPMRichard Ackerman, Becki Watt, Mentor Graphics

Integrated circuit manufacturers are under constant and increas-

ing pressure from their customers to reduce costs; this pressure

makes it imperative they produce high-yielding, high-quality

devices with a quick production ramp. Although particulate

defect rates are relatively stable, yields continue to fall with each

process generation as systematic, or feature dependant, defects

become the predominant failure mechanisms. Yield improvement

in the presence of these defects requires design corrections.

Maintaining profitability in this market requires high-quality tests;

accurate, high-volume diagnosis of production failures; and the

development of a feedback process where design parameters are

driven by production data. In this paper, the author will describe

ways to produce higher yields with faster time to market.

Session 3: 3:00 – 5:00Test Quality: Ready to Ramp?

Session 3/B: 3:30 – 4:00

Force Fail Tool, AcceleratingProduction ReleaseWalter Oldham, Teradyne

Releasing a test program to production is never an easy task for

test engineers. They must ensure the program is stable and meets

quality requirements while responding to other demands, some of

which may be in conflict, such as meeting aggressive schedules

and hitting yield and performance targets.

The Force Fail Tool described in this paper is targeted to help

test engineers with the production release process. The tool forces

failures on some or all limit checks in a program for a specified

site automatically. It will help test engineers check for site-to-site

interactions, site shutdown issues, and improper reset conditions

quickly.

Session 3/C: 4:00 – 4:30

Relays — Conquering the TestEngineer's Nemesis Paul Nelson, Elisa Woo, Teradyne

Instrument connections continue to present test time challenges

and plague reliability on instruments that use relays for DIB con-

nections. The DC instrument hot-switching detection tool has

been deployed to aid in relay use education. This paper will

describe the highlights and lowlights from the first year of tool

usage in field applications; it will describe the tool and how les-

sons from it can be applied to other instruments and DIB relays.

Determining the best methods for using different instruments and

programming structures based on the instruments’ specifications

and documentation to optimize the connections will also be cov-

ered. These methods will also include techniques that will put

FLEX™ instruments into benign states rather than repeating dis-

connects and connects.

Session 3/D: 4:30 – 5:00

Lowering DPPM without IncreasingBurn-in or Test Time Jeff Bibbee, OptimalTest

Common sense leads test and product engineers to believe the

only way to lower DPPM is to either increase burn-in or increase

test time by introducing additional stress tests. Using an emerg-

ing technology named Test Management Solutions (TMS), DPPM

can be lowered significantly while burn-in and test time are actu-

ally reduced. Case study results show that TMS and its inherent

rule sets push DPPM toward zero.

TERADYNE PARTY: 6:00 – 9:00

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BREAKFAST: 7:00 – 8:00

WELCOME: 8:15 – 8:45

KEYNOTE I: 8:45 – 9:30

KEYNOTE II: 9:30 – 10:15

BREAK: 10:15 – 10:30

Session 1/A:10:30 – 11:00

Reduce Program Development Timefor the Automotive Market on theFLEX™Dominique Le Roux, Teradyne

Reusing a proven working code will dramatically reduce test time

development for a new test package. In this paper, the author will

describe a set of functions, including the trim and fuses descrip-

tion, best fit trim selection, and memory management, to be

reused as a standard. The capability to record the trim effect will

allow fine tuning according to the lot parameters.

Session 1/B:11:00 - 11:30

VBT or POP? How to Decide theImplementation of a Mixed-SignalTest Fast Cristian Cesarini, Filomena Ricci, Teradyne

When approaching the implementation of a mixed-signal test, the

dilemma is VBT or pattern. At first glance, it is not always easy to

determine whether testing in a pattern will lead to better execu-

tion time as the time overhead associated with pattern start and

pattern halt can jeopardize it. Furthermore, pattern may increase

test complexity, making it difficult to debug. The goal of this

paper is to simplify the decision process by providing a few guide-

lines to help you make a good approximation of the expected

time overhead. User programming style can also affect start pat-

tern overhead. Keeping in mind a few IG-XL™ behaviors will help

to minimize that overhead as well.

Session 1: 10:30-12:00Accelerating Program Development and

Characterization

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Session 1/C: 11:30 – 12:00

Better Programming on the FLEX™Tester for Easy Debug and EasySwitch from Characterization toProduction TestElie Trognon, Freescale Semiconductor

Test program development time is always a big challenge. The

same test program is modified to debug and characterize the

device and finally test it in production. Therefore, the step from

characterization to production requires a long development phase

which was not planned during the first phase coding. This paper

presents techniques on the FLEX that allow easy debugging and

switching from characterization to production test.

LUNCH: 12:00 – 1:00

Session 2/A: 1:00 – 1:30

My Pattern is Running — Can I StillDebug?Lorenzo Simonini, Elisa Woo, Teradyne

In most power and mixed-signal test programs there is a need for

handshaking between pattern and VBT program flows. On the

FLEX™ there are different ways to implement the handshaking

with different tradeoffs between test time and ease of debug,

namely KeepAlive™ versus CPU loops. This paper will address the

different tradeoffs and also present new software techniques for

users to interact with FLEX DC (DC30, DC75, DC90) instruments

via debug displays while a pattern is running during CPU loop

execution.

Session 2/B: 1:30 – 2:00

Using the PLMeter as a DebugResourceKrista Bertsch, Teradyne

Oftentimes there are unused resources in your tester for any one

device. Since the resource is already in place, how can we use it

to our advantage? The PLMeter is one good example of a

resource that can be useful as a debug tool. The PLMeter can

function as an onboard scope, offering more advantages for low

pin count devices with short test times. Because the PLMeter has

a capture memory of 4096, it can capture an entire test program

that is 500ms long with a resolution of just over 120us. In this

paper, the author will describe the advantages and disadvantages

of using this technique, as well as providing the code to set up

the meter. In addition, the author will discuss an example LDO

program that was debugged using this technique.

Session 2: 1:00 – 2:30Accelerating Program Development and

Characterization

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selectable crossover types. However, before users can take advan-

tage of this flexibility to solve their testing problems, they need to

know how each type works and which type to use in certain test

situations. This paper will describe when to use which crossover

type so test program developers will have the best chances of

using their choices successfully.

Session 6/B: 1:30 – 2:00

Paralleling DC90XP VIs to AchieveCurrents Beyond Merged Mode Eric Bergeron, Maurilio Fabiano, Teradyne

To deliver more current than a single DC90 VI channel, the user

can merge channels and not worry about sharing current among

the channels or adding DIB components that compromise voltage

forcing accuracy. The DC90XP, a new version of the DC90, fea-

tures a different method for paralleling as many as 16 channels.

This method requires programming a new Current Limit Mode to

prevent overheating the VI. No DIB components are required. This

paper will describe the difference between Merged Mode and

paralleling and how to parallel channels for currents up to 32ADC

or 160Apulsed.

Session 6/C: 2:00 – 2:30

Introduction to the DC90XP — A HighPower Instrument Optimized for theAutomotive MarketCristian Cesarini, Larry Klein, Teradyne

The automotive device market is changing. Devices requiring

higher currents, better dynamic performance, and higher

throughput are being produced in volume. These devices take

advantage of newer FET technology to switch higher currents at

faster on and off rates than previous generation devices. In addi-

tion, the volume of parts being designed into each automobile

continues to climb, increasing production volumes for these parts

and driving requirements for shorter test times. The DC90XP is an

instrument designed to address these needs in the automotive

market. It is an updated and improved version of the DC90™

instrument which addresses the above needs while maintaining

compatibility with the DC90. This paper will describe the require-

ments of the automotive device test market and will detail the

features of the DC90XP to address them. Technical changes will

be described, along with examples of how to use them and the

impact they will have on device test.mechanism. In addition, the

test execution times to existing test solutions will be compared.

BREAK: 2:30 – 3:00

Session 7/A: 3:00 – 3:15

Semiconductor Business Meeting

Session 7/B: 3:15 – 4:00

Semiconductor Engineering Update

Session 7/C: 4:00 – 4:45

Semiconductor Open Forum Discussion

VENDOR FAIR: 4:00 – 7:00

Poster Presentations/Roundtable Sessions: 4:45 – 7:00

Poster 1

Implementating a SetupManager VBClass to Simplify PSet-BasedInstrument ProgrammingManfred Graf, Teradyne

The SetupManager VB class offers the possibility to create differ-

ent types of instrument setups. The instrument setups such as

DCVI PSets and HVD signals are defined for each IG-XL™ test

instance in one single setup file as ASCII text. In addition, the

SetupManager class supports loading specific instrument settings

for each test instance. Advantages of this technique include

improved reusability, a modular programming style, and a reduc-

tion in test program development time. In addition, the

SetupManager tool supports the easy creation of instrument

setups and is being extended to auto generate the setup informa-

tion from device specifications. In this paper, the author will

describe this technique and how to implement it.

Round Table 1

Update on IG-XL™ HelpJohn Buckley, Mike Gill, Teradyne

Round Table 2

DTV/HDTV Testing on the UltraFLEX™ — Q&AFang Xu, Teradyne

Q&A for Session 6/A

Round Table 3

OpenFLEX

Round Table 4

TAG Table

Session 7: 3:00 – 7:00Engineering Update, Round Table/

Poster Sessions & Vendor Fair

31

BREAKFAST: 8:00 – 9:00

Session 4/A: 9:00 – 9:30

How to go Beyond 30V @ 100mA withonly Two DC30 ChannelsDean Garrison, Sherry Sponheimer, Teradyne

Two customers asked whether it is possible to drive a DC30 to

35V @ 200mA. Another customer asked if he can test a -48V

DC Hot-Swap controller with a DC30. Yet another asked how to

get a DC30 to act more like a High Voltage DPS (Device Power

Supply 30V @ 200mA).

This paper will describe how to achieve higher than 30V @

500mA using only a single DC30 channel and a few additional

parts. The paper will also present one way of achieving this goal

schematically, a simple FPGA controller to allow low current IDDQ

measurements without glitches, and how the DC30 channel can

be adapted for use as a DPS.

Session 4/B: 9:30 – 10:00

Parallel Test Solution for a HighCurrent PROFET Device Using FLEX™DC90 DEMUX Petar Fanic, Tzong Sheng Ng, Infineon Technologies

Due to the limited mounting area on the DIB, getting accurate

test results is difficult. Using the FLEX DC90, the authors devel-

oped a parallel test solution that reduces the number of relays on

the board (eliminating high current relays) and improves test accu-

racy. Work required to maintain the boards should be reduced as

well.

In this paper, the authors will describe how they measured

four 80A devices using four DC90 cards (16 DC90 sources) simul-

taneously. Tests up to 40A were done in parallel. Tests up to 80A

were done for two devices simultaneously without relays on the

board. There was no connection between the devices; the devices

were electrically isolated and tested separately.

BREAK: 10:00 – 10:30

Session 4: 9:00 – 10:00Welcome to Power: High Voltage/

High Current Test

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Session 5/A: 10:30 – 11:00

Tutorial — DC90™ VoltageCompliance, Part 1: Insider Look atthe DC90 Power Model Cristian Cesarini, Arthur Russell, Chi-Heng Wang, Teradyne

The DC90 VI offers users flexible control over how power is dis-

tributed and dissipated within a channel. Waveform syntax per-

mits precise control over drive waveforms. The instrument supply

rails are continuously variable and, with the new IG-XL™ release,

users have almost complete control over these rails (no additional

padding of Voltage Compliance). Because of this flexibility, users

may bump up against several different specified capability limits,

such as internal thermal limits, slot power limits, and pulse

width/current limits; but, they may not always know why or how

to fix them. This paper will describe the hardware's capabilities

against these various constraints. In addition, it will introduce a

new software tool, DC90 VI Power Curve Tool, which will help

users understand and manage their performance against these

constraints.

Session 5/B: 11:00 – 12:00

TUTORIAL — DC90™ VoltageCompliance, Part 2: Are You Gettingyour Two Kilowatt's Worth? Cristian Cesarini, Arthur Russell, Chi-Heng Wang, Teradyne

DC90 VI Power Curve Tool is an interactive real-time calculator

that aids in test program development and debug. It validates

instrument parameters against the constraints for current ampli-

tude, pulse width, compliance voltage, DUT voltage, VI thermal

dissipation, and system level power constraints. In this tutorial, the

authors will describe the tool and how it works.

LUNCH: 12:00 – 1:00

Session 6/A: 1:00 – 1:30

When to Use Which V/I Crossover Typeon the FLEX DC90XP Mereen Mammen

Full four-quadrant automatic V/I crossover is one feature that

makes V/I instruments one of the most versatile tools for mixed-

signal, power, and automotive testing. There have been several

topologies employed in Teradyne instrumentation over the years,

and there are advantages and disadvantages to all of them. For

the DC90XP, the V/I instruments offer the choice of three user

Session 6: 1:00 – 2:30 Welcome to Power: High Voltage/

High Current Test

Session 5: 10:30 – 12:00Welcome to Power: High Voltage/

High Current Test

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Session 10/A: 1:00 – 1:30

Modulation Input Applications ExtendDCVI Applicability in POP Diego Koch, Alfredo.Stabile, Massimo Zambusi, Teradyne

DCVI modulation input allows efficient tuning of DCVI voltage

without requiring multiple patgen restarts and PSet adjustments.

This feature helps to overcome the DCVI lock-while-patgen-run-

ning limitation and allows real time DUT-controlled biasing. The

modulating source can be another voltage source or even a DUT

pin. Test time and DIB complexity can be improved. In this paper,

the authors will present actual applications for power manage-

ment device testing.

Session 10/B: 1:30 – 2:00

Octal-Site High Power Class-DAmplifier Interface Board Design Mike Chu, Yan Jin, Haibo Zhang, Texas Instruments

As the power of digital amplifier power stage devices increases,

the range of PVDD, Over Current (OC) protection on chips also

increases. In order to test these chips, instruments on the tester

provide very high voltage (as high as to 60v) and high current (as

high as 30A pulse). Because the device is switching at 400KHz

PWM, the ground bounce on HIB is significant, especially during

multisite parallel test. Without a good grounding scheme and

control, crosstalk between sites can cause device reference

changes, and may even cause device shutdown. The result will

make tests fail which will cause yield loss.

Texas Instruments has worked in this area for many years and

is the leader in the high power Class-D power stage market. This

presentation will review lessons learned from HIB design for high

power class-D amplifiers. In addition, different ground schemes

will be compared.

BREAK: 2:30 – 3:00

Session 10: 1:00 – 2:30Power Management

Session 11/A: 3:00 – 3:30

Reducing Wafer Testing Cost for theAutomotive Market on the FLEX™Jerome Mercier, Freescale Semiconductor; Francis Danel,

Teradyne

Increasing test parallelism is a proven, effective way to reduce the

cost of test. Since probe index times are significantly less than on

handlers, wafer testing is a very good candidate for high paral-

lelism. Advanced FLEX DIB design techniques, such as DIB access

and XOR, can also lower the hardware costs without impacting

measurement accuracy. In addition, vertical probe technology

offers significant advantages that improve the overall equipment

efficiency, such as quick repair operations, low-cost maintenance,

and small probe marks.

Session 11/B: 3:30 – 4:00

Speed Up Test Program Execution forDC Instrumentation Giorgio Calia, STMicroelectronics; Nicolino Tassara, Teradyne

DC instrumentation does not support background move (IIM).

However, for some programs, data moved from DC instruments

may be large enough to use a significant percentage of the total

test execution time. In addition, the time it takes for data process-

ing may be considerable and can be hidden during pattern execu-

tion. In this paper, the author will describe how to speed up test

program execution by exploiting DC instrumentation architecture

and multiple processing (Patgen and VBT). This technique allows

faster background data movement, and data processing.

Session 11/C: 4:00 – 4:30

Help! Where Do I Start in TestProgram Conversion?WL Chan, Dean Garrison, Teradyne

Many users have converted test programs from their legacy test to

the FLEX™, and then wonder why they don’t see much test time

improvement. Many users, with little to no experience in test pro-

gram conversion, tend to copy the legacy program lock, stock,

and barrel. This copying leads to programs with little test time

improvement for the same number of sites as run on the legacy

tester. This paper will attempt to show some of the pitfalls the

authors have observed in the conversions of a few legacy pro-

grams (Eagle) to the FLEX, i.e., Trim, TMU measurements, and

DUT protection.

SURVIVOR PARTY: 5:30 – 7:00

Session 11: 3:00 – 5:00Reducting Test Costs

33

BREAKFAST: 7:30 – 8:30

Session 8/A: 9:00 – 9:30

Challenges to Test an ADC in anAutomotive DeviceHugo Molina, Texas Instruments

This presentation will describe how to combine linearity data gen-

erated by the FLEX™ BBACSrc instrument and zero/full error data

generated by the FLEX DCSrc to calculate ADC Total Error.

DSPWave will be used to store this information. ADC total error

calculation formulas and methods to evaluate and modify arrays

will also be presented. INL/DNL calculations using histogram

method and best fit algorithms will be used.

Session 8/B: 9:30 – 10:00

An Easy Way for SPI Communicationvia DSSC Wei Chong Ng, Infineon Technologies; Nazlen Jabar, Teradyne

In recent years, the predominance of serial protocol interface or

SPI communication protocol has become evident. Many consumer

and automotive ICs rely on SPI for basic communication.

Eventually, this protocol will have to be used in test programs to

configure the devices. To simplify SPI signal programming and

improve debugging capability with Digital Signal Source and

Capture (DSSC), the authors created an SPI library. This paper will

describe this new test technique that shortens the test develop-

ment phase dramatically.

BREAK: 10:00 – 10:30

Session 8: 9:00 – 10:00Automotive SoC and IC Integration

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Session 9/A: 10:30 – 11:00

Airbag Device Testing on the FLEX™Jian-Wei Wang, Kenny Zhu, Teradyne

Cars today have more airbags which means more channels will be

designed in the airbag device. In addition, many other functional

blocks are combined with airbag channels which can complicate

testing. The FLEX system provides rich instrument resources to

implement tests for different function blocks such as a squib driv-

er, squib diagnosis, and ASIC. This paper will introduce airbag

device testing on the FLEX and will provide examples of typical

tests and circuits.

Session 9/B: 11:00 – 11:30

Octal-Site Final Test Concept forAutomotive Intelligent DistributedControl Products Johann Hilburger, Gerhard Knez, Olaf Neper, Freescale

Semiconductor

Intelligent Distributed Control (IDC) devices are gaining market

share in automotive electronics applications such as window lift

control and safety, mirror control, and headlight leveling. This

paper will analyze test strategies and cost scenarios for automo-

tive multi-chip System-in-Package (SiP) IDC products. It will

describe a cost-optimized octal-site final test (FLEX™) and gravity

handling (MT9928 Gravity Handler™) solution for high-volume

devices that combine microprocessor and analog technology in a

single package.

Session 9/C: 11:30 – 12:00

The Lowest Cost Method of IDDQTesting on the J750Satoshi Funakoshi, Teradyne

In microcontroller device testing today, the IDDQ test and analysis

is very important. However, it can increase test time significantly

when it is measuring hundreds or thousands per test item. This

presentation will introduce the fastest test method on IDDQ in

J750 using DPS Mout pin and CTO capture pin.

LUNCH: 12:00 – 1:00

Session 9: 10:30 – 12:00Automotive SoC and IC Integration

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Session 2/C: 2:00 – 2:30

Working with OpenFLEX™ — A Customer’s Experience ofDeveloping Test Solutions throughTeradyne’s OpenFLEX Office Omar Biabani, Sten Peeters, Teradyne

This paper will describe to potential customers how easy, rapid,

and practical it is to integrate their niche requirements into

FLEX™ architecture through the OpenFLEX initiative. This paper

will explain, from a customer’s point of view, the overall process

to develop customized instrumentation that leverages the

strengths of FLEX architecture.

The audience will learn about various product development

phases as experienced by a customer. A customer will share his

success story by elaborating on the following topics:

1. Building a relationship with the OpenFLEX office

2. Training, support, and services provided by the OpenFLEX team

3. Roles and responsibilities for each party

4. Best practices in product development

5. Best practices in project execution

6. Value of product certification

7. Teradyne/Customer IP concealment

BREAK: 2:30 – 3:00

Session 3/A: 3:00 – 3:30

DIB Design Sanity Check Using CircuitSimulation Software Ambika Krishnamoorthy, Swetha Thiagarajan, Intel; Tom

Chambers, Chris Paull, Teradyne

This paper will review a method for using circuit simulation soft-

ware to verify DIB design. The authors were presented with a situ-

ation in which both DC and AC measurements had to be made

on a DUT output. This situation required trade offs in the DIB

design to handle both the current requirements for the DC meas-

urements and the frequency requirements for the AC measure-

ments. To validate their choices, the authors used circuit simula-

tion software to show how the DUT response would be seen at

the tester hardware. In this paper, the authors will review their

creation of the circuit and the results that demonstrated they had

accurately designed the DUT.

Session 3: 3:00 – 5:00DIB Design Verification

Session 3/B: 3:30 – 4:00

Automating Schematic Verification forBetter Efficiency and Better Chancefor First-Pass SuccessDavid Baird, Freescale Semiconductor

Verifying and error checking loadboard schematics can now be

performed in less than one hour. This reduction in time is the

result of a major software tool advancement developed by

Freescale engineers. Designed specifically to check FLEX™ load-

boards and Probe to PIB boards, the new tool automates most of

the schematic verification and helps eliminate errors that are easily

overlooked. It takes in exported net lists and sheet/part parame-

ters and outputs any potential issues and maps from the DUT to

the tester resource for easy verification.

Session 3/C: 4:00 – 4:30

Self-Documenting PIB Diagnostics Chad Bray, Trevor Dixon, Texas Instruments

The manufacturing world is constantly searching for process tools

and techniques to increase productivity. As a result, the time met-

ric for processing has increased from six-minute intervals (1/10

hour) to one-second intervals. This paradigm shift from the stan-

dard Availability metric to an Overall Equipment Utilization metric

has increased the tracking resolution by a factor of 360. Now,

where seconds really do count, subsystems must be developed to

reduce all aspects of test throughput. This paper will describe a

method to reduce troubleshooting downtime through the use of

self-documenting diagnostic datalogs.

Session 3/D: 4:30 – 5:00

A Chip that Avoids Mechanical Relayson a DIBGiuseppe Amelio, Francesco Cantini, Moreno Lupi, Francesco

Picchi, Microtest

In this paper, the authors will describe the chip they developed

that avoids the use of mechanical relays and improves DIB reliabili-

ty dramatically. The chip was designed to perform best on a DIB; it

increases density and decreases the number of utility bits used.

TERADYNE PARTY: 6:00 – 9:00

35

BREAKFAST: 7:00 – 8:00

WELCOME: 8:15 – 8:45

KEYNOTE I: 8:45 – 9:30

KEYNOTE II: 9:30 – 10:15

BREAK: 10:15 – 10:30

Session 1/A: 10:30 – 11:00

Use Scripting to Get the Most Out ofData Analysis Antoine Megens, Salland Engineering

The toolbox of our standard data analysis tool is extensive, but

some problems can only be solved by using the flexibility of a

script. Scripting can be used for rapid prototyping, that is, Does

this solution work? And, this rapid prototyping using script could

eventually evolve into a new standard feature for the tool.

Session 1/B: 11:00 - 11:30

Data Analysis in Real-time ModeMartijn van der Vlag, Salland Engineering

The real-time module offers immediate access to the tester’s data

through TCI daemons. There is no need to wait for the measure-

ment data. In addition, real-time data sets can be exported to file

(STDF, CSV). Real-time data sets do not differ from normal data

sets except they receive data in real-time. Real-time data sets can

be used in SEDana and will update new data automatically. The

real-time module offers direct feedback on production and quality

issues. It can also compare historical with real-time data and do

site-to-site correlation.

Session 1 : 10:30-12:00Data Analysis

PRODUCTION

INTEGRATION

ANDHW/SWINTERFACE

Session 1/C: 11:30 – 12:00

Yield Monitor Tool for IG-XL™ PlatformsJimmy Chan, Yeng Chee Liew, Broadcom; Nagappan

Nachiappan, Jeffrey Tan, Teradyne

This paper will introduce a yield monitor tool for IG-XL-based plat-

forms. Currently, there is no tool integrated with IG-XL to perform

detailed yield and test analyses during run-time. When developed,

this tool will extract yield reports without ending the current test lot

or closing the stdf. The user will be able to monitor the yield results

(Bin, Sort, paretos) and detailed test analyses (Cpk, Cp, Mean, etc.)

for various tests. Thus, when the operator alerts the engineers to a

low yield setup in a production environment, the engineers will be

able to analyze the lot results and narrow the problematic test in an

efficient manner. The user need not touch the setup (loadboard,

tester, handler) until a proper analysis is done. The majority of the

yield monitor tool will be written in the Python® programming lan-

guage. There will be minimal impact on test time as the process

written in Python will run independently of IG-XL.

LUNCH: 12:00 – 1:00

Session 2/A: 1:00 – 1:30

Integrating the FLEX™ Test Systeminto a Well-Established Test Floor Chad Bray, Trevor Dixon, Texas Instruments

To be competitive in the semiconductor industry we must focus

on reducing the time to market for new devices, which includes

installing and validating new tester platforms. Before an installa-

tion, it is imperative to understand the testing environment.

Integrating a test platform into a well-established test floor

requires careful planning, coordination, and communication

among various groups. This paper will describe lessons learned for

release to production, growing pains, equipment correlation

methodology, and how to reduce the number of installation steps.

Session 2/B: 1:30 – 2:00

Planning and Logistics: Converting aComplex SoC Catalyst™ to FLEX™ inAsia without Leaving EuropeJohn Tatchell, CSR; Ian Beck, Teradyne

Converting any test application from one platform to another is

difficult and even more so when the application is a complex RF

SoC. To further complicate the conversion, add a fabless customer.

In this particular case, when a conversion is for a fabless customer,

the development is done in Europe and the production in Asia.

Now link multiple test system acceptances and add a tight dead-

line. High pressure on the development team? Absolutely!

This paper will describe how the authors planned, implement-

ed, monitored, met their goals, and kept costs under control …

and what they learned from the project.

Session 2: 1:00 – 2:30Tester Integration A

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LUNCH: 12:00 – 1:00

Session 6/A: 1:00 – 1:30

Mixed-Signal Simulation for TestProgram DevelopmentPhilippe Raynaud, Mentor Graphics ; Philippe Planelle,

STMicroelectronics

Mentor Graphics and STMicroelectronics are collaborating to

develop the capability to simulate test sequences for Analog and

Mixed-Signal devices and then to transfer the simulation stimuli

and results into IG-XL™ for the Teradyne FLEX™ tester.

During the presentation, the problem statement will be

described and the implemented flow will be reviewed. A more

detailed description of the AMS simulations, the STIL-AMS lan-

guage initiative, as well as the roadmap will be discussed.

Following the presentation, a real-life example will be demon-

strated, including some of the debug steps that were carried out.

Session 6/B: 1:30 – 2:00

Integrating the GSI GroupWaferTrim™ M310 with themicroFLEX™John Grandbois, Analog Devices; Peter Turner, Teradyne

This presentation will summarize the integration of the M310

Active IC Trim System with the microFLEX. To control the laser, a

custom circuit to use tester resources and the SW drivers will be

described. In addition, the authors will present the first application

of this technique on the ADXL330 from Analog Devices.

Session 6: 1:00 – 2:30 Tester Integration B

Session 6/C: 2:00 – 2:30

Enabling Customers to DevelopTailored Instruments for the FLEX™Architecture through OpenFLEX™ Omar Biabani, Lee Holt, Robert Manlick, Teradyne

This paper will inform the audience about various tools and servic-

es that the OpenFLEX team has developed to enable customers to

integrate their customized instruments into FLEX systems rapidly.

The authors will introduce a set of enablers they have used suc-

cessfully in the past and a few that are planned for 2007.

Customers who have the expertise to develop specialized instru-

mentation to test specific devices will be excited about these

enablers. This paper will provide in-depth coverage of the techni-

cal aspects of these enablers, such as the controlling hardware,

software language, and the user model. (Also a poster session)

BREAK: 2:30 – 3:00

Session 7/A: 3:00 – 3:15

Semiconductor Business Meeting

Session 7/B: 3:15 – 4:00

Semiconductor Engineering Update

Session 7/B: 4:00 – 4:45

Semiconductor Open ForumDiscussion

VENDOR FAIR: 4:00 – 7:00

Session 7: 3:00 – 7:00Engineering Update, Round Table/Poster

Sessions & Vendor Fair

37

BREAKFAST: 7:30 – 8:30

Session 4/A: 9:00 – 9:30

PI Version SelectorMike Knapp, Analog Devices; Laurent Bonneval, Teradyne

Managing custom software can become cumbersome, especially

for user interfaces and various drivers which are IG-XL™ depend-

ent. ADI needed a fast way of switching their custom software

from one version to another using different IG-XL versions along

with setting default configurations for production testing. These

issues can be resolved by the PI Version Selector tool, previously

developed for Analog Devices. In this presentation, the authors

will describe the challenges they faced when delivering the tool to

ADI and the solution chosen to manage ADI's custom software.

Session 4/B: 9:30 – 10:00

How to Write and Use Simple DLLs toAccelerate Code ExecutionEmanuele Vazzoler, STMicroelectronics, Alfredo Stabile, Teradyne

This paper will illustrate an easy way to write DLLs using VB or

VC++ and how to call them from IG-XL™. While VB code is inter-

preted, DLLs are compiled which allow code to be executed at a

significant increase in speed. In addition, DLLs are well suited to

execute code when heavy calculations need to be performed

(especially when a DSP is not available, i.e., J750™), or when

dealing with complex string manipulations. A method to register

an ActiveX DLL by a non-administrator user is also described. This

method will be useful in production environments where users

are normally given restricted rights.

BREAK: 10:00 – 10:30

Session 4: 9:00 – 10:00Collaboration

PRODUCTION

INTEGRATION

ANDHW/SWINTERFACE

Session 5/A: 10:30 – 11:00

Test Program Guidelines forCollaborative DevelopmentJeff Cramer, Jonathan Kubala, Tom Vance, Teradyne

This paper will describe the software guidelines and coding strate-

gy used by a multi-member two-continent development team to

implement a package test program on a complex cell phone

power-management device. A description of some of the prob-

lems experienced on previous generations of devices will be

included as well as a description of the efforts to eliminate these

issues for this project. The software guidelines and coding stan-

dards will be presented, including the reasoning for each, and a

final assessment of the strategy's successes and failures. In addi-

tion, an overview of the revision control strategy and the success-

es and failures of the revision control system during program

development will be covered.

Session 5/B: 11:00 – 11:30

Subprogram Modularity: ImprovingTest Program DevelopmentProductivity and ReusabilityKevin Bushe, Teradyne

Subprogram modularity can make development and collaboration

for an IG-XL™ test program easier for today’s System on Chip

(SoC) designs. Using an Add-In built by Applications and

Software engineers at Teradyne, a development team can modu-

larize its IG-XL test program based on individual IP blocks that

make up the larger SoC. Test engineers now can work on a single

IP block of the chip and, once completed, the Add-In can be used

to 'merge' the smaller block into the SoC's master test program.

With this method, test program development time will decrease.

Common or next generation devices that have similar IP blocks

will be able to take the modular IG-XL test and incorporate it into

the new device much more easily, which will maximize test pro-

gram reuse.

Session 5/C: 11:30 – 12:00

Smarter ASCII Export for Dumber CMTools: Using Interpose Functions withASCII_Utils.xla Glenn Carson, Freescale Semiconductor

The ASCII_Utils.xla add-in provides an excellent framework to sup-

port CM activities and modular program development. It provides

an ASCII sheet export function that supports CM for the modular

pieces of an IG-XL™ test program. Unfortunately, many CM tools

use time and date stamps to detect file changes; and the

ASCII_Utils.xla always exports all files, even the files that have not

been modified. This paper will present a solution that uses inter-

pose functions available in ASCII_Utils.xla to export only changed

files into the CM working directory.

Session 5: 10:30 – 12:00Collaboration and Revision Control

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BREAKFAST: 7:30 – 8:30

Session 8/A: 9:00 – 9:30

Calibration of SE-HDACTO Pushes theDC Calibration Unit to its Limits DirkJan Stuij, Salland Engineering

The SE-HDACTO pushes the limits of the DC-calibration unit,

bringing the DC accuracy to the next level for synthesizer/digitizer

instruments on the FLEX™. The DC calibration for the SE-HDAC-

TO must be close to the accuracy of the DC calibration unit of the

FLEX. This presentation will describe the techniques used to cali-

brate both the source and capture channels of the SE-HDACTO

with the DC-calibration unit and will verify that the calibration

meets specifications.

Session 8/B: 9:30 – 10:00

Effective Spot Calibration of the DC30Source and Meter Using PSets Michael Shilhanek, Texas Instruments; Zayd Hammoudeh,

Nathaniel Jansak-Noble, Teradyne

The DC30 is a medium-performance, high-density VI. For some

current generation devices, it is critical to force and measure volt-

ages from a DC30 channel with high precision, pushing the capa-

bilities of the instrument. Therefore, a high-precision spot calibra-

tion (SpotCal) which couples the DC30 with a high-precision meter

such as the Precision Metering Option (PMO) is becoming more

commonplace. Because of the increase in the use of high-end

spot calibration, there is a need for a new SpotCal tool set that

supplies comprehensive tester coverage, ease of use, and a stan-

dard for incorporating these SpotCal techniques into test programs.

This paper will provide a DC30 source and meter SpotCal archi-

tecture for the FLEX™ and microFLEX™ that is fully site-aware and

implemented to reduce run-time overhead. It achieves this reduc-

tion by storing all calibration information in a data structure capa-

ble of low access times, even lower than a standard array.

Moreover, it has been designed using the PSet paradigm, which

allows for reduced setup time when changing an instrument’s

state as well as use in patterns. In addition, the architecture can

detect when an autocalibration has occurred on a specific channel

and recalibrate only that channel, further reducing overhead.

Session 8: 9:00 – 10:00Calibration

BREAK: 10:00 – 10:30

Session 9/A: 10:30 – 11:00

A Useful VBT Programming ToolIntegrated in IG-XL™Hao Chang, Teradyne

Today’s complex DUTs often have complex VBT programs, the pre-

ferred mixed-signal test programming language on the IG-XL

platform. Writing and maintaining these complex programs is

always tedious and difficult. This paper will introduce a tool that

shows the VBT programming structure in Microsoft TreeView. This

tool shows how the nodes correspond to every sub-structure in

the program, such as a function, a “for loop,” and so on. It can

accelerate program development and facilitate program mainte-

nance and be integrated seamlessly into VBA IDE as an add-in

program. The author will also describe how to customize VBA IDE

with add-in.

Session 9/B: 11:00 – 11:30

Buttons to Generate VBTBin Chiu, Teradyne

This paper will provide a fast and friendly GUI to generate VBT.

The GUI is embedded in the right-click menu. Users can select the

relevant GUI and easily modify some parameters. The code will be

generated automatically into the VBT. This tool will make program

development faster and easier to construct. The developer will be

able to click just a couple of buttons to generate VBT code.

Session 9/C: 11:30 – 12:00

Automated Optimization and Cleanupof VBA-based Test ProgramsHubert Schafzahl, Infineon Technologies

During test program development, various elements of the test

program (pattern, instances, VBA code) typically will accumulate

and remain part of the test program even if they are no longer

needed in the final test program.

This paper will demonstrate a method to identify and remove

unused elements of the test program automatically. It will also

show how the method can be used to document test flow, test

pattern, test instances and, most importantly, the code execution

flow. Based on this information, the VBA code can be optimized

for both size and speed, thus reducing complexity and increasing

efficiency.

Session 4: 9:00 – 10:00Collaboration

39

Poster Presentations/Roundtable Sessions: 4:45 – 7:00

Poster 1

VOM (Voice of Mine) — Closing the Loop Swagata Chakrabarti, Peter Chuang, Teradyne

Gathering requirements that define and describe the function for

its software from the user’s point of view is one of Teradyne’s con-

tinuous improvement methods. This helps Teradyne build and

deliver software that meets customers’ needs and expectations

and closes the loop between the users in the field and the

designers in the factory.

In this paper, the basic concept and key elements of the

requirements process and documentation will be introduced. How

to read the requirements document from the user’s point of view

and how to validate and examine the completeness and correct-

ness of the requirements will be explained. In addition, this paper

will describe and show examples of how to create requirements

to facilitate communication with design engineers.

Poster 2

Integration of Full Dynamic Test-CellController with IG-XL™Rob Marcelis, Salland Engineering

The author will demonstrate the capabilities of the Dynamic Test-

cell Controller, including a lot-start event which loads the test pro-

gram on the tester and set-up on the prober automatically.

During production run, real-time parametric data are received and

being used to monitor the CPk and parametric trends for some

selected tests. Actions will be taken dynamically. At the end of the

run a PAT algorithm is executed in combination with “cluster-

detection.” STDF is generated automatically. Equipment status

and results are automatically transferred to the appropriate

locations. This demonstration will show the “ultimate test-cell”

automation.

PRODUCTION

INTEGRATION

ANDHW/SWINTERFACE

Poster 3

Securing Test Systems in theProduction EnvironmentBob Mastrogiacomo, Jaci Wilson, Teradyne

During the past 15 years, PCs have become a common household

item. While many still do not own PCs, many more not only own

but think they know how to manage and customize the settings

for their local machines. This sense of mastery can lead to and

causes many PCs to become infected with viruses, Trojans, and

malicious software. An infected PC may result in slower perform-

ance and/or the loss of important data. While Teradyne recom-

mends the use of an anti-virus software, it cannot control the

security of your test system. Security needs to be addressed by the

owner and System Manager for each device. This paper will

review several methods to limit access for the user/operator of a

test system, such as disabling web surfing, downloading pro-

grams, and changing backgrounds.

Poster 4

Enabling Customers to DevelopTailored Instruments for the FLEX™ Architecture throughOpenFLEX™ (Also a paper- Session 6/C)

Omar Biabani, Lee Holt, Robert Manlick, Teradyne

This paper will inform the audience about various tools and servic-

es that the OpenFLEX team has developed to enable customers to

integrate their customized instruments into FLEX systems rapidly.

The authors will introduce a set of enablers they have used

successfully in the past and a few that are planned for 2007.

Customers who have the expertise to develop specialized instru-

mentation to test specific devices will be excited about these

enablers. This paper will provide in-depth coverage of the techni-

cal aspects of these enablers, such as the controlling hardware,

software language, and the user model.

Round Table 1

Update on IG-XL™ HelpJohn Buckley, Mike Gill, Teradyne

Round Table 2

DTV/HDTV Testing on the UltraFLEX™ — Q&AFang Xu, Teradyne

Q&A for Session 6/A

Round Table 3

OpenFLEX

Round Table 4

TAG Table

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Session 11/B: 3:30 – 4:00

Using 32x Parallel Test with ViProbe for Test Time and Test Cost Reduction on Low Cost DevicesAndreas Berdzentis, Texas Instruments; Andre Vogel, Teradyne

To improve test time and the cost of test, a simple switch was

converted from a legacy single site tester to 32x FLEX™ using

ViProbe from Feinmetall. With the implementation of this test,

the authors realized two major advantages, i.e., calibration units

on the FLEX are not needed and the production process is more

robust when cantilever probe cards are replaced. The first pro-

gram was released to production and is running well. The original

FLEX program was modified to test three similar devices. All four

test programs are now running in high volume.

Session 11/C: 4:00 – 4:30

Practical Hardware and SoftwareConsiderations for High-ParallelMixed-Signal Testing with the J750™Michael Jonas, Texas Instruments

With the increase in the importance for reducing test cost, more

simultaneous DUT testing is required. Mixed-signal testing, in

particular, requires different hardware resources such as digital

channels, CTO, MTO, and MSO. Depending on the tester config-

uration and the device specific function, one or more instrument

resources may not be sufficient.

To parallel test 16- to 32-sites, there are several constraints to

consider. On the hardware side, one solution is to share tester

resources like digital channels, utility bits, or MSO resources.

Another approach is to reduce resources applied to the DUT to

the absolute minimum to execute the test. Combining these two

methods allows going beyond the typical parallel site count in

mixed-signal testing.

Sharing resources also creates more effort on the software

side, e.g., measurements must be taken for each site individually

by using site loops and data arrays.

The paper will describe the challenge to reduce test cost by

increasing parallel testing up to 32-sites, and will give examples

and solutions to deal with limited tester resources like high-volt-

age channels, utility bits, CTO, MTO, and MSO. In addition, some

software examples will be presented.

Session 11/D: 4:30 – 5:00

Simultaneous Device Testing atMultiple Handlers with Single FLEX™and Cable DockingArmin Winkler, Infineon Technologies; Ramanamurthy Pakki,

Teradyne

The intricacies involved in testing multiple handlers with different

ambient settings simultaneously using one test program and one

tester are discussed in this paper. The signals from the DIB are

brought to the handlers by Cable Docking. A lead frame transfers

the devices through three handlers with different ambient condi-

tions. The devices are tested and the data collected at each han-

dler for its specific condition. When finished, the data are

processed accordingly. The bin, data, site, fail and alarm handling

are meticulously managed in the test program.

SURVIVOR PARTY: 5:30 – 7:00

41

LUNCH: 12:00 – 1:00

Session 10/A: 1:00 – 1:30

Automated Voltage and Temperature Characterization Utility for IG-XL™Tarang Dadia, Qualcomm; Daniel Buker, Teradyne

This paper will describe a method to run an entire IG-XL test pro-

gram over multiple voltage and temperature combinations auto-

matically. When this method is used, instead of changing jobs or

modifying a Spec sheet, which requires revalidation, the tempera-

ture and voltage conditions are defined with a text file or lines in

the Flow sheet. The voltage/temperature characterization

sequence is started either from the toolbar or from an ALT+ key

combination. In addition, VBT programming examples will be

presented.

Session 10/B: 1:30 – 2:00

Introducing Power Supply StatusVariables – A Simple and EfficientWay to Organize and Document Test Functions Yaw-Hua Hong, Weishu Wu, Texas Instruments

Proper organization and documentation of test programs are

especially important when used globally by various groups. It is

often desired to have modular test functions which allow an

engineer to insert a new test function or disable an existing one

without affecting other functions. Modular test functions can be

achieved by restoring the test program to a default state after

each test, e.g., power-down state. Because modern IC chips

offer more features and multiple resources are often used for

power pins, modular test functions come at the expense of

longer test times. Power supply status variables will provide a

simple yet efficient way to organize test functions without sacri-

ficing test time.

Session 10: 1:00 – 2:30General Programming

PRODUCTION

INTEGRATION

ANDHW/SWINTERFACE

Session 10/C: 2:00 – 2:30

A Software Technique for CheckingData Integrity in FusesSteve Sheck, Freescale Semiconductor

Programmable fuses play a critical role in the operation of many

of today’s semiconductor devices. Their primary use is in the

implementation of redundancy for bulk memory, caches, and

embedded memory. In addition, circuit tuning and the storing of

parametric data, chip identification, and encryption keys are other

common uses. Regardless of end use, it is critical that the data

stored in fuses remains constant throughout the life of the device.

This paper will present a technique for authenticating the data

stored in fuses, and will discuss methods of analysis when stored

data fails to authenticate.

BREAK: 2:30 – 3:00

Session 11/A: 3:00 – 3:30

Reduce, Reuse, and Recycle: On-the-Fly DC Measurements Without a New Instrument Jim Crafts, Amit Shah, IBM

The objective of the authors was to perform a DC measurement

concurrent with a pattern burst. Previously, the DC measurement

was taken before and after a pattern burst with the Per-Pin-

Parametric-Unit (PPMU). A spare HexVS instrument on the existing

tool configuration was leveraged to perform the measurement. To

increase accuracy of voltage measurements, external circuitry was

used to amplify the voltage readings by the HexVS. This paper will

describe the methods and results.

Session 11: 3:00 – 5:00Handler n'All

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Session 2/B: 1:30 – 2:00

On-the-Fly Statistics with IG-XL™Jos Driessen, NXP Semiconductors

SiPs (multiple dies and SMDs) show a relatively high biasing for

test parameter distributions from lot to lot. To improve test cover-

age (outlier screening) and yield when testing a batch, dynamic

(control) limits are very helpful. With IG-XL/VBA, it is possible to

create a generic approach to track the statistics per test parame-

ter (standard-deviation, mean, median) and, therefore, control-

limits. In addition, when carrying out iterative settings, the ‘mean’

can be used as a starting point which improves test time. This

paper will describe the IG-XL template used in this approach.

BREAK: 2:30 – 3:00

Session 3/A: 3:00 – 3:30

Defining Inductance in ContactorsRyan Satrom, Everett Charles Technologies

Inductance is a critical parameter in determining the electrical per-

formance of a contactor. Unfortunately, this value is rarely inter-

preted properly. Inductance specifications are typically determined

in a Ground-Signal-Ground configuration. This value is beneficial

as a relative comparison between contactor technologies, but can

be very misleading when trying to model the inductance through

a contactor.

This presentation will give a basic overview of inductance and

a description of the relationship between inductance and electro-

magnetic wave theory. This theory states that the inductance

through a contactor is not defined by a single probe but, rather, is

determined by the configuration of each individual signal/power-

to-ground loop. Without this background, it is extremely difficult

to model the inductance through a contactor accurately.

A common method to represent the inductance through a

contactor which models each probe as an inductor will be

explored. By understanding electromagnetic wave theory, this

method will be shown to provide inaccurate results. A more accu-

rate technique will be presented. Inductance is directly related to

the number of magnetic field lines surrounding a conductor. Only

through the use of 3D electromagnetic simulation can this value

be captured accurately.

Session 3: 3:00 – 5:00Board/Material Considerations

By understanding the basics of inductance and using 3D elec-

tromagnetic simulation, engineers are able to characterize the

inductance through a given contactor more accurately. As the

challenge to meet the electrical requirements continues to

increase, understanding the concepts described in this presenta-

tion will allow for continued improvement in contactor design.

Session 3/B: 3:30 – 4:00

RF Connectors and Material: APerformance Comparison Martin Dresler, Wolfgang Steger, Teradyne

With the increasing speed of digital and RF devices it is important

to understand the influence of different DIB materials and RF con-

nectors. Poor signal performance can make a high-speed DIB use-

less. This paper will provide theoretical and practical insights for

the critical performance parameters and how they can be estimat-

ed. Finally, the performance of different types of DIB materials and

RF connectors will be compared and recommendations for RF DIB

design will be included.

Session 3/C: 4:00 – 4:30

Design Example for a Generic RF DIBand Custom Daughter BoardKN Chui, Corad Technology; Charles Kao, Teradyne

This paper will describe a generic RF DIB example with microwave

Gen4 for the FLEX™ which will speed up the performance verifi-

cation and test program development for modern RF SoC trans-

ceivers. Topics covered in the presentation include flexible tester

configuration, low PN clocks, and programmable dampers. In

addition, samples of daughter board custom features for produc-

tion release will be demonstrated.

Session 3/D: 4:30 – 5:00

RF Debugging Techniques for VolumeProduction Peter Higgins, Teradyne

The transition from semiconductor RF test development for sam-

ple quantities on one tester to high-yield volume production on

many testers is major. This paper will describe some techniques for

successful volume production and some hints for debugging stan-

dard RF tests. The methods are generic; they can apply to many

RF devices and testers. The reasons for repeated RF calibrations,

techniques, and test floor conditions will be explained, together

with the reasons why RF is “special” and why RF volume produc-

tion ramp is not to be taken lightly.

TERADYNE PARTY: 6:00 – 9:00

43

BREAKFAST: 7:00 – 8:00

WELCOME: 8:15 – 8:45

KEYNOTE I: 8:45 – 9:30

KEYNOTE II: 9:30 – 10:15

BREAK: 10:15 – 10:30

Session 1/A: 10:30 – 11:00

Introducing the Port ExpanderInstrumentGlenn Burnham, Teradyne

RF switches are often added to DIBs to increase RF port count

beyond the eleven available with Gen4. Splitters are also used to

provide simultaneous signals to multiple sites, especially receivers

which can be tested in parallel. Unfortunately, splitters and

switches add complexity, cost, and additional risk to a DIB in pro-

duction. Since Gen4 calibration does not include these compo-

nents, the burden is on the test engineer to characterize the DIB

to adjust Gen4 accordingly. Splitters have the additional problem

of allowing a grossly failing site to affect the results of other sites.

The port expander was designed to allow users to remove

most, if not all, switches and splitters from DIBs. Additionally, an

integrated Rhode & Swartz power sensor is used to execute a

run-time focused calibration of all signal paths. These calibration

factors can be easily retrieved and applied to Gen4 for source and

receive. A single port expander essentially expands three Gen4

ports to twelve bi-directional Port Expander ports.

This paper will present the Port Expander instrument with

block diagrams and example Visual Basic language that is com-

pletely integrated into IG-XL™. Some example devices will be

used to show interconnection from Gen4 through the port

expander to the DUT.

Session 1 : 10:30-12:00Instrumentation

RFWIRELESS

Session 1/B: 11:00 - 11:30

Improving the Level Accuracy of Gen4MW Hardware David DiBona, Teradyne

Hardware, Software and Applications engineering are participat-

ing in a joint development project to make significant improve-

ments in the source and receive level accuracy of the Gen4 MW

hardware. When a frequency and power-specific calibration table

in a job is followed by the Gen4-focused calibration program, an

improvement in level accuracy is achieved. The focused calibration

program is run from a newly developed option within the

Maintenance User Interface software. In this paper, the author will

describe how this improvement is achieved.

Session 1/C: 11:30 – 12:00

The Implementation of GSM/EDGESource and Receive Library in IG-XL™Ronald Burke, Helen Chen, Peter Chen, Greg Dionne, Shu Xia,

Zhe (Sophie) Xu, Teradyne

GSM/EDGE signals are defined in 3GPP specs which are normally

generated and analyzed by bench instruments. ATE vendors corre-

late the results and move them to production. The GSM/EDGE

Source and Receive Library enables users to generate GSM/EDGE

source segments and test Error Vector Magnitude (EVM) and

Output RF Spectrum (ORFS) in IG-XL easily and quickly. The corre-

lation between the bench instrument and FLEX™ GSM

Modulation Library Rev.1 functions is good and stable. In Rev.2,

the Graphic User Interface for the source side and GSM Phase

Error test will be added to make it more user friendly and useful.

In addition, BER test for different channel types and how to use

different channel decoder mode and puncture mode and so on

will be described.

LUNCH: 12:00 – 1:00

Session 2/A: 1:00 – 1:30

Migrating a Final Test RF SoC fromSingle-Site Catalyst to Quad-Site FLEX™Kim Gundersen, AMI Semiconductor

A summary of strengths and challenges encountered in develop-

ing an RF SoC final test program on a single-site Catalyst, then

later for a quad-site FLEX, is presented. Topics include test pro-

gram, RF source and measurement accuracy, DIB hardware, test

time, and correlation comparisons. The intended audience

includes those interested in mixed-signal and RF SoC Catalyst to

FLEX test program conversion.

Session 2: 1:00 – 2:30Code Examples

42

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RFWIRELESS

LUNCH: 12:00 – 1:00

Session 6/A: 1:00 – 2:30

Tutorial — DTV/HDTV Testing onUltraFLEX™Fang Xu, Teradyne

After a brief introduction of standards worldwide, this tutorial will

describe various DTV/HDTV signal modulation schemes such as

VSB8 and OFDM, followed by an introduction of DTV/HDTV relat-

ed signals and a block diagram of a typical DTV System-on-Chip

as well as its test list. Some DTV specific functions and their test

requirements are analyzed in detail. These functions include con-

verters, PLL, and HDMI as well as related instruments on the

UltraFLEX platform and their application. Performance for

DTV/HDTV test will also be demonstrated. In addition, a typical

tester configuration on the UltraFLEX will be covered. This tutorial

was first presented in Asia to more than 150 customers.

Session 6: 1:00 – 2:30 Tutorial

45

BREAKFAST: 7:30 – 8:30

Session 4/A: 9:00 – 9:30

Characterization/HVM ComprehensiveTest Solution for 10G/3G TransceiverUtilizing the Teradyne Tiger Platformand SDM 10G ModuleFayez Sedarous, Intel

This paper explores the implementation of Intel’s latest HVM fully

comprehensive test solution to test Optical Devices (10 Ethernet,

10G Fiber Channel and Sonnet OC-192) utilizing the Teradyne

Tiger Tester Platform. It deals with the pros and cons and many of

the lessons, experiences, and knowledge acquired when dealing

with high-speed mixed-signal testing. It explores the test develop-

ment codes and hardware implementation techniques using the

Seahorse2, a 10G transceiver, as a test case example. The

Seahorse2 test program is fully implemented and the device has

been released to production.

Session 4/B: 9:30 – 10:00

Interpolation Cookbook: Algorithms,Performance, and GuidelinesAimen Oueslati, NXP Semiconductors; Martin Dresler, Teradyne

Interpolation algorithms can play an important role for a wide

range of ATE test challenges to reduce test time or to improve

measurement resolution. These challenges include mixed-signal

applications with filter characterization, RF with 1dB compression

point measurement, and digital with edge search. Mathematical

theory provides many different algorithms, such as compensation

analysis and polynomial or spline interpolation, which makes it

difficult for test engineers to select the one most appropriate. This

paper will describe the most common algorithms in terms of

functionality, accuracy, and calculation time. The authors will

share the code used for the algorithms and will compare the

results of a 3dB point filter characterization.

Session 4: 9:00 – 10:00Miscellaneous

RFWIRELESS

BREAK: 10:00 – 10:30

Session 5/A: 10:30 – 11:30

Tutorial — Forward Error Correction in Wireless Communication StandardsSteven Fields, Teradyne

This paper will describe Forward Error Correction (FEC) and how it

is used to recover dropouts/burst errors. The general concept and

a high-level description of need for FEC will be discussed.

Following this overview, the author will focus on the convolutional

encoder/puncturing on the source side physical layer and the

Viterbi decoder on the receive side of the physical layer and how

these play an important role in FEC.

Session 5/B: 11:30 – 12:00

Tutorial — GSM/EDGE EVM TestChing-Chia Tien, Teradyne

Unlike WLAN in which constellations are fixed at ideal IQ frame,

GSM/EDGE's constellation can become corrupted. The inter-sym-

bol interference cannot be recovered easily because a 90kHz win-

dow raised cosine filter is used in EVM test where the pass band is

well below the 200kHz channel bandwidth. A reference frame

will be generated for comparing the actual data points for EVM

calculation. This reference frame is data dependent and should be

generated for each unique baseband data stream.

Session 5: 10:30 – 12:00Tutorials

44

BREAK: 2:30 – 3:00

Session 7/A: 3:00 – 3:15

Semiconductor Business Meeting

Session 7/B: 3:15 – 4:00

Semiconductor Engineering Update

Session 7/B: 4:00 – 4:45

Semiconductor Open ForumDiscussion

VENDOR FAIR: 4:00 – 7:00

Poster Presentations/Roundtable Sessions: 4:45 – 7:00

Round Table 1

Update on IG-XL™ HelpJohn Buckley, Mike Gill, Teradyne

Round Table 2

DTV/HDTV Testing on the UltraFLEX™ — Q&AFang Xu, Teradyne

Q&A for Session 6/A

Round Table 3

OpenFLEX

Round Table 4

TAG Table

Session 7: 3:00 – 7:00Engineering Update, Round Table/Poster

Sessions & Vendor Fair

Page 25: TUG '07

RFWIRELESS

LUNCH: 12:00 – 1:00

Session 10/A: 1:00 – 1:30

Developing the Spectrum Mask /Adjacent Channel Power Test on the FLEXHongBin Tong, NXP Semiconductors; Ching-Chia Tien, Teradyne

The spectrum of an RF transmitter must not exceed its allocated

bandwidth. Otherwise, the power spill over could corrupt the

neighboring channels. The tradeoff between the test time and

the measurement accuracy of the following three algorithms will

be discussed.

1. Multiple captures using Gen IV RF instrument

2. One capture for symmetrical side bands and two for asymmetrical side bands

3. Two captures using an external mixer

Session 10/B: 1:30 – 2:00

Accurate GSM Phase Error and EVM Measurements on the FLEX™Helen Chen, Greg Dionne, Shu Xia, Zhe (Sophie) Xu, Teradyne

Phase error and Error Vector Magnitude (EVM) tests are common-

ly used to provide a figure-of-merit for the overall modulation

accuracy of the Global System for Mobile Communications (GSM)

systems. There is a trend for accurate, fast, yet easy to implement

GSM modulation accuracy measurements in final production test

on ATE platforms. This paper will describe some key techniques

used inside the library that facilitate accurate and easy-to-use test-

ing on the FLEX. Test programs using these techniques show

good correlation with bench equipment when testing a real GSM

transceiver device.

Session 10: 1:00 – 2:30Test Techniques

Session 10/C: 2:00 – 2:30

RF Modulation/Demodulation forDummiesM.Ramasamy, Gopalakrishnan Srinivasan, Teradyne/HCL

Technologies

For the beginner, any bookish material written so far on these two

topics has always been a nightmare to grasp and retain. This tuto-

rial may help to alleviate the problems of an RF novice. The vari-

ous types of analog and digital modulation and an overview of

constellation diagrams will be presented. In addition, the authors

will describe how to make modulation measurements using

the tester.

BREAK: 2:30 – 3:00

SURVIVOR PARTY: 5:30 – 7:00

47

BREAKFAST: 7:30 – 8:30

Session 8/A: 9:00 – 9:30

Test Time: A License for an RF TestEngineer!Philippe Soleil, NXP Semiconductors

My name is Philippe, Philippe SOLEIL. My mission: Kill the test

time!

This paper will describe a test strategy defined on an RF trans-

ceiver that, when followed, will drastically reduce test time and

meet the profitability target. Different ways to improve test time

will be presented such as a new test method (Xo steps), group of

measurements, multi-tone, tips and tricks for IG-XL™ and

FLEX™, correlation and redundancy between tested parameters,

and System test versus Parametric Test. This paper will provide a

complete package for the future test engineer to obtain his

license to test.

Session 8/B: 9:30 – 10:00

Test Time Reduction and Strategy on a Multi—Chip DeviceMike Bellanger, Salvatore Cutrupia, NXP Semiconductors

In this paper, the authors will describe a fully-integrated solution

for the wireless market. The solution is composed of two different

dies in the same package. They are: 1) an analog and RF unit

(RFAPU) integrating a power amplifier able to deliver 27dBm, a

DECT transceiver and an analog process unit (two codec, ADC,

one hands free and one a power management unit); and 2) a

baseband processor (DPU) based on ARM9 technology. The

FLEX™ platform was chosen for the solution because of its RF,

analog, and digital capability. This presentation will focus on the

RFAPU die. It will describe the test strategy, DFT integrated to

make some blocks testable, and tips and tricks to reduce

test time.

Session 8: 9:00 – 10:00Test Time Reduction

RFWIRELESS

BREAK: 10:00 – 10:30

Session 9/A: 10:30 – 11:00

Generating ASK Modulation Signalsfor Contactless Chip Card Controllerson the J750™Hubert Schafzahl, Johannes Schorrer, Infineon Technologies

Historically, the contactless functionality of chip card controllers

was tested by applying ASK modulated signals with varying mod-

ulation depths. In general, these signals were generated by exter-

nal circuitry controlled by the tester. This paper will describe a

method that does not require additional external elements; the

modulation signal will be generated by the tester. The signal is

achieved with special test pattern and timing sets, and by control-

ling pin levels dynamically according to modulation depth. When

this new method is applied, overall test cost can be significantly

reduced with equal or increased test quality.

Session 9/B: 11:00 – 11:30

Low-cost Alternate EVM Test forWireless Transmitter SystemsPhilippe Brousse, NXP Semiconductors

The EVM is a fundamental parameter used in EDGE and WCDMA

to characterize modulation accuracy under real-life conditions. The

next generation RF transmitters require EVM test for each band

and each mode. However, due to the complexity of this measure-

ment, the test times for EVM are very long. This paper will present

a study to calculate the EVM TX with major contributors like

Phase noise, LO rejection, Image rejection, and some other tricks

for the real measurements.

Session 9/C: 11:30 – 12:00

RF Test Code Templates forWCDMA+GSM Transceiver on Generic RF DIBAlbert Jen, Charles Kao, Luis Tang, Teradyne

In this paper, the authors will describe a set of IG-XL™ test code

templates developed with WCDMA+GSM. These templates are

based on a generic RF DIB developed for Teradyne FLEX™ RF

testers. The generic RF contains three types of code (basic,

advanced, and utility) to reduce RF test program development

time and effort. The authors will show how these templates will

shorten the engineering time to production on the Evaluation

Board (EVB) and how the EVB can be a production board

for customers.

Session 9: 10:30 – 12:00Test Techniques

46

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MIL/AERO

LUNCH: 12:00 – 1:00

Session 2/A: 1:00 – 2:30

Hands-On Programming in C#Workshop

BREAK: 2:30 – 3:00

Session 3/A: 3:00 – 5:00

Hands-On Programming the Bi4-Series WorkshopThe Bi4-Series Workshop will demonstrate how to write a simple

program that uses the Bi4-Series instrument to communicate with

a UUT using the RS-232 bus protocol. Attendees will get a chance

to write code and run that code on a Bi4-Series instrument to

control an array of LEDs.

TERADYNE PARTY: 6:00 – 9:00

Session 3: 3:00 – 5:00Bi-Series

Session 2: 1:00 – 2:30Programming in C #

49

BREAKFAST: 7:00 – 8:00

WELCOME: 8:15 – 8:45

KEYNOTE I: 8:45 – 9:30

KEYNOTE II: 9:30 – 10:15

BREAK: 10:15 – 10:30

Session 1/A: 10:30 – 11:00

Using Interchangeable VirtualInstrument (IVI) to Increase TestDevelopment Efficiency Sameer Bivalkar, Teradyne

A consortium of leaders in the ATE industry is developing an IVI

standard. The goal is to develop a standard to write SW drivers

that can be hardware independent. The tests are written using IVI

Class Drivers which enable calls to be routed to the correctly con-

figured hardware. The IVI Class Driver also provides a simulation

option which completely frees the test developer from any hard-

ware dependencies while developing test program sets.

This paper will describe how IVI was used to reduce test devel-

opment time significantly for Ai-760™, the new analog test

instrument being developed by Teradyne.

The paper will cover the following topics:

1. Introduction to IVI

2. Software requirements and system setup for IVI

3. Overview of the Ai-760

4. Writing tests using other IVI Compliant instruments

5. Debug test cases using simulation & 3rd party hardware

6. Running tests on the Ai-760

7. Impact on overall test schedule

8. Conclusions

Teradyne has been able to leverage the IVI technology to reduce

'Time to Market' significantly for the new analog test instrument.

Session 1 : 10:30-12:00Test Development

MIL/AERO

Session 1/B: 11:00 - 11:30

Cost Benefit Analysis for Using ATLASJim Danscuk, U.S. Air Force

What is the cost-benefit of using legacy ATLAS code versus devel-

oping new C-code to re-host Test Program Sets from the USAF

IATE tester to the ADTS tester?

The Oklahoma City Air Logistics Center at Tinker Air Force

Base in Oklahoma is part of a multi-organizational team working

to re-host the intermediate level test software for B1-B LRU elec-

tronics. The target tester is the Advanced Digital Test Station™

(ADTS), developed by Teradyne from the Spectrum™-series tester.

Since the old test programs were written in ATLAS, ATLAS 89

was chosen as the test program development language. This

approach was taken to capitalize on previous ATLAS development

work and, we hoped, minimize the effort. However, since the

inception of the re-host project, the ATLAS language has intro-

duced problems and limitations that have actually slowed down

the development process.

C programming language is commonly used to develop instru-

ment and device drivers. C is a powerful, high-level language that

is widely available and accepted in the industry. When the ATLAS

language does not provide the capability to interface with test

instruments, sub-programs called Non-ATLAS Modules (NAMs) are

written in C to accomplish the same task.

This research paper will examine the cost-benefit of using lega-

cy ATLAS to re-host existing test programs versus developing new

programs using only C. The time to convert legacy ATLAS to

ATLAS 89 will be compared to development time for workaround

C modules (NAMs) or complete test programs using C language

exclusively Examples of Non-ATLAS Module development will be

cited. Unique situations will be identified with issues that would

lend themselves better to one language. Finally, a description of

the advantages and disadvantages, lessons learned in several

cases, along with the potential solution will be presented.

Session 1/C: 11:30 – 12:00

Programmable Test Boards forAssembly TPS Troubleshooting Luis Villalta, Teradyne

Programmable development kit boards provide a troubleshooting

sandbox for TPS developers and integration testers. When used,

these boards reduce the risk of system and prototype UUT dam-

age during TPS development. This approach allows for TPS devel-

opment and UUT hardware emulation away from a tester. This

paper will present two examples of how a development kit board

can be used to troubleshoot TPS development. One example will

use a Teradyne digital instrument (Di) to test a device controlled by

a USB interface, and one will use a Teradyne analog instrument

(Ai710) to test the electromechanical interlocks in a system.

48

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MIL/AERO

BREAK: 2:30 – 3:00

Session 7/A: 3:00 – 4:00

Engineering Update

Roundtable Sessions: 4:00 – 7:00

Roundtable 1

Bi-Series

Roundtable 2

Di-Series

Roundtable 3

iStudio

Roundtable 4

Spectrum

Roundtable 5

Ai-Series

Session 7: 3:00 – 7:00Engineering Update, Round Table/Poster

Sessions & Vendor Fair

51

BREAKFAST: 7:30 – 8:30

Session 4/A: 9:00 – 10:00

Hands-On Programming the Di-Seriesusing iStudio WorkshopThe Di-Series workshop will include hands on instruction on the

user of iStudio to develop and debug a Di-Series-based digital

test. Attendees will use iStudio on development stations to create

tests and run those tests on a Di-Series digital test instrument.

BREAK: 10:00 – 10:30

Session 5/A: 10:30 – 11:30

iStudio/Di-Series Workshop (contin-ued)

Session 5/B: 11:30 – 12:00

Replacing M9-Series Digital TestInstruments (M9-Series DTI) with Di-Series Digital Test Instruments (Di-Series DTI)Lloyd Frick, Teradyne

This paper will discuss several aspects of the process to replace

M9-Series with Di-Series digital test instruments using the M9-

Series interface of the Di-Series driver. Topics include a review of

some important differences between the M9-Series DTI and Di-

Series DTI architecture, how the M9-Series Interface is controlled,

and several debugging techniques.

LUNCH: 12:00 – 1:00

Session 5: 10:30 – 12:00iStudio/Di-Series

Session 4: 9:00 – 10:00iStudio/Di-Series

MIL/AERO

Session 6/A: 1:00 – 1:30

Applications for Ai- and Bi-SeriesInstruments in Legacy™ TesterReplacement Richard Lawrence, Gary Bryant, NAVAIR

Aging weapons platforms are faced with increasing complexity in

system diagnoses. Diagnostic techniques for system maintenance

progress throughout the lifecycle of the weapons platform in an

effort to keep pace with system requirements. The progression for

these diagnostic techniques tends to follow a path set by the sys-

tem’s original designers. As capabilities for generic instrumenta-

tion increase, new paths are created for system maintenance that

were not originally envisioned during the original system design. A

study of tools currently used in the maintenance of control sys-

tems on VSTOL aircraft reveals possible applications for generic

instrumentation.

Session 6/B: 1:30 – 2:00

TBA

Session 6/C: 2:00 – 2:30

A Reconfigurable, Extendable L200Auto-Converter Yonet Eracar, Teradyne

As part of the RTCASS program, The Boeing Company and U.S.

Navy re-hosted a large number of L200 TPSs from CASS to

RTCASS. Teradyne’s TPS Converter Studio was used to convert

these tests. As part of this effort, an L200 Auto-Converter was

developed as an add-on for TPS Converter Studio to automate

many of the common steps and custom configurations for each

conversion. The L200 Auto-Converter interacts behind the scenes

with TPS Converter Studio through the Teradyne Test Studio API

to complete the conversion with minimal user interaction.

However, many of the configuration data and custom conversion

steps were hard-coded in the L200 Auto-Converter. To reuse the

L200 Auto-Converter for another legacy re-hosting program, pro-

grammatic changes and a re-build of the converter would be

required.

This paper will describe the steps taken to extend the capabili-

ties of this custom tool to work with all the legacy re-hosting pro-

grams, and not only for RTCASS. Additional topics will include

the new features added to the L200 Auto-Converter for easy

reconfiguration and the new .NET interface that supports the

addition of custom conversion steps by a user.

Session 6: 1:00 – 2:30 Instrument Replacement

50

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