True Assembly Language True Assembly Language

Part IPart I

The Assembly ProcessThe Assembly Process

The process of translating a MAL code (an The process of translating a MAL code (an assembly language program) into machine assembly language program) into machine code (a sequence of bits) is called assembly.code (a sequence of bits) is called assembly.

The program that performs the translation is The program that performs the translation is called an assembler.called an assembler.

The translation from assembly language to The translation from assembly language to machine code is mechanical, repetitive, and machine code is mechanical, repetitive, and tedious. Small errors can have disastrous tedious. Small errors can have disastrous results and therefore this job is better left to results and therefore this job is better left to computers. computers.

Sometimes, a set of instructions are Sometimes, a set of instructions are repeated several times within a code. It is repeated several times within a code. It is best to give a name to this repetitive best to give a name to this repetitive code sequence. A code sequence. A macro macro defines a defines a sequence of instructions by associating sequence of instructions by associating to it a keyword.to it a keyword.

AA preprocessor preprocessor can then be used to can then be used to expand a macro into a series of expand a macro into a series of instructions it represents.instructions it represents.

Many MAL instructions are identical to Many MAL instructions are identical to TAL. The first step in assembling a MAL TAL. The first step in assembling a MAL program is to translate the code into TAL.program is to translate the code into TAL.

TAL - True Assembly LanguageTAL - True Assembly LanguageMAL is not directly translatable into MAL is not directly translatable into machine code because of several machine code because of several abstractions in the language. abstractions in the language.

The TAL instruction set, however, The TAL instruction set, however, defines the MIPS RISC architecture.defines the MIPS RISC architecture.

TAL arithmetic and logical instructions TAL arithmetic and logical instructions generally require three-operand generally require three-operand specifications but MAL permits two- or specifications but MAL permits two- or three-operand specifications.three-operand specifications.

Arithmetic and Logical Arithmetic and Logical InstructionsInstructions

TAL has both register and immediate TAL has both register and immediate addressing modes, although not all have addressing modes, although not all have immediate modes, e.g., there is no immediate modes, e.g., there is no immediate immediate subsub instruction because it can be instruction because it can be done by done by addadd

addiaddi R Rtt,R,Rss,I R,I Rtt [R [Rss]+([I]+([I1515]]1616||I||I15..015..0))

addiu Raddiu Rtt,R,Rss,I R,I Rtt [R [Rss]+([I]+([I1515]]1616||I||I15..015..0))

andi Randi Rtt,R,Rss,I ,I R Rtt 0 01616||([R||([Rss]]15..0 15..0 AND AND II15..015..0))

lui Rlui Rtt,I R,I Rtt I I15..015..0||0||01616

The MAL The MAL movemove instruction instruction

move Rmove Rtt, R, Rss

is equivalent to the TAL instructionis equivalent to the TAL instruction

add Radd Rtt,$0,R,$0,Rss

Each of the MAL shift instructions exists in two Each of the MAL shift instructions exists in two forms in TALforms in TAL

sll Rsll Rdestdest,R,Rsrc1src1,Src2,Src2

sllv Rsllv Rdestdest,R,Rscr1scr1,R,Rscr2scr2

The first shift instruction is the same as MAL; the The first shift instruction is the same as MAL; the second one specifies a register from which the second one specifies a register from which the amount of shifts is obtained from. The suffix amount of shifts is obtained from. The suffix vv indicate that the amount of shift is variable.indicate that the amount of shift is variable.

Multiplication in TALMultiplication in TALMIPS RISC architecture contains two special MIPS RISC architecture contains two special registers, registers, HIHI and and LOLO, that are used to hold , that are used to hold 64-bit results.64-bit results.

mult Rmult Rss,R,Rtt

takes the contents of takes the contents of RRss and and RRtt as multiplicands as multiplicands

and places the least 32-bit result into and places the least 32-bit result into LOLO and and the other 32-bit result into the other 32-bit result into HIHI..

mul $8,$9,$10 mult $9,$10mflo $8

MAL TAL

HI must be checked for overflowmove from LO

Division in TALDivision in TALThe TAL The TAL divdiv instruction computes both the instruction computes both the integer quotient and remainder, leaving the integer quotient and remainder, leaving the quotient in quotient in LOLO and the remainder in and the remainder in HIHI..

rem $8,$9,$10 div $9,$10mfhi $8

MAL TAL

div $8,$9,$10 div $9,$10mflo $8

Unsigned arithmeticUnsigned arithmetic

The MIPS RISC architecture provides a set of The MIPS RISC architecture provides a set of instructions that perform unsigned arithmetic instructions that perform unsigned arithmetic via instructions that are suffixed via instructions that are suffixed uu..

These instructions These instructions nevernever cause exceptions cause exceptions (error condition) even if overflow occurs. The (error condition) even if overflow occurs. The responsibility is left to the programmer or responsibility is left to the programmer or compiler to assure that overflow never occurs compiler to assure that overflow never occurs when these instructions are used.when these instructions are used.

addu addiumultu subudivu

Branch InstructionsBranch InstructionsBranchBranch instructions use a signed instructions use a signed 221616 offset field, offset field, hence (because addresses must be multiples of hence (because addresses must be multiples of 4, we can shift the 18 bit value right twice and 4, we can shift the 18 bit value right twice and just store a 16 bit value) can only jump just store a 16 bit value) can only jump 221717-1-1 addresses forward and addresses forward and 221717 backward. backward. JumpJump instructions can jump longer using a instructions can jump longer using a 2626-bit -bit offset field.offset field.

Not all MAL branch instructions are available in Not all MAL branch instructions are available in TAL. Only TAL. Only bltzbltz,, blez, bgez blez, bgez, , blezblez, , beqbeq, , bne, bne, andand b b are available. are available.

Subtle problems on branchingSubtle problems on branching

blt $11,$12,next sub $10,$11,$12bltz $10,next

Subtraction may causean overflow, e.g. if $11contains 4000000 and$12 contains -4000000 thenthe result is 8000000 whichhas no representation

MAL TAL

slt $10,$11,$12bne $10,$0,next

Sets $10 to 1 if the 2’s complementof the contents of $11 is less than the 2’s complement of the contentsof $12, else it sets $10 to 0. Thecomparison does not cause overflow

Load Address InstructionLoad Address InstructionTAL does not natively have the MAL TAL does not natively have the MAL la la instruction (though la still works in TAL).instruction (though la still works in TAL).

The assembler determines the address bound tolabel and divides it into two halves. The upper halfis loaded into R via lui and the lower half is ored intoR using the ori instruction.

la R, label lui R, highaddressori R, lowaddress

MAL TAL

la $12, 0x00030248 lui $12, 0x0003ori $12, 0x0248