Trigger System

LIU Zhen’anInst. of High Energy Physics, Beijing

Sep. 17 2002

OutlineGeneral Event Rate design rules trigger in data flow trigger block diagram

MDC triggerTOF triggerEMC subsystemGlobal TriggerPresent status and Outlook

General:Estimation of event rate

Fig:Backgrounds rate vs beam current At BESII/BEPC

Purpose of trigger system:to accept all interested eventsto rejects as much background as possible DAQ is sustainable

With good design of MDC,TOF and EMC trigger,

we estimate that

total trigger rate

= good event rate (~2000, LBEPCII = 1 1033 cm-2 s-1)

+ bhabha rate (~800,to be pre-scaled)

+ cosmic event rate (<200,from 1500)

+ beam background rate (<2000,from 13MHz)

= ~ 4000 Hz

General:design rules

Pipeline processing must be used in trigger Multi-bunches(93 in the ring) small bunch spacing(8ns) =>Latch-process-decision mode not possible in 8ns)

Latency of trigger signal necessary 3.2 s No dead time in trigger system

Most recent technology will be used

General: trigger system in data flowHardware trigger + software filterFEE signal splitted:

trigger + FEE pipeline

FEE pipeline clock 40MHz

Level 1(L1): 3.2 sFEE Control Logic checks L1 with FEE pipeline clockL1 YES:

moves pipeline buffer data

L1 No: overwritten by new data BESIII FEE pipeline and Data flow

Detector

switch

Level 1FEEpipeline

Readoutbuffer

Farms

Disk

Time Reference

0 s

3.2s

Ev.Filter

PowerPC

Block Diagram of BES III Trigger

Glo

bal T

rigge

r Log

ic

3.2 s

TOF

MDC

EMC

MU

DISC

DISC

Mu trackDISC

TrigSum

Track Finder

Etotal Energy

Hit/Seg Count

Track Seg. FinderDAQ

RF TTC

TC Sum

L1P

CLOCK

Track Match

Energy Balance

Cluster Counting

Nswires 9008N axial 4008N stereo 5000N layers 47Nlaxial 19Nlstereo 28N pivot cells ax 92/116/224/320/320N pivot cells st 48/72/160/192/224/256/288N spcells/sector 32/16

Wire

Lay

er

# of

sig.

in a

laye

r Supe

rLa

yer

# of

WL

in S

L

Sym

met

ry

Tota

l sig

.in

SL

# of

piv

otce

lls in

SL#

SPC

in S

L

# of

sig.

inSP

C

ST-1~4 40/48/56/64 SL-1 4 1/8 208 48 16 3

ST-5~8 64/72/80/88 SL-2 4 1/8 304 72 16 4, 5

AX-9~14 92/92/104/104 SL-3 4 1/4 392 92 32 2,3

AX-13~16 116/116/128/128 SL-4 4 1/4 488 116 32 3,4

ST-17~20 160*4 SL-5 4 1/32 640 160 32 5

ST-21~24 192*4 SL-6 4 1/32 768 192 32 6

AX-25~28 224*4 SL-7 4 1/32 896 224 32 7

ST-29~32 224*4 SL-8 4 1/32 896 224 32 7

ST-33~36 256*4 SL-9 4 1/32 1024 256 32 8

ST-37~40 288*4 SL-10 4 1/32 1152 288 32 9

AX-40~44 320*4 SL-11 4 1/32 1280 320 32 10

AX-45~47 320*3 SL12 3 1/32 960

Total 9008 12 9008 1992 320

MDC Trigger-Signals

MDC trigger schemes

GLT

TSF cards

On FEEGTSF

BLT

PTD/TF

90082008

Axial&

stereo

TRK CNT

•Scheme A(AX only):•TSF + TF + TRKCNT

•Scheme B(AX+ST):•TSF + GTSF +BLT+PTD+TRKCNT

TSF(Track Segment Finding)

4/4 group 3/4 groupB1 pivot cell:

A0*B1*C0*D0 A0*B1*C0+A0*B1*D0+A0*C0*D0+B1*C0*D0A0*B1*C0*D1 A0*B1*C0+A0*B1*D1+A0*C0*D1+B1*C0*D1A0*B1*C1*D1 A0*B1*C1+A0*B1*D1+A0*C1*D1+B1*C1*D1A0*B1*C1*D2 A0*B1*C1+A0*B1*D2+A0*C1*D2+B1*C1*D2A1*B1*C0*D0 A1*B1*C0+A1*B1*D0+A1*C0*D0+B1*C0*D0A1*B1*C0*D1 A1*B1*C0+A1*B1*D1+A1*C0*D1+B1*C0*D1A1*B1*C1*D1 A1*B1*C1+A1*B1*D1+A1*C1*D1+B1*C1*D1A1*B1*C1*D2 A1*B1*C1+A1*B1*D2+A1*C1*D2+B1*C1*D2

B2 pivot cell:A1*B2*C1*D1 A1*B2*C1+A1*B2*D1+A1*C1*D1+B2*C1*D1A1*B2*C1*D2 A1*B2*C1+A1*B2*D2+A1*C1*D2+B2*C1*D2A1*B2*C2*D2 A1*B2*C2+A1*B2*D2+A1*C2*D2+B2*C2*D2A1*B2*C2*D3 A1*B2*C2+A1*B2*D3+A1*C2*D3+B2*C2*D3A2*B2*C1*D1 A2*B2*C1+A2*B2*D1+A2*C1*D1+B2*C1*D1A2*B2*C1*D2 A2*B2*C1+A2*B2*D2+A2*C1*D2+B2*C1*D2A2*B2*C2*D2 A2*B2*C2+A2*B2*D2+A2*C2*D2+B2*C2*D2A2*B2*C2*D3 A2*B2*C2+A2*B2*D3+A2*C2*D3+B2*C2*D3

Each pivot cell Bi has 8 combinations each pivot cell Bi has 22 combinations

Pivot layer

Block Diagram of TSF

Xilinx FPGAPROM

ToNeighbour

REC

ORGATE

FromNeighbour

MDCHits

ToBLT

delay

INPUTRegister

TimeStretcher

l1

l2

l3

l4

3/4

CLB

Ideal case:

same cells,high Pt

Real case simulation

These data is used for TS Finding

TSF-Daughter Board Block Diagram

32Track

segment finding dr

iver

rece

iver

8 8stretcherProgramable delay

(LVPECL) (LVPECL/LVDS)

(LVPECL/LVDS)

(LVPECL/LVDS)

1-5

1-5

InputsOutputs

driv

erre

c

8Left

Neighbour

driv

er

8Left

Neighbour

Test and Control8

VME R/W

Commands

TSF Daughter Board

FPGA

1-3

1-3

GTSF(TSF grouping) and BLT(Binary Link Track)

BLT

Algorithm 2to1

OUTMem

INMem

ControlMem

DAQMem

ORgate

FromGTSF

To

GLT

BLT Long track

BLT Short track

AX-AX: N=3

AX-ST: N=3

ST-ST: N=5SPC:

SL1-2:1/16

SL5-11:1/32

PTD/TF Long track: Reference layer SL11 SL7,SL4 and SL3 4 / 4 or 3 / 4

PTD/TF Short track: Reference layer SL7 SL4 and SL3 3 / 3 or 2/3

Momentum Discrimination(PTD)/TF)PTD

Algorithm

FPGA

OUTMem

INMem

ORgate

FromTSF

To

GLT

DAQMem

LUT

PROM

SL11

SL7

SL4

SL3

FORTRAN code MDC structure + hits Trigger scheme

Tasks: Feasibility of trigger

scheme Trigger efficiency study Wire in-efficiency

influence study Backgrounds rejecting

ability study Production of

configuration data Track Segment Finding Track Finding/PTD

MDC trigger simulation

Trigger efficiency vs Pt and wire efficiencyConfiguration:

Pt > 120 MeV

tracks with Pt>130MeV + Weff>95%

TrigEff>95%

TSF:Ncomb=8

TSF:Ncomb=24

very good rejection of artificial cosmic rays 10cm away from vertax(100% when requires Nltrk_ptd>1)Rejection for beam backgd understudy. Result to be given after inputs from beam background simulation is avalable

MDC background rejection

TOF Trigger

48

LeadingEdge Disc

MeanTimer

LeadingEdge Disc

LeadingEdge Disc

LeadingEdge Disc

MeanTimer

L1i&(L2i-1or L2i+1)

TOF Trigger Master

TriggerTiming

Hit count andtopology logic

Disc.

TOFE

PMT PMT

PMT PMT

88TOFB

88TOFB

Disc.

48TOFE

EMC trigger

Barrel: θ×φ=56×144

= 8064

Endcap: 120 、 120 、 120 、 96 、

96 、 96 、 84 、 84 、 84

=1800

Basic trigger unit( trigger cell):

sum of 24 crystals outputs

EMC Simulation

<20% difference acceptableGain adjustment for each crystal+PD+PreAmp chain

Trigger Cell should be at least 4X4 =16 crystals.4X6=24 is taken

BESIII EMC trigger scheme

Gain Adj.

FEE 8ch sum

Track Matching scheme

TOF TrackDistribution

BEMC TrackDistribution

EEMC TrackDistribution

Input SignalsDelay

Input SignalsDelay

Input SignalsDelay

Input SignalsDelay

Matched Track Count

ToMain Trigger

Controller

Barrel TrackMatch

Eadcap TrackMatch

From TOFTrigger

From EEMCTrigger

From MDCTrigger

From BEMCTrigger

Global Trigger (GLT)

TOF-T

Reset

To TRG Sub-system

TriggerConditions

L1

ProgrammableInput Signal

Delay

ProgrammableTrigger Event

Decision

ProgrammablePre-scale

TriggerController

ClockProcessor

RF

Multi-Scaler

CHK

INIT

BUSY

Trigger EVT

E-TYPE

Trigger Signals

DistributionTo ElectronicsTDC

EMC-TEEMC-T

Inputs: sub-detector conditionsTime adjustmenttrigger tablePre-scaling of some event types

Trigger conditionsDetector Trigger

Conditionbits Comments

TOF Ntof1Ntof>=2Ntof-BBTOF-T

TOF hits number

Back to back hitsTiming

MDC Nltrk>=1Nltrk>=2Nltrk>=4Trk-BBlNltrk>=16MDC-zNStrk>=1NStrk>=2Trk-BBsNStrk>=16

Long Track number

Back to back tracksMany tracksZ>=25cm,COS>0.9Short Tracks number

EMC EMC-TEtot-lEtot-mEtot-hNcls>=1Ncls>=2ClsBB

Neutrino channel TimingEnergy >Thre-lEnergy >Thre-mEnergy >Thre-hCluster number

Back to back clusterEndCap EMC EEMC-T

EEtotEclsBBENcls>=1ENcls>=2

Endcap timingEndcap total EnergyBack to Back Energy at endcapEndcap cluster Number

MU MU-ORMU-BB

MU hits 'OR'Back to back MUOR

EndCap MU EMUOREMUBB

Endcap MU HitsEndcap back to back MU

MATCH NAtrk1NAtrk2ATRK-BBNBtrk1NBtrk2BTRK-BBNCtrk1NCtrk2CTrk-BB

Atrk=MDC Full track+TOF hit

Btrk=Atrk+EMC Clust

Ctrk=MDC Short track +Endcap EMC clust

39

Timing and handshaking with DAQCLK

L1

Tdead

Tlife

3s

BUSY

CHKTRG#=256 500ns

GEVT

Trigger pipeline clock fRF= 499.8 MHz f fRF /12 40MHz

Blocking of L1 of 3s required by Electronics fro peak finding#TRG error checking with CHK signal

Trigger scheme is drafted and will be refined.Trigger simulation goes well, will go further

with physics and backgrounds studyPipelined digital signal generator Designed for other module testing. Signal Sequence Programmable, signal length programmable Readback Check, TTL/LVDS high reliability

Experiment Board for VME Module Design Base on FPGA, to be used for testing other VME module’s functionality

Pipeline Clock Generater/Divider Experiment doneVMS BUS Display Prototyped. Manual Controller in Circuit designDigital programmable signal delay module is under debugging.MDC TSF board is modeled in FPGA with 32 inputs, and simulated, will begin board design

Present Status and Outlook(1)

Present Status and Outlook(2)Preliminary Design: Jul.2001 - End 2002Prototype of sub-system modules: Apr. 2002 - Dec.2003Test system and software:Oct.2002-Mar.2005Mass production: Oct.2003-Mar.2005Sub-system test: Jan. 2005-Sep.2005System integration/test Oct.2005-Dec.2005Cosmic-ray test:Jan.2006-May 2006Test run: End 2006

SummaryHardware trigger + software filter(on PC farm)L1 latency: 3.2 sPipeline clock: 40 MHzMonte Carlo simulation going well backgrounds, MDC, EMC trigger schemes studies

Design scheme draftedSome modules designedFurther/detailed designing undergoingWelcome collaboration domestic and abroad

Thanks!