Trends in CMOS Image Sensor

Technology and Design

Abbas El Gamal

Department of Electrical Engineering

Stanford University

2

CCD Image Sensors

• High QE and low dark current • Serial readout:

– Slow readout– Complex clocking and supply

requirements– High power consumption

• Cannot integrate circuitry on chip

3

CMOS Image Sensors

• Memory-like readout:– Enables high speed

operation– Low power consumption– Region of interest

• Integration• Enable new applications:

– Embedded imaging– High dynamic range – Biometrics– 3D imaging

Column Amplifiers / Caps

Column ADC / Mux

Row

Dec

oder

Pixel

Word

Bit

Reset

WordBit

4

Image Sensor Market

0

20,000

40,000

60,000

80,000

100,000

120,000

140,000

160,000

180,000

200,000

2001 2002 2003 2004 2005 2006

Year

Th

ou

sa

nd

s o

f U

nit

s

CMOS

CCD

Source: In-Stat/MDR, 8/02

5

CMOS Image Sensors Today

• Most sensors:– application-specific (optical mouse)– low end (PC, toys)

• Fabricated in old (0.6-0.35m) processes – limited integration

• Lower performance than CCDs: – Not used in digital cameras – Some exceptions (Canon D30/D60)

6

Technology and Design Trends

• Recent developments in:– Silicon processing – Color Filter Array and Microlens– Miniaturized packaging – Pixel design– Camera-on-chip

• Promise to broaden CMOS image sensor applicability and enhance their performance

7

This Talk

• Silicon processing:– Sub-micron CMOS process modifications– Triple-well photodetector

• Applications of modified processes:– Integrated color pixel– Multi-mega pixel sensors– Camera-on-chip integration– Pixel-level ADC – Digital Pixel Sensor

• High Frame Rate Sensors and Applications– High dynamic range

8

Scaling

• CMOS image sensors have benefited from scaling:– smaller pixels– higher fill factor– greater pixel functionality (PPS APS)

• Need 0.18m and below process for camera-on-chip integration

9

Problems with standard CMOS

• Low photoresponsivity -- shallow junctions, high doping

• High junction leakage -- STI, salicide

• High transistor leakage – off-current, thin gate oxide

• Poor analog circuit performance

Wong IEDM’96

10

Improving Photoresponsivity

• Deeper non-silicided lightly doped diode junctions (NW/PSUB, Ndiff/PSUB)

• High transmittance SiON materials

• Micro-lens and CFA integration

Color Filter Color Filter Color Filter

Microlens

Microlens Spacer

Microlens Overcoat

Color Filter Planarization Layer

SEM photograph of 3.3m pixel

Courtesy of TSMC

11

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

400 450 500 550 600 650 700 750 800

Qu

ant

um

Effi

cie

ncy

Wavelength (nm)

QE of 0.18m CMOS Photodiode

Courtesy of TSMC/Pixim

12

Reducing Leakage

• Junction leakage reduction:– Non-silicided double-diffused source/drain

implants– Hydrogen annealing– Pinned-diode

• Transistor leakage reduction:– Thick gate oxide transistors – Thresholds adjusted to increase voltage swing

• Leakages of sub 1nA/cm2 achieved

Wuu, IEDM, 2001

13

Drawbacks of Color Filter Array

• Loss of resolution

– aliasing

• Color cross-talk

• Increase microlens to photodetector distance

• Adds manufacturing steps and cost

14

Triple-Well Photodetector (Foveon)

Vn VnVp ResetReset

Row Select Row Select Row Select

Column Out Blue

Column Out Green

Column Out Red

Vcc Vcc Vcc

P Substrate

N Well

P Well

N Ldd

15

Triple-well

• Advantages:– No loss of resolution– Elimination of photon loss due to CFA– Elimination of color cross-talk

• Challenges:– Larger pixel size – less pixels than standard

sensors for same area– High spectral overlap between three color

channels– Fabrication and circuit operation ?

16

Spectral Response R

elat

ive

Res

po

nse

400 450 500 550 600 650 7000

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

GreenBlueRed

400 450 500 550 600 650 7000

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

Wavelength (nm)

Courtesy Foveon, Dick Lyon

Courtesy TSMC

Rel

ativ

e R

esp

on

se

Triple-Well

CFA

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Integrated Color Pixel

Light filters using

patterned metal layers

Catrysse, IEDM, 2001

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Enabling CMOS Technology

0.13 um 0.18 um 0.25 um

Smallest Period in CMOS Technology

400 500 600 700 800 900 1000

Wavelength (nm)

19

Integrated Color Pixel

• Using metal patterns above each photodetector, wavelength selectivity can be controlled

• Needs 0.13um process or multiple layers in 0.18 for good selectivity in the visible range

20

1D ICPs under imaging conditions

Pixels with increasinggap width

400 500 600 700 800 900Wavelength (nm)

0.5

0.45

0.4

0.35

0.3

0.25

0.2

0.15

0.1

Tra

ns

mit

tan

ce

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Multiple Layers in 0.18m CMOS

One layerTwo layers

400 500 600 700 800

Wavelength (nm)

0.6

0.5

0.4

0.3

0.2

0.1

0

Tra

ns

mit

tan

ce

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Layer Alignment in 0.18m CMOS

Two layers (Aligned)Two layers (Offset)

400 500 600 700 800

Wavelength (nm)

0.6

0.5

0.4

0.3

0.2

0.1

0

Tra

ns

mit

tan

ce

23

Scaling to 0.13m CMOS

0.18 m

0.13 m

0.18 m0.15 m0.13 m

400 500 600 700 800

Wavelength (nm)

0.6

0.5

0.4

0.3

0.2

0.1

0

Tra

ns

mit

tan

ce

24

Multi-Mega Pixel Sensors

• Memory-like readout of CMOS image sensors an advantage over CCDs (Kozlowski, et al, IEDM, 1999)

• Recent examples:– Kodak DCS Pro 14n (13.7 Megapixels)– Canon 1Ds (11 Megapixels)– Foveon 10X (10 Megapixel Triple-Well)

25

Camera-on-Chip Integration

PC-Board

Image

Sensor

Analog Proc & ADC

ASIC

PC-Board

ImageSensor

&

ADC

ASIC

Memory

Camera-on-chip

Memory

Today Future

26

Camera-on-chip Applications

27

Digital Pixel Sensor (DPS)

• Developed at Stanford (under PDC program)• ADC per pixel and all ADCs operate in parallel• Advantages:

– Better technology scaling (integration) than APS– Very high speed digital readout– No column read noise or Fixed Pattern Noise

ADC Memory

28

Sense Amplifiers and Latches

Ro

w A

ddr

ess

De

cod

er

Pixel Block

Pixel Block

Pixel Block

Pixel Block

Pixel Block

Pixel Block

Pixel Block

Pixel Block

Pixel Block

Pixel Block

Pixel Block

Pixel Block

Pixel Block

Pixel Block

Pixel Block

Pixel Block

Pixel Block

Pixel Block

Pixel Block

Pixel Block

Pixel Block

Pixel Block

Pixel Block

Pixel Block

Pixel Block

Pixel Block

Pixel Block

Pixel Block

Pixel Block

Pixel Block

DPS Block Diagram

29

High Speed DPS Chip

• 0.18m CMOS • 352 x 288 pixels (CIF)• 9.4m x 9.4m pixels• 37 transistors/pixel• 3.8 million transistors• 8 bit single slope ADC

and memory / pixel• 64 wide digital output

bus at 167 MHz

Kleinfelder, ISSCC, 2001

30

Pixel Schematic

Sensor Comparator 8-bit Memory

PG Tx

Reset V Reset

RAMPRead

Data I/O

Thick-oxide

31

ADC Operation

Input

Comp Out

Memory Loading

Memory Latched

Latched Value

Counter (Gray Code)

RAMP

0 01

RAMP Input

Comp Out

Gray Code Counter

Digital Out

Memory

8

8

+_

32

Video Sequence at 10,000 FPS

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Video Sequence at 700 FPS

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High Frame Rate Applications

• High frame rate enables new still and video imaging applications:– Dynamic range extension– Motion blur prevention– Optical flow estimation– Motion estimation– Tracking– Super-resolution

35

Multiple-Capture Single-Image

• Operate sensor at high frame rate• Process high frame rate data on-chip• Output data at standard rates

• Integration of sensor with embedded DRAM and DSPs enables low cost implementation (Lim‘01)

DSP

36

HDR via Multiple CaptureT 2T 4T

8T 16T 32T

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HDR Image

• Use Last-Sample-Before-Saturation Algorithm

38

HDR Example

Two captures of same high dynamic range scene

Courtesy of Pixim

39

DPS HDR Comparison

CCD1 CCD2

DPS

Courtesy of Pixim

40

HDR Image via Multiple Capture

41

Extending DR at Low Illumination

• For given exposure time, LSBS only extends DR at high illumination -- Read noise is not reduced• Increasing exposure time limited by motion blur

• Liu, ICASSP, 2001 describe an algorithm for extending DR at low illumination and preventing motion blur

Input Short exposure Long exposure

42

SNR and DR Enhancement

10-1 100 101 102 103

60

50

40

30

20

10

0

Weighted AveragingLast Sample Before SaturationSingle Capture

DR=47dB

DR=85dBSN

R (

dB

)

iph (fA)

DR=77dB

43

65 Image Capture Example0 ms 10 ms 20 ms

30 ms 40 ms 50 ms

44

High Dynamic Range Image

LSBS Estimation / Motion Prevention

45

Integration Beyond Camera-on-chip

Frame Memory

SIMD Processor

DPS Imaging

Array

Lim, SPIE, 2001

46

Summary•

47

Transistors Per Pixel

512

256

128

64

32

16

8

4

2

1 0.35 0.25 0.18 0.15 0.13 0.10 0.07 0.05

Technology (m)

# T

ran

sist

ors

5m pixel with 30% fill factor

ITRS Roadmap

48

Motivation

• PPS/APS do not scale well with technology:– Analog scaling problems– Sensitive to digital noise coupling

• Modified 0.18m CMOS enables camera-on-chip: – low cost and power consumption

• Digital Pixel Sensor: – Scales well and less sensitive to digital noise– Can operate at high frame rate

• Integration + high frame rate can be used to enhance sensor performance beyond CCDs

49

Current Pixel Architectures

• Passive Pixel (PPS):– Small pixel, large fill factor– Slow readout, low SNR– Reading is destructive

• Active Pixel (APS):– Larger pixel, lower fill factor– Faster readout, higher SNR– Most popular architecture

50

Micro-lens and CFA Integration

Color Filter Color Filter Color Filter

Microlens

Microlens Spacer

Microlens Overcoat

Color Filter Planarization Layer

SEM photograph of 3.3m pixel

Courtesy of TSMC